Sony CDP-M205 User manual

MICROFILM
CDP-M205/M305
Model Name Using Similar Machanism CDP-M201/M301
CD Mechanism Type CDM14-5BD29B
Base Unit Type BU-5BD29B
Optical Pick-up Type KSS-213B/K-N
COMPACT DISC PLAYER
Photo : CDP-M305
AEP Model
UK Model
CDP-M205/M305
E Model
CDP-M305
SERVICE MANUAL
SPECIFICATIONS

– 2 –
SAFETY-RELATED COMPONENTWARNING!!
COMPONENTS IDENTIFIED BY MARK !OR DOTTED LINEWITH
MARK !ON THE SCHEMATIC DIAGRAMS AND INTHE PARTS
LIST ARE CRITICALTO SAFE OPERATION.
REPLACE THESE COMPONENTS WITH SONY PARTS WHOSE
PART NUMBERS APPEAR AS SHOWN IN THIS MANUAL OR IN
SUPPLEMENTS PUBLISHED BY SONY.
MODEL NO.
CDP-M205
CDP-M305
COMPACT DISC PLAYER
SERIAL NO.
MADE IN JAPAN
AEP, UK model :
AC : 220–230V⁄50/60Hz 10W
E model :
AC : 110–120V, 220–240V⁄Adjustable 50/60Hz 10W
Specifications ........................................................................... 1
1. GENERAL
Location and Function of Controls .................................... 3
2. SERVICING NOTE.......................................................... 4
3. DISASSEMBLY ............................................................... 5
4. ELECTRICAL ADJUSTMENTS ................................... 6
5. DIAGRAMS
5-1. IC Pin Function........................................................... 7
5-2. Printed Wiring Boards – BD Section –......................11
5-3. Schematic Diagram – BD Section – ......................... 13
5-4. Schematic Diagram – Main Section – ...................... 17
5-5. Printed Wiring Boards – Main Section – .................. 21
6. EXPLODEDVIEWS
6-1. Main Section............................................................. 26
6-2. CD Block Section ..................................................... 27
6-3. Optical Pick-up Block Section (BU-5BD29B)......... 28
7. ELECTRICAL PARTS LIST ........................................ 29
TABLE OF CONTENTS
WARNING
To prevent fire or shock hazard, do
not expose the unit to rain on
moisture.
To avoid electrical shock, do not
open the cabinet. Refer servicing to
qualified personnel only.
The following caution label is
located inside of the unit.
This appliance is classified as a
CLASS 1 LASER product.
The CLASS 1 LASER
PRODUCT MARKING is
located on the rear exterior.
Laser component in this product is capable of emitting radiation
exceeding the limit for Class 1.
MODEL IDENTIFICATION

– 3 –
SECTION 1
GENERAL
LOCATION AND FUNCTION OF CONTROLS
This section is extracted from
instruction manual.
123456!§78
!∞ !¢ !£ !™ !¡ 0 9
9P(PAUSE) button
0·(PLAY) button
!¡ DISPLAY window
!™ REMOTE senser (CDP-M305 only)
!£ PEAK SEARCH button
!¢ REPEAT button
!∞ TIME button
!§ VOLTAGE selector (Singapore model)
1POWER switch
2CONTINUE button
3SHUFFLE button
4PROGRAM button
5DISK tray
6OPEN/CLOSE button
70/) (MANUAL SEARCH) buttons
=/+(AMS : AUTOMATIC MUSIC SENSOR) buttons
8p(STOP) button
1
2
3
4
5
6
7
8
!∞
!¢
!£
!™
!¡
0
9
9=/+(AMS : AUTOMATIC MUSIC SENSOR) buttons
0((PLAY) button
!¡ REPEAT button
!™ TIME button
!£ >10 (OVER 10) button
!¢ NUMBER buttons
!∞ CONTINUE button
1SHUFFLE button
2PROGRAM button
3CLEAR button
4CHECK button
5FADER button
6p(STOP) button
7P(PAUSE) button
80/)(MANUAL SEARCH) buttons
Front Panel
Remote Commander (CDP-M305 only)

– 4 –
SECTION 2
SERVICING NOTE
HOWTO OPENTHE DISCTRAYWHEN POWER SWITCHTURNS OFF
Caution : When you work, keep the set horizontal.
1 Turn in the direction of the arrow

– 5 –
SECTION 3
DISASSEMBLY
Note : Follow the disassembly procedure in the numerical order given.
3-1. PANEL, FRONT REMOVAL
2
5
5
6
Panel, Front
3 Wire (Flat type)
(21core)
Panel, Loading
3-2. CD MECHANISM SECTION REMOVAL
3
Wire (Flat type) (19 core)
2
4
CN151 (5P)
CD mechanism section
1 Three screws
(+BVTP 3x8 TYPE2 N-S)
Chassis assy
4 Two screws
(+BVTP 3x8TYPE2 N-S)
1 Turn in the direction
of the arrow
(Refer to page 4)

– 6 –
SECTION 4
ELECTRICAL ADJUSTMENTS
oscilloscope
BD board
TP (RF)
TP (VC)
CD SECTION
Note:
1. CD Block is basically constructed to operate without adjustment.
Therefore, check each item in order given.
2. UseYEDS-18 disc (3-702-101-01) unless otherwise indicated.
3. Use an oscilloscope with more than 10M impedance.
4. Clean the objectlensby an applicatorwith neutral detergent when
the signal level is low than specified value with the following
checks.
S Curve Check
oscilloscope
BD board
TP (FEO)
TP (VC)
Procedure :
1. Connect oscilloscope to test point TP (FEO).
2. Connect between test point TP (FOK) and Ground by lead wire.
3. Turn Power switch on.
4. Put disc (YEDS-18) in and turned Power switch on again and
actuate the focus search. (actuate the focus search when disc
table is moving in and out.)
5. Check the oscilloscope waveform (S-curve) is symmetrical be-
tweenAand B.And confirm peakto peak level within3 ± 1Vp-p.
S-curve waveform
within 3 ± 1 Vp-p
symmetry
B
A
6. After check, remove the lead wire connected in step 2.
Note: • Try to measure several times to make sure than the ratio of
A : B or B : A is more than 10 : 7.
• Takesweep time aslong as possibleand light up the bright-
ness to obtain best waveform.
Procedure :
1. Connect oscilloscope to test point TP (RF) on BD board.
2. Turned Power switch on.
3. Put disc (YEDS-18) in and playback.
4. Confirm that oscilloscope waveform is clear and check RF sig-
nal level is correct or not.
Note: Clear RF signal waveform means that the shape “◊” can be
clearly distinguished at the center of the waveform.
RF signal waveform
VOLT/DIV: 200 mV
TIME/DIV: 500 nS
level: 1.1 ± 0.3 Vp-p
E-F Balance (1Track Jump) check
oscilloscope
BD board
TP(TEO)
TP (VC)
Procedure:
1. Connect oscilloscope to test point TP (TEO) on BD board.
2. Turned Power switch on.
3. Put disc (YEDS-18) in to play the number five track.
4. Press the “P(Pause)” button.
5. Check the level B of the oscilloscope's waveform and theA (DC
voltage) of the center of the Traverse waveform.
Confirm the following:
• A/B x 100 = less than ± 7 (%)
1 track jump waveform Center of the waveform
B
A (DC voitage)
Symmetry
level : 500 mV ± 100 mVp-p
Adjustment Location:
[BD BOARD] (Conductor Side)
CNU102
TP
(FOK)
TP
(RF)
0V
IC102
IC101
IC103
TP
(TEO)
RF Level Check
TP
(VC)
TP
(FEO)TP
(GND)
CNU101

– 7 –
Pin No. Pin name I/O Description.
1 FEO O Focus error amplifier output.
Connected internally to the window comparator input for bias adjustment.
2 FEI I Focus error input.
3 FDFCT I Capacitor connection pin for defect time constant.
4 FGD I Ground this pin through a capacitor for cutting the focus servo high-frequency gain.
5 FLB I External time constant setting pin for boosting the focus servo low-frequency.
6 FE O O Focus drive output.
7 FE M I Focus amplifier inverted input.
8 SRCH I External time constant setting pin for generating focus search waveform.
9 TGU I External time constant setting pin for switching tracking high-frequency gain.
10 TG2 I External time constant setting pin for switching tracking high-frequency gain.
11 FSET I Peak frequency setting pin for focus and tracking phase compensation amplifier.
12 TA M I Tracking amplifier inverted input.
13 TA O O Tracking drive output.
14 SL P I Sled amplifier non-inverted input.
15 SL M I Sled amplifier inverted input.
16 SL O O Sled drive output.
17 ISET I Connect an external capacitance to set the current which determines the Focus search,
Track jump, and Sled kick heights.
18 VCC I Positive power supply.
19 LOCK I The sled overrun prevention circuit operates when this pin is Low (No pull-up resistance).
20 CLK I Serial data transfer clock input from CPU (No pull-up resistance).
21 XLT I Lach input from CPU (No pull-up resistance).
22 DATA I Serial data input from CPU (No pull-up resistance).
23 XRST I Reset input; resets at Low (No pull-up resistance).
24 C.OUT O Track number count signal output.
25 SENS1 O Outputs FZC, DFCT1, TZC, BALH, TGH, FOH, ATSC, and others according to the
command from CPU.
26 SENS2 O Outputs DFCT2, MIRR, BALL, TGL, FOL,and others according to the command from
CPU.
27 FOK O Focus OK comparator output.
28 CC2 I Input for the defect bottom hold output with capacitance coupled.
29 CC1 O Defect bottom hold output
Connected internally to the interruption comparator input.
30 CB I Connection pin for defect bottom hold capacitor.
31 CP I Connection pin for MIRR hold capacitor
MIRR comparator non-inverted input.
32 RF I I Input for the RF summing amplifier output with capacitance coupled.
33 RF O O RF summing amplifier output
Eye-pattern check point.
34 RF M I
RF summing amplifier inverted input.
The RF amplifier gain is determined by the resistance connected between this pin and
RFO pin .
35 RFTC I External time constant setting pin during RF level control.
36 LD O APC amplifier output.
37 PD I APC amplifier input.
38 PD1 I RF I-V amplifier inverted input.
39 PD2 I Connect these pins to the photo diode A+C and B+D pins.
40 FE BIAS I Bias adjustment of focus error amplifier
Leave this pin open for automatic adjustment (not used).
SECTION 5
DIAGRAMS
5-1. IC PIN FUNCTION
IC101 FOCUS/TRACKING/SLED SERVO RF AMP (CXA1992AR)

– 8 –
Pin No. Pin name I/O Description.
1 VDD – +5V power supply
2 VSS – Ground
3 LMUT O Lch “L” detection flog (Not used)
4 RMUT O Rch “L” detection flog (Not used)
5 ACDT O Test output (Not used)
6 CKOUT O Master clock divider output (Not used)
7 SQCK I Clock input for SQSO read out
8 SQSO O Serial output for Sub-Q 80bit
9 SENS O SENS signal output to CPU
10 DATA I Serial data input, supplied from CPU
11 XLAT I Latch input, supplied from CPU
12 CLOK I Serial data transfer clock input, supplied from CPU
13 SEIN I SENS input from IC101
14 CNIN I Numbers of track jump counted signal input
15 DATO O Serial data output to IC101
16 XLTO O Serial data latch output to IC101
17 CLKO O Serial data transfer clock output to IC101
18 SPOA I Micro computer demodulation interface (Input A)
19 SPOB I Micro computer demodulation interface (Input B)
20 SPOC I Micro computer demodulation interface (Input C)
21 SPOD I Micro computer demodulation interface (Input D)
22 XLON O Micro computer demodulation interface (Output) (not used)
23 FOK I Focus OK input
24 VDD – +5V power supply
25 VSS – Ground
26 MON O Output to control ON/OFF of spindle motor (Not used)
27 MDP O Output to control spindle motor servo
28 MDS O Output to control spindle motor servo (Not used)
29 LOCK O GFS is sampled by 460Hz
30 PWMI I Input to control the outside spindle motor
31 TES0 I Test pin (Connected to ground)
32 TES1 I Test pin (Connected to ground)
33 VPCO2 O Charge-pump output (Not used)
34 VPCO1 O Charge-pump output (Not used)
35 VCKI I VCO2 oscillator input (Not used)
36 V16M O VCO2 oscillator output (Not used)
Pin No. Pin name I/O Description.
41 F I F I-V and E I-V amplifier inverted input.
42 E I Connect these pins to photo diodes F and E.
43 EI – I-V amplifier E gain adjustment
(When not using automatic balance adjustment) (not used).
44 VEE – Negative power supply.
45 TEO O Tracking error amplifier output
E-F signal is output.
46 LPFI I Comparator input for balance adjustment
(Input from TEO through LPF).
47 TEI I Tracking error input.
48 ATSC I Window comparator input for ATSC detection.
49 TZC I Trackig zero-cross comparator input.
50 TDFCT I Capacitor connection pin for defect time constant.
51 VC O (VCC + VEE)/2 direct voltage output.
52 FZC I Focus zero-cross comparator input.
IC103 DIGITAL SIGNAL PROCESSOR (CXD2529Q)

– 9 –
Pin No. Pin name I/O Description.
37 VCTL I VCO2 control voltage input
38 PCO O Charge-pump output to master PLL
39 FILO O Filter output to master PLL
40 FILI I Filter input for master PLL
41 AVSS – Analog ground
42 CLTV I Control voltage input for VCO
43 AVDD – Analog power supply
44 RF I EFM signal input
45 BIAS I Asymmetry circuit constant current input
46 ASYI I Asymmetry comparate voltage input
47 ASYO O EFM full swing output (“L” =VSS, “H” =VDD)
48 ASYE I Asymmetry circuit ON/OFF (“L”=OFF, “H”=ON)
49 WDCK O D/A interface Word clock f=2fs (Not used)
50 LRCK O D/A interface LR clock output f=Fs
51 LRCKI I D/A interface LR clock input f=Fs
52 PCMD O D/A interface Serial data output
53 PCMDI I D/A interface Serial data input
54 BCK O D/A interface Bit clock output
55 BCKI I D/A interface Bit clock input
56 VSS – Ground
57 VDD – +5V power supply
58 GTOP – Not used
59 XUGF – Not used
60 XPLCK O EFM decoder PLL clock output
61 GFS O “H” Playback EFM sync and interpolation protection timming much
62 RFCK O Read Frame Clock signal output
63 C2PO – Not used
64 XRAOF O Internal RAM overflow detection signal output (Not used)
65 MNT3 – Not used
66 MNT1 – Not used
67 MNT0 – Not used
68 XTSL – Not used
69 FSTT O 2/3 divider output (Not used)
70 C4M O 4.2336MHz output(Not used)
71 DOUT O Digital audio signal output
72 EMPH O Playback disc output in emphasis mode
73 EMPHI I “H” =Input when de-emphasis ON
74 WFCK O Write Frame Clock signal output
75 SCOR O Sub-code sync output
76 SBSO O Sub-P through Sub-W serial output
77 EXCK I Clock input for SBSO read-out
78 VSS – Ground
79 VDD – +5V power supply
80 SYSM I System mute input (Connected to ground)
81 — – Not used
82 AVSS – Analog ground
83 AVDD – Analog power supply
84 AOUT1 O Lch analog output
85 AIN1 I Lch opamp input
86 LOUT1 O Lch line output
87 AVSS – Analog ground
88 XVDD – Master clock power supply
89 XTAI I X’tal oscillator circuit input
90 XTAO O X’tal oscillator circuit output

– 10 –
Pin No. Pin name I/O Description
1 GND – Ground.
2 RMIN I Remote control signal input.
3 GND – Ground.
4–7 NC – Not used (Open).
8 CLK O Serial clock output.
9 SENSE I Sense signal input from IC103 (CXD2529Q).
10 DATA O Serial data output.
11 SQCK O Sub Q clock output.
12 SUBQ I Sub Q data input.
13 SENSE2 I Sense signal input from IC101 (CXA1992AR)
14 NC – Not used (Open).
15 XLT O Serial latch output.
16–19 NC – Not used (Open).
20 LD OUT O Loadin motor control.
21 LD IN O Loadin motor control.
22 KEY 0 I Key input 0.
23 KEY1 I Key input 1.
24–27 NC – Not used (Open).
28 ADJ/AFADJ I Test mode terminal.
29 IN/OUT SW I CD tray IN/OUT switch.
30 RST I System reset terminal.
31 EXTAL O System oscillator (4.0 MHz).
32 XTAL I System oscillator (4.0 MHz).
33 VSS – Ground.
34–41 NC – Not used (Open).
42–62 S21–S1 O FL segment signal output.
63–67 1G–5G O FL grid signal output.
68 NC – Not used (Open).
69, 70 6G,7G O FL grid signal output.
71 VFDP – Pull down voltage (– 30V).
72 VDD – Power supply (+5V).
73,74 GND – Ground.
75 VDD – Power supply (+5V).
76,77 NC – Not used (Open).
78 SCOR I Sub code data request signal input.
79, 80 GND – Ground.
IC501 SYSTEM CONTROL (CXP82612-028Q)
Pin No. Pin name I/O Description.
91 XVSS – Master clock ground
92 AVSS – Analog ground
93 LOUT2 O Rch line output
94 AIN2 I Rch opamp input
95 AOUT2 O Rch analog output
96 AVDD – Analog power supply
97 AVSS – Analog ground
98 — – Not used
99 — – Not used
100 XRST I Sysyem reset input