Sony SS-HQ1 Supplement

- SS-HQ1 Application Notes -
Ver.1.0.0 January 7, 2005
i
SS-HQ1 Application Notes
Sony Corporation
Semiconductor Solutions Network Company

- SS-HQ1 Application Notes -
Ver.1.0.0 January 7, 2005
ii
CONTENTS
1. System Concept........................................................................................................................................1
1.1. Comparison of SS-HQ1 and SS-1M System Specifications ....................................................................1
1.2. New Functions in SS-HQ1 System ..........................................................................................................2
2. System Configuration...............................................................................................................................3
2.1. IC Configuration.......................................................................................................................................3
2.2. Clock Configuration .................................................................................................................................5
2.2.1. 1 clock / digital encoder system configuration ..................................................................................5
2.2.2. 2 clock / ECK master - MCK PLL system configuration.................................................................... 5
2.3. Output Configuration................................................................................................................................6
2.3.1. Analog Composite (YCMIX) Output System Configuration...............................................................6
2.3.2. Digital Output System Configuration (REC656, REC601) ................................................................6
3. Peripheral Circuits ....................................................................................................................................7
3.1. Initially Occupied Terminals .....................................................................................................................7
3.1.1. If No Valid Data in EEPROM ............................................................................................................7
3.2. Processing of Empty Pins........................................................................................................................8
3.2.1. Processing of Empty Pins in Each Mode..........................................................................................8
3.2.2. Processing of Empty Pins in case DAC is not used..........................................................................9
3.2.3. Processing of Empty Pins in case Internal EVR is not used.............................................................9
3.2.4. Processing of the power supply Pins for analog cells.......................................................................9
3.3. Oscillator Circuit Periphery ....................................................................................................................10
3.3.1. Clock oscillator circuit for 1 clock/digital encoder system ............................................................... 10
3.3.2. Clock oscillator circuit for 2 clock/ECK master MCK PLL ............................................................... 11
3.4. Reset Circuit ..........................................................................................................................................14
3.4.1. Outline ............................................................................................................................................ 14
3.4.2. Example Circuit and Timing Chart ..................................................................................................14
3.4.3. ICs Requiring Reset after Power-On ..............................................................................................15
3.5. EVR Connection ....................................................................................................................................16
3.5.1. Integrated EVR and Reserved Channels (AGC control)................................................................. 16
3.5.2. Communication Control with an External EVR ...............................................................................18
3.6. Noise Countermeasures ........................................................................................................................20
3.6.1. Introduction.....................................................................................................................................20
3.6.2. Countermeasures for Areas around Individual Devices..................................................................21
3.6.3. If Noise Occurs...............................................................................................................................24
3.7. External LPF..........................................................................................................................................25
3.7.1. Outline ............................................................................................................................................ 25
3.7.2. High Resolution and LPF................................................................................................................25
3.8. Example Characteristics and Circuit for External BPF...........................................................................25
3.8.1. Outline ............................................................................................................................................ 25
3.8.2. BPF Circuit Example ......................................................................................................................25
3.8.3. Example BPF Characteristics.........................................................................................................26
3.9. DAC Mode and YC-mix External Analog Circuit ....................................................................................27
3.9.1. DAC Mode...................................................................................................................................... 27
3.9.2. Circuit Configuration for Component Output...................................................................................28

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3.9.3. Circuit Configuration for Composite Output ....................................................................................29
3.10. Optical Filters .....................................................................................................................................30
3.10.1. Outline ........................................................................................................................................ 30
4. Parameter Configuration........................................................................................................................31
4.1. Communication Parameter Concept......................................................................................................31
4.1.1. Communication Category Concept.................................................................................................31
4.1.2. Communication Category Details ...................................................................................................31
4.2. Parameter Control by Built-in CPU ........................................................................................................32
4.2.1. Processing by CPU ........................................................................................................................32
4.2.2. CPU Main Processing and Firmware Applications..........................................................................32
4.3. Parameter Changes through Communication........................................................................................33
4.4. Saving Parameters to EEPROM............................................................................................................34
4.4.1. EEPROM Write Command and Address Map ................................................................................ 34
4.4.2. "EEPROM ALL WRITE" Command ................................................................................................ 35
5. Power-on Sequence................................................................................................................................36
5.1. Power-on Sequence ..............................................................................................................................36
5.1.1. DSP (CXD3172AR) Initialization Sequence....................................................................................36
5.1.2. Parameters Exclusively for Initialization .........................................................................................38
6. CCD Type Selection ................................................................................................................................39
6.1. Supported CCD type..............................................................................................................................39
6.2. List of Clock Configurations for Each CCD type ....................................................................................40
6.3. Important information on Wiring.............................................................................................................41
6.3.1. Drive Circuit Changes..................................................................................................................... 41
6.3.2. Clock System Changes ..................................................................................................................44
6.3.3. Frequency Response Changes ......................................................................................................44
6.3.4. Clock System Selection..................................................................................................................45
6.3.5. Wiring Changes When EEPROM is not written ..............................................................................46
6.4. CCD Primary Color Separation Matrix ...................................................................................................47
6.4.1. The Sequence of Parameter Changes ...........................................................................................47
6.4.2. Recommended Parameter’s Value ................................................................................................. 47
7. Power Supply ..........................................................................................................................................49
7.1. Supply Voltage.......................................................................................................................................49
7.1.1. Supply Voltage Accuracy ................................................................................................................49
7.1.2. Power Consumption ....................................................................................................................... 50
7.1.3. Power-on Sequence .......................................................................................................................50
8. Level Diagram..........................................................................................................................................51
8.1. SS-HQ1 Level Diagram .........................................................................................................................51
8.1.1. Signal Standard Level Diagram of Analog Output...........................................................................51
8.1.2. The Standard Level Diagram of Digital Outputs.............................................................................. 55
9. RS-232C Communication and Communication with Peripheral ICs...................................................57
9.1. RS-232C Communication ......................................................................................................................57
9.1.1. Interface .........................................................................................................................................57
9.1.2. Communication Procedure .............................................................................................................58
9.1.3. Communication Timing ...................................................................................................................59
9.1.4. Communication Format ..................................................................................................................60

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9.1.5. Serial Communication Prohibited Period ........................................................................................62
9.1.6. Important Note Regarding Communication ....................................................................................62
9.1.7. When Communication is Not Used.................................................................................................62
9.2. Communication with Peripheral ICs.......................................................................................................63
9.2.1. Connection of Communication Bus between DSP (CXD3172AR) and Peripheral ICs ...................63
9.2.2. Pin Connections for Serial Communication with Individual ICs ......................................................63
9.2.3. Serial Communication Speed and Timing....................................................................................... 64
9.2.4. Clock for Communication with Peripheral ICs ................................................................................67
10. Description of Operation of Each Function ..........................................................................................71
10.1. Port Driver Function ...........................................................................................................................71
10.1.1. Port Driver Function Description .................................................................................................71
10.1.2. Port Driver Setting Method..........................................................................................................72
10.1.3. Parameter Setting Instructions....................................................................................................76
10.1.4. Field Processing for Each Port Driver .........................................................................................79
10.1.5. Port Driver Initial Settings, Depending on Presence of EEPROM............................................... 79
10.1.6. Precautions for Port Driver Configuration ...................................................................................80
10.1.7. Port Driver Setting Example........................................................................................................81
10.1.8. Conditions for Disabling the Port Drivers ....................................................................................82
10.2. Y Signal Processing ...........................................................................................................................83
10.2.1. Y (Luminance Signal) Processing Flow.......................................................................................83
10.2.2. Pre-Block Signal Processing.......................................................................................................83
10.2.3. Y Signal Main Process ................................................................................................................86
10.2.4. High resolution mode ..................................................................................................................89
10.2.5. Aperture Compensation Function ...............................................................................................91
10.3. Chroma Signal Processing................................................................................................................. 93
10.3.1. Block diagram .............................................................................................................................93
10.3.2. Complementary Color Pixel Clipping ..........................................................................................94
10.3.3. Highlight Edge Color Compensation Function ............................................................................95
10.3.4. Using Four-Quadrant Independent Control.................................................................................96
10.3.5. False Color Suppress Function...................................................................................................98
10.4. Variable Gamma Function..................................................................................................................99
10.4.1. Gamma Curve Types ..................................................................................................................99
10.4.2. Y Variable Gamma ....................................................................................................................101
10.4.3. Y Gamma OFF..........................................................................................................................102
10.4.4. Y Gamma Curve Compression in Low Luminance Areas (S Gamma)......................................103
10.4.5. Chroma Variable Gamma..........................................................................................................104
10.4.6. Chroma Gamma OFF ...............................................................................................................106
10.4.7. Chroma Knee High Region Correction...................................................................................... 106
10.4.8. Chroma Signal Knee Clipping Process .....................................................................................107
10.5. OPD Window Setting and Display....................................................................................................108
10.5.1. Detection Window Setting Method ............................................................................................108
10.5.2. Detection Window Screen Display ............................................................................................ 110
10.6. AE operation .................................................................................................................................... 111
10.6.1. Sequence of Operation ............................................................................................................. 111
10.6.2. Mode......................................................................................................................................... 112

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10.6.3. Backlight Compensation ........................................................................................................... 116
10.6.4. Flickerless Function .................................................................................................................. 117
10.6.5. AE Hysteresis Function............................................................................................................. 118
10.6.6. AE Mechanical Iris Mode ..........................................................................................................120
10.6.7. ME Shutter Speed and AGC Gain Setting.................................................................................122
10.6.8. Detailed Description (Relationship of Modes and Parameters).................................................123
10.7. WB operation ...................................................................................................................................126
10.7.1. Sequence of Operation .............................................................................................................126
10.7.2. WB Operation ...........................................................................................................................127
10.7.3. ATW Operation Range..............................................................................................................131
10.7.4. ATW Related Parameters .........................................................................................................132
10.7.5. Anti Color-rolling mode ............................................................................................................. 139
10.8. Suppress..........................................................................................................................................143
10.8.1. Chroma Suppress .....................................................................................................................143
10.8.2. Aperture Correction Suppress...................................................................................................145
10.9. Mirror Function.................................................................................................................................147
10.10. Mask Function..................................................................................................................................148
10.10.1. Setting Procedure .....................................................................................................................148
10.10.2. Important...................................................................................................................................150
11. Functions for Adjustment.....................................................................................................................151
11.1. Adjustment Operation Mode ............................................................................................................151
11.1.1. The kind of Modes .................................................................................................................... 151
11.2. CCD blemish detection and compensation ...................................................................................... 156
11.2.1. CCD blemish detection method types....................................................................................... 156
11.2.2. Blemish detection and compensation parameters ....................................................................157
11.2.3. Static detection and compensation function .............................................................................. 158
11.2.4. Dynamic detection and compensation function.........................................................................165
11.2.5. False blemish generating function ............................................................................................173
11.3. Adjustment of TG Phase ..................................................................................................................174
11.3.1. Adjustment method of phase and drive ability .......................................................................... 174
12. Supporting Functions for applications ...............................................................................................179
12.1. Using Digital Output .........................................................................................................................179
12.1.1. Operation Modes with Digital Output ........................................................................................179
12.1.2. Digital Output Format................................................................................................................179
12.1.3. Digital Output Gain Setting........................................................................................................179
12.1.4. Ways to Use Digital Output ....................................................................................................... 180
12.1.5. Parameter Settings for Each Output Type................................................................................. 182
12.1.6. ITU-REC656 .............................................................................................................................183
12.2. Using external synchronization ........................................................................................................ 188
12.2.1. Synchronization for the SS-HQ1 system................................................................................... 188
12.2.2. Parameters used to set external synchronization .....................................................................189
12.2.3. Internal mode (INT)...................................................................................................................192
12.2.4. Line lock mode (LL) ..................................................................................................................195
12.2.5. Combined Use of INT and LL Modes in a Single System ......................................................... 199
12.2.6. VS Lock Mode (VSL) ................................................................................................................210

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12.2.7. Using the Internal SYNCSEP.................................................................................................... 212
12.2.8. VS Lock Mode (VSL-S).............................................................................................................213
12.2.9. VS Lock Mode (VSL-D).............................................................................................................215
12.2.10. VBS Lock Mode (VBSLHP).......................................................................................................217
12.2.11. VBS Lock Mode (VBSLHR) ...................................................................................................... 220
12.2.12. V Reset H Reset Mode (VRHR)................................................................................................222
12.2.13. I/O pin initial settings and preventive measures........................................................................224
12.2.14. Phase Adjustment Using the Shifter..........................................................................................225
12.3. Key Operations (Shifter)................................................................................................................... 227
12.3.1. AWB MODE and SFTUP/SFTDWN assignments ..................................................................... 227
12.3.2. Key Operations .........................................................................................................................227
12.3.3. External Synchronization Phase Adjustment through Key Operations......................................229
12.3.4. WB Gain Adjustment through Key Operations ..........................................................................230
12.4. When Using the External Microcomputer......................................................................................... 231
12.4.1. External Microcomputer-SS-HQ1 System Interface.................................................................. 231
12.4.2. Communication Protocol with External Microcomputers ...........................................................232
12.5. Pattern Generator (PG)....................................................................................................................239
12.5.1. Pattern generator (PG) Usage Method .....................................................................................239
12.5.2. Pattern settings .........................................................................................................................240
12.6. Sync Signal Output Setting Method ................................................................................................. 244
12.7. ADJUST Output ............................................................................................................................... 246
12.7.1. ADJUST Function .....................................................................................................................246
13. Appendix................................................................................................................................................248
13.1. External Synchronization Evaluation Results...................................................................................248
13.2. Operation Mode Control during Digital Output .................................................................................248
13.3. Tables: The parameters controlled by FW........................................................................................249

- SS-HQ1 Application Notes -
Ver.1.0.0 January 7, 2005
1
1. System Concept
1.1. Comparison of SS-HQ1 and SS-1M System Specifications
The SS-HQ1 system processes camera signals using a two-chip configuration consisting of a DSP
(CXD3172AR) and a digital CCD camera head amp (CXA2096N).
The following table summarizes the major differences between the SS-HQ1 and the specifications for our
SS-1M system, in which CXD2163BR is used as the DSP.
Table 1.1-1 Comparison of SS-HQ1 and SS-1M System Specifications
SS-HQ1 SS-1M
Supported CCDs 510H, 760H 360H, 510H, 720H, 760H
System Configuration
2-chip configuration
(AFE, DSP)
TG, V-Dr, and EVR are built into DSP
3-chip configuration
(AFE, TG/V-Dr, DSP)
(separate EVR is required)
Package LQFP 100pin LQFP 100pin
Horizontal resolution Excellent Good
Blemish detection
and compensation
Static & Dynamic detection,
maximum 32 points
Compensation only,
maximum 2 points (no detection)
Privacy masking Up to 8 locations can be set None
Mirror Function ○None
Port Driver 16 ports None
External synchronization LL/VS/VBS/VRHR LL/VS/VBS/VRHR
Pre-White Balance Adjustment Semi-auto Manual
Color rolling suppression Excellent None
Flickerless Shutter fixing + AGC modulation Shutter fixing only
System clock 1 clock permitted
(contains digital chroma encoder) 2 clock inputs
Internal ADC 10bit 8bit
Analog Output Composite video and
Y/C component video both supported Y/C component video only
Digital Output Conforms to ITU-Rec.601
Conforms to ITU-Rec.656 Conforms to ITU-Rec.601
AWB control Feed Forward method Feed Back method
External LPF Built into DSP
(performance ensured without LPF) Required

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Ver.1.0.0 January 7, 2005
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1.2. New Functions in SS-HQ1 System
The SS-HQ1 system contains the new functions listed in the following table.
Table 1.2-1 New Functions in SS-HQ1 System
New function Basic description Detailed description
High resolution mode Improves horizontal
resolution
Uses an aperture compensation generation
block to provide high resolution within
brightness signal processing
Color rolling-less mode Color rolling suppression
Allows a color rolling-only operation frame to
be set, in addition high precision, high speed
operation control
MODESEL control Automatic control of
system-related parameters
Automatically changes parameters which
have different settings depending on the
particular clock system
Internal burst separator Extracts burst signal for VBS
Lock
Extracts a burst signal from an incoming VBS
signal and outputs a phase comparison signal
for burst PLL
OUTGAIN function
Simultaneously increases
gain in chroma and
brightness signals
Simultaneously increases gain in chroma and
brightness signals using a single parameter (a
single switch)

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2. System Configuration
2.1. IC Configuration
The SS-HQ1 is the digital signal processing system for single CCD color camera.
The main LSIs are shown in Table 2.1-1.
Table 2.1-1 Main LSIs
Main LSIs Type name Outline Package
DSP CXD3172AR
1. Luminance and Chroma signal processing
2. Built-in digital encoder
3. Built-in microcontroller with AE/AWB
4. Built-in AE/AWB integral circuit
5. Built-in external synchronization function
6. Built-in 10bit A/D converter
7. Built-in 10bit D/A converter (Y/C 2ch)
8. Built-in PLL
9. Built-in Burst Separator and Sync Separator
10. Built-in EVR3ch
11. Built-in timing generator
12. Built-in vertical driver
13. Built-in serial communication circuit that supports
RS-232C and microcomputer communication
14. Built-in ITU REC656 conformity digital output function
15. Built-in ITU REC601 conformity digital output function
LQFP
100 pin
CDS/AGC CXA2096N
1. Correlated double sampling (CDS)
2. Built-in AGC circuit
3. Built-in interface circuit for A/D converter
SSOP
24 pin
*Please refer to the specification of each LSI about detail.
The peripheral ICs shown in Table 2.1-2 are needed to configurate the system in addition to the
above-mentioned 2LSIs.
Table 2.1-2 Peripheral ICs
Peripheral IC Type name (Brand name) Description Package
EEPROM
AK6480AF
(AKM)
or
BR9080AF-W
(ROHM)
8kbit EEPROM
(Note that other substitutions are
not possible due to limitations in
the communication format.)
SSOP
8pin
RS-232C
Transceiver
MAX3232CSE (Considerable)
(Maxim integrated Products, Inc.)
PC control I/F
External u-Com I/F
SO
16pin
System Reset PST9127N (Considerable)
(MITSUMI ELECTRIC CO.,LTD) Vth 2.7V SOT-25
5pin

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In SS-HQ1, 3ch EVRs are built-in in the camera DSP (CXD3172AR).
External EVRs shown in Table 2.1-3 are possible to use as peripheral IC.
Table 2.1-3 Peripheral IC (External EVR)
Peripheral IC Type name (Brand name) Description Package
External EVR MB88347LPFV
(Fujitsu Device Inc.)
8bit D/A Converter (built in 8sets)
(Power supply : 3.3V)
SSOP
16pin

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2.2. Clock Configuration
2.2.1. 1 clock / digital encoder system configuration
DSP can be operated by using only one clock in this system. The clock for driving system in DSP is generated
by supplying the clock for encoder (ECK).
Fig 2.2-1 Signal path of 1 clock / digital encoder system configuration
2.2.2. 2 clock / ECK master - MCK PLL system configuration
DSP can be operated by using both the clock (ECK) which is for encoder oscillated by the crystal and the
clock(MCK) which is for driving system oscillated by the PLL.
Fig 2.2-2 Signal path of 2 clock / ECK master - MCK PLL system
CCD CDS
AGC
CXA2096N CXD3172AR
EEPROM
Y analog output
Signal
Control signal
C analog output
Switches
TG
V-Driver
EVR
A/D D/A
D/A
DSP
PC
External
Microcomputer
RS-232C X'tal
ECK
RS-232C
Level Shift
CCD CDS
AGC
CXA2096N CXD3172AR
EEPROM
Y analog output
Signal
Control signal
C analog output
Switches
TG
V-Driver
EVR
A/D D/A
D/A
DSP
PC
External
Microcomputer
RS-232C X'tal
ECK
RS-232C
Level Shift MCK
VCOLPF
PCOMP

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2.3. Output Configuration
2.3.1. Analog Composite (YCMIX) Output System Configuration
Analog composite (YCMIX ) output is also possible in SS-HQ1.
Fig 2.3-1 Signal Path of Analog Composite (YCMIX) Output System
2.3.2. Digital Output System Configuration (REC656, REC601)
SS-HQ1 has two digital output modes. One is the output which is compliant with ITU REC656. The other is the
output which is compliant with ITU REC601.
Fig 2.3-2 Signal Path of Digital Output System
CCD CDS
AGC
CXA2096N CXD3172AR
EEPROM
YCMIX
analog output
Signal
Control signal
Switches
TG
V-Driver
EVR
A/D D/A
D/A
DSP
PC
External
Microcomputer
RS-232C X'tal
ECK
RS-232C
Level Shift
CCD CDS
AGC
CXA2096N CXD3172AR
EEPROM
Signal
Control signal
TG
V-Driver
EVR
A/D
DSP
PC
External
Microcomputer
RS-232C X'tal
ECK
RS-232C
Level Shift
digital output
Conforms to
・ITU-REC656
・ITU-REC601
format

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3. Peripheral Circuits
3.1. Initially Occupied Terminals
3.1.1. If No Valid Data in EEPROM
If there is no valid data in EEPROM (AK6480AF or BR9080AF-W), data is read from internal memory of
CXD3172AR. At this time parameters are assigned from CXD3172AR internal memory for the terminals
indicated in the following table (the port driver). Thus, setup does not apply user-designated settings.
Table 3.1-1 Initially Occupied Terminals
Pin Name Pin No Parameter Name Description
P0 91
P1 92
P2 93
AWBMODE AWB operation mode switching
P3 94 CRLESSON Switches anti-color rolling mode ON and OFF
P4 96 BLCOFF Switches backlight compensation ON and OFF
P5 97 AEREF Switches AE reference ON and OFF
P6 98 NORMFLC Switches the flickerless function ON and OFF
P7 99 AGCMAX Switches the AGC maximum value ON and OFF
P8 76 AEME Switches between AE and ME
P9 77 AESHUT
Switches the electronic shutter fixed speed ON
and OFF
P10 78 SGMODE0 Switches between INT and LL
P11 79 GAMSEL Switches the gamma parameters
P12 80
P13 82
P14 83
P15 84
MODESEL DSP operation mode switching

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3.2. Processing of Empty Pins
3.2.1. Processing of Empty Pins in Each Mode
Perform pin processing for the CXD3172AR depending on each mode as follows.
Table 3.2-1 Processing of Empty Pins in Each Mode
Internal sync External sync
Pin Name Pin
No 1 clock
digital
encoder
2 clock
ECK master
MCK PLL
Line
Lock VS Lock VBS Lock VRHR Digital
output
TEST1 12 GND GND GND GND GND GND GND
PCOMP 42 OPEN * * * * * *
MCK 43 GND * * * * * *
S0 44 3.3V 3.3V * * 3.3V * *
S1 46 OPEN OPEN OPEN * OPEN * *
S2 47 OPEN OPEN OPEN OPEN * * OPEN
S3 48 OPEN OPEN OPEN OPEN * OPEN OPEN
PCK 51 OPEN OPEN OPEN OPEN OPEN OPEN OPEN
VCTRLIN 53 GND GND GND GND GND GND GND
CPOUT 54 GND GND GND GND GND GND GND
EXVIDEOY 57 3.3V 3.3V 3.3V * * 3.3V 3.3V
EXVIDEO 58 3.3V 3.3V 3.3V 3.3V * 3.3V 3.3V
TEST2 61 GND GND GND GND GND GND GND
TEST3 62 GND GND GND GND GND GND GND
DCK 90 OPEN OPEN OPEN OPEN OPEN OPEN *
* Terminals used in each mode (see separate explanation)

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3.2.2. Processing of Empty Pins in case DAC is not used
When Y-DAC and C-DAC are not used by YCMIX output (DACMODE=0[h]), digital output, etc. Perform pin
processing for the CXD3172AR as follows.
Table 3.2-2 Processing of Empty Pins in case C-DAC is not used
Pin Name Pin No When C-DAC is not used
IOC 67
VGC 69 3.3V
VREFC 68
IREFC 70 GND
Table 3.2-3 Processing of Empty Pins in case Y-DAC is not used
Pin Name Pin No When Y-DAC is not used
IOY 75
VGY 72 3.3V
VREFY 73
IREFY 71 GND
3.2.3. Processing of Empty Pins in case Internal EVR is not used
When Internal EVR are not used. Perform pin processing for the CXD3172AR as follows.
Table 3.2-4 Processing of Empty Pins in case Internal EVR is not used
Pin Name Pin No When Internal EVR is not used
EVR0 63
EVR1 64
EVR2 66
Connects with GND
through 0.1uF capacitor.
3.2.4. Processing of the power supply Pins for analog cells
When an analog cell is not used. Perform Processing of the power supply Pin for analog cells as follows.
Table 3.2-5 Processing of the power supply Pins for analog cells
Pin Name Pin No When Analog Cells is not used
AVD4 55
AVD5 56
AVD6 74
3.3V
AVS4 52
AVS5 59
AVS6 65
GND

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3.3. Oscillator Circuit Periphery
3.3.1. Clock oscillator circuit for 1 clock/digital encoder system
Providing an encoder clock (ECK) for the CXD3172AR enables internal generation in the CXD3172AR of the
clock that drives the system.
Fig 3.3-1 shows the composition of an oscillator circuit using X'tal.
Fig 3.3-1 X'tal Oscillator Circuit Configuration (Evaluation Board)
Table 3.3-1 X'tal Oscillating Frequency
Number of pixels TV System X1
NTSC 38.13986MHz
510H PAL 37.87500MHz
NTSC 28.63636MHz
760H PAL 28.37500MHz
CXD3172AR
87
ESCO
86
ESCI
1M
X1 20p
1000p
ECK
88
20p
150
43
MCK

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3.3.2. Clock oscillator circuit for 2 clock/ECK master MCK PLL
Operate the CXD3172AR with two clocks: the encoder clock (ECK), oscillated by X'tal, and the driving system
clock (MCK), oscillated by PLL.
Fig 3.3-2 shows the configuration and evaluation board circuit constants (Table 3.3-2) for a clock oscillator
circuit for MCK PLL using X'tal.
Fig 3.3-2 Configuration of Clock Oscillator Circuit for 2 Clock
/ECK Master MCK PLL Using X'tal Oscillation
Table 3.3-2 Evaluation Board Circuit Constants
R1
TV System X1 VH=15V VH=12V C1
NTSC 0.01uF
PAL See Table 3.3-1 56k 47k 1uF
CXD3172AR
42
43
PCOMP MCK
10k
10k
C1
1M
10k
2SC2412
10k
1u
R1
VH
100k 1000p
MA2Z365
1M
X2
6p 12p
1000p
87
ESCO
86
ESCI
1M
X1 20p
1000p
ECK
88
20p
150
TC7SU69F
TC7SA04F

- SS-HQ1 Application Notes -
Ver.1.0.0 January 7, 2005
12
Fig 3.3-3 shows the configuration and evaluation board circuit constants (Table 3.3-3) for a clock oscillator
circuit for MCK PLL using LC.
Fig 3.3-3 Configuration of Clock Oscillator Circuit for 2 Clock
/ECK Master MCK PLL Using LC Oscillation
Table 3.3-3 Evaluation Board Circuit Constants
R1
TV System VH=15V VH=12V
NTSC
PAL 56k 47k
CXD3172AR
42
43
PCOMP MCK
10k
10k
3.3u
1M
10k
2SC2412
10k
1u
R1
VH
100k 1000p
1M
3.3u
20p 10p
1000p
3.3u
100 12p
87
ESCO
86
ESCI
1M
X1 20p
1000p
ECK
88
20p
150
TC7SU69F
TC7SA04F
MA2Z365

- SS-HQ1 Application Notes -
Ver.1.0.0 January 7, 2005
13
These three figures give examples of oscillator circuits introduced with the SS-HQ1 evaluation board: Fig 3.3-1,
Fig 3.3-2, and Fig 3.3-3. The circuit constants presented here has been verified in operation using a Sony
evaluation board equipped with the crystal oscillator shown in Table 3.3-4. Understand that no performance
guarantee is implied for different board layouts, component selection, or temperature characteristics.
For VCO circuits, LC and X'tal oscillation circuits are available. Choose the one that suits your application.
Table 3.3-4 Components Used on the Evaluation Board
Component name Manufacturer Model Frequency Load capacitance
28.63636MHz
28.37500MHz
38.13986MHz
Crystal oscillator RIVER ELETEC
CORPORATION HC-49/U03
37.87500MHz
12pF
Variable capacitance diode Panasonic MA2Z365 - * 3.4pF to 36pF
*: The diode capacity is the minimum value when 17V to 2V reverse voltage is applied.

- SS-HQ1 Application Notes -
Ver.1.0.0 January 7, 2005
14
3.4. Reset Circuit
3.4.1. Outline
This circuit performs system reset to enable stable operation when the CXD3172AR and peripheral ICs start
up after power is supplied.
However, problems may also be caused by a transient power supply. For a reliable way to avoid such
problems, add a circuit that meets the following conditions.
3.4.2. Example Circuit and Timing Chart
The sample reset circuit is shown in "Fig 3.4-1 Example Reset Circuit," and the timing chart is shown in Fig
3.4-2.
If the 3.3V voltage supply surges to exceed 2.7V after power is supplied or other events, set the CXD3172AR
XRST terminal to Low (at least 500ns) and be sure to reset it. Additionally, if the 3.3V power supply falls under
2.7V, set the XRST terminal to Low and be sure to reset it.
* The guaranteed voltage for DSP operation is 3.0 to 3.6V. For details refer to the product specifications.
Fig 3.4-1 Example Reset Circuit
CXD3172AR
XRST
RESET SW 100pF
4
VOUT
PST9127N
3
1 5
2
GND
SUB
NC VCC
RESET IC
MITSUMI ELECTRIC CO.,LTD.
4.7k
11
+3.3V