Sperry Rand UNIVAC 9200 Series User manual

I
PROGRAMMEF~
REFEREN
PROCESSOR
AND
STORAGE
UP-7546 Rev. 1

This document contains the latest information available at the time of publication. However, the Univac
Division reserves the right to modify or revise its contents. To ensure that you have the most recen~
information, contact your local Univac Representative.
UN
IVAC is a registered trademark of the Sperry Rand Corporation.
©1970
, 1973 -SPERRY RAND
CORPORATION
PRINTED IN U.S.A.

UP-7546
Rev. 1
UP.NUMBER
Section
-
Cover/Disclaimer
PSS
Contents
1
2
3
Appendix A -
Appendix B
Appendix C
Appendix D
Index
Page
Number
1
1
thru 5
1
thru 17
1
thru 34
1
thru 21
1 thru 3
1
thru 3
1
thru 4
1
1
thru 11
Update
Level
UNIVAC 9200/920011/9300/9300 II
PROCESSOR AND STORAGE
PAGE STATUS SUMMARY
ISSUE: UP-7546 Rev. 1
Section
Page
Number Update
Level
PSS-l
PAGE REVISION PAGE
Section
Page
Number
Update
Level

UP-7546
Rev. 1
UNIVAC 9200/9200 11/9300/9300 II
PROCESSOR AND STORAGE
PAGE STATUS SUMMARY
CONTENTS
1. INTRODUCTION
1.1. GENERAL
1.2. SYSTEM CONFIGURATION
1.1, COMPONENT DESCRIPTION
1.3,,1. Processor
1.3.1.1. Main Storage
1.3.1.2. Control
1.3.1.3. Arithmetic
1.3.1.3.1. Multiply, Divide, and Edit
1.3.,1.3.2. Subtraction by Two's Complement Method
1.3.1.4. Input/Output
1.3.1.4.1. Multiplexer Channel
1.3,,1.4.2. Selector Channel
1.3.,2. Printer
1. 3 .. 2.1. 300 L PM P ri nt Speed
1.3.2.2. 120 Print Positions
1.3.2.3. Print Position Expansion
1.3.2.4. 132 Print Positions
1.3.2.5. Variable Speed Printing
1.3.2.6. 8 LPI Print Spacing
1.3.2.7. Form Alignment
1.3.2.8. High Speed Numeric Print
1.4. DATA FORMATS AND CODES
1.4.1. Binary Number Representation
1.4.2. Hexadecimal Representation
1.4.3. Decimal Number Representation
1.4.3.1. Sign Bits
1.4.4. Character Representation
1.4.5. Parity Verification
1.4.6. OP Codes
1.4.7. Logical Information
Contents
SEC TION:
CONTENTS
1-1
1-4
1-9
1-9
1-9
1-9
1-9
1-9
1-10
1-11
1-11
1-12
1-12
1-12
1-13
1-13
1-13
1-13
1-13
1-13
1-13
1-14
1-15
1-15
1-16
1-16
1-17
1-17
1-17
1-17
1
P AGE:

UP-7546
Rev. 1
UNIVAC 9200/9200 11/9300/9300 II
PROCESSOR AND STORAGE
2. PROCESSOR UNIT
2.1. MAIN STORAGE
2.1.1. Privileged and Low Order Storage
2.1.2. Storage Boundaries
2.1.3. Parity Checking
2.1.4. Interrupts
2.2. PROCESSOR CONTROL
2.2.1. Program State Control
2.2.1.1. Processor Program State Control Words (Bytes 0-3)
2.2.1.2. Input/Output Program State Control Word (Bytes 16-19)
2.2.2.
Restricted Alter/Display and Operator Request (Bytes 4,5)
2.2.3.
Machine Instruction Register (Bytes 6-11)
2.2.4.
Restart Instruction Register (Bytes 22-25)
2.2.5.
Spec i al Statu s (Bytes 29-31)
2.2.6.
Processor Program Register (Bytes 32-47) and Input/Output Program
Registers (Bytes 48-63)
2.2.7.
Device Status (Byte 66) and Device Address (Byte 67)
2.2.8. Buffer Control Words (Bytes 68-127)
2.2.8.1. Multiplexer
Subchannel BCW
2.2.8.2. Device Control Subchannel Numbering
2.2.8.3. Buffer Control Word Location
2.2.8.4. Additional Nonshared Subchannel Device Addresses
2.2.9. Printer Image Area (Bytes 128-259)
2.2.10. Printer Control
2.2.10.1. P ri nter Instru ctions
2.2.10.2. Printer Buffer Control Word
2.2.10.3. Issue and Execute
2.2.10.4. status Register
2.2.10.5. Interrupt Requests
2.2.10.6. Printer Status Byte
2.2.11. Input/Output Control
2.2.12. Operator-Ini tiated Functions
2.2.12.1. Load Cycle
2.2.12.2. Alternate Execute and Staticize Cycle
2.3. MUL TIPLEXER CHANNEL CONTROL
2.3.1. Multiplexer Channel Instructions
2.3.2. Multiplexer Channel Buffer Control Word
2.3.3. Multiplexer Channel Status Byte
2.3.4. Condition Code
2.3.5. Alternate BCW Format
2.3.5.1. Data Di rection Control
2.3.6. Polling
2.3.6.1. Priority of Interrupt
2.3.7. Special Channel Instructions and Interrupts
2.3.7.1. Operator Interrupt
2.3.7.2. Alternate (L T) Summary Interrupt
2.3.7.3. One-Second Interrupt
2.3.7.4. Summary of Special Channel Instructions
2.3.8. Channel Checking
2.3.8.1. Interface Error FI ip-Flop
2.3.8.2. Device Address Parity
2.3.8.3. Parity Error Flip-Flop
Contents
SECTION:
2-1
2-1
2-2
2-3
2-3
2-4
2-6
2-6
2-7
2-7
2-7
2-8
2-8
2-8
2-8
2-8
2-9
2-9
2-9
2-9
2-10
2-10
2-10
2-10
2-11
2-12
2-12
2-13
2-13
2-14
2-15
2-15
2-15
2-15
2-16
2-16
2-17
2-17
2-18
2-19
2-19
2-20
2-20
2-20
2-21
2-21
2-21
2-22
2-22
2-22
2-22
2
P .A;GE:

UP-7546
Rev. 1
UNIVAC 9200/9200 11/9300/9300 II
PROCESSOR AND STORAGE
2.4. SELECTOR CHANNEL CONTROL
2.4.1. Channel Addressing
2.4.1.1. Selector Channel Address Format
2.4.1.2. Mu Itip lexer Channel Address Format
2.4.2. Processor Lock-Out
2.4.3. Concurrent Operations
2.4.4. Command Chaining
2.4.!J. Execute I/O and Test I/O Instructions
2.4.6. I/O Commands
2.4.7. Transfer-in-Channel (TIC) Command
2.4.8. Condition Code (CC)
2.4.9. Channel Address Word (CAW) and Diagnostic Interrupt
2.4.10. Channel Command Word (CCW)
2.4.11. Device Status
2.4.12. Channel Status Word (CSW)
2.4.13. Channel Check i ng
2.4.14. Special Selector Channel Instructions
2.5. DATA TRANSLATION
2.5.1. Card Code Translation (SO-Column Card)
2.5.1.1. Card Code Image Mode (SO-Column Card)
2.5.2. Card Code Translation (90-Column Card)
2.5,2.1. Card Code Image Mode (90-Column Card)
2.5.3. Internal Codes
3. INSTRUCTIONS
3.1. GENERAL
3.2. INSTRUCTION FORMAT
3.2.1. Register and Indexed Storage Operation (RX)
3.2.2. Storage and Immediate Operand Operation (SI)
3.2.3. Storage-to-Storage (SS1)
3.2.4. Storage-to-Storage (SS2)
3.3. INSTRUCTION REPERTOIRE
3.3.1. Binary Instructions and Overflow
3.3.1..1. Store Halfword Instruction (STH)
3.3.1.2. Load Halfword Instruction (LH)
3.3.1.3. Compare Halfword Instruction (CH)
3.3.1.4. Add Immediate Instruction (AI)
3.3.1.5. Add Halfword Instruction (AH)
3.3.1.6. Subtract Halfword Instruction (SH)
3.3.2. Logical Instructions
3.3.2.1. Test Under Mask Instruction (TM)
3.3.2.2. Move Immediate Instructions (MVI)
3.3.2.3. AND Immediate Instruction (NI)
3.3.2.4. Compare Logical Immediate Instruction (CLI)
3.3.2.5. OR Immediate Instruction (01)
3.3.2.6. Halt and Proceed Instruction (HPR)
3.3.2.7. Move Numeric Instruction (MVN)
3.3.2.S. Move Character Instruction (MVC)
3.3.2.9. AND Character Instruction (NC)
3.3.2.10. Compare Logical Character Instruction (CLC)
3.3.2.11. 0R Character Instructi on (0 C)
Contents
SECTION:
2-23
2-23
2-23
2-23
2-23
2-24
2-24
2-24
2-25
2-25
2-26
2-26
2-27
2-2S
2-30
2-30
2-31
2-31
2-31
2-32
2-33
2-34
2-34
3-1
3-6
3-6
3-6
3-6
3-7
3-7
3-S
3-9
3-9
3-9
3-9
3-10
3-10
3-10
3-10
3-10
3-10
3-10
3-11
3-11
3-11
3-11
3-11
3-11
3-12
3
PA G E:

Rev. 1
UNIVAC 9200/9200 11/9300/9300 II
PROCESSOR AND STORAGE
Contents
SECTION:
4
PAGE:
UP-7546L
----------------------------------~~--------~----------~-----------
3.3.2.12. Translate Instruction (TR)
3.3.2.13. Edit Instruction (ED)
3.3.3. Decimal Instructions
3.3.3.1. Move with Offset Instruction (MVO)
3.3.3.2. Pack Instruction (PACK)
3.3.3.3. Unpack Instruction (U N PK)
3.3.3.4. Zero Add (Packed) Decimal Instruction (ZAP)
3.3.3.5. Compare (Packed) Decimal Instruction (CP)
3.3.3.6. ADD (Packed) Decimal Instruction (AP)
3.3.3.7. Subtract (Packed) Decimal Instruction (SP)
3.3.3.8. Multiply (Packed) Decimal Instruction (MP)
3.3.3.9. Divide (Packed) Decimal Instruction (DP)
3.3.4. Bran ch Instructi on s
3.3.4.1. Branch-on-Condition Instruction (BC)
3.3.4.2. Branch and Link Instruction (BAL)
3.3.5. State Control (Privileged and Special) Instructions
3.3.5.1. Load Program State Control Instruction (LPSC)
3.3.5.2. Store Program State Control Instruction (SPSC)
3.3.5.3. Supervisor Request Call Instruction (SRC)
3.3.6. Input/Output Instruction
3.3.6.1. Execute I/O Instruction (XIO F)
3.3.6.2. Test I/O Instruction (TID)
APPENDIXES
A, INSTRUCTIONS, FORMATS, CODES
B. HEXADECIMAL TABLES
C. CHARACTER GRAPHIC SET CODES AND PRINTER SYNCHRONIZER CODE
D. POWERS OF 2; POWERS OF 16
INDEX
TABLES
1-1. Configurations for UNIVAC 9200 and 9300 Systems Processors
1-2. Hexadecimal-Decimal Conversion
3-1. Instruction Mnemonics in Alphabetical Sequence
3-2. Instructions Grouped by Functional Type
3-3. Instructions Grouped by Format
3-4. Instructions in Sequence of Hexadecimal Codes
3-12
3-12
3-13
3-13
3-14
3-15
3-15
3-15
3-15
3-16
3-16
3-18
3-20
3-20
3-20
3-20
3-20
3-21
3-21
3-21
3-21
3-21
1-4
1-15
3-2
3-3
3-4
3-5

UP-7546
Rev. 1
FIGURES
1--1.
1-- 2.
1-3.
1--4.
1-5.
1--6.
2-1.
2--2.
2--3.
2--4.
2 --5.
2--6.
3--1.
UNIVAC 9200/9200 11/9300/9300 II
PROCESSOR AND STORAGE
UNIVAC 9200/9200 11/9300/9300 II Systems Processor
UN IV AC 9200/9200 11/9300/9300 II Systems Processor Block 0 iagram
Configuration for UNIVAC 9200 System Processor
Configuration for UNIVAC 9200 II System Processor
Configuration for UNIVAC 9300 System Processor
Configuration for UNIVAC 9300 II System Pr,ocessor
Main Slo rag e 0rg ani zat ion
Organization of First 260 Bytes of Storage
Compressed Code for 80-Column Card
Image Mode for 80-Column Card
Card
Code Tran.slation for 90-Column Card
Image Mode for 90-Column Card
Instruction Formats
Contents
5
SECTION:
P AG E:
1-1
1-2
1-5
1-6
1-7
1-8
2-2
2-5
2-32
2-33
2-33
2-34
3-7

UP-7546
Rev. 1
UNIVAC 9200/9200 11/9300/9300 II I 1 I
____ P_R_O_C_E_SS_O_R_A_N_D_S_T_O_R_A_G_E _____ ~ ____ ~~.~~
1. INTRODUCTION
Figure 1-1. UNIVAC 9200/9200 1//9300/9300 /I Systems Processor
1.1. GENERAL
This document contains a description of the UNIVAC 9200/9200 11/9300/9300 II Systems
processor with optional features pertaining to expans ion, internal operation of the processor,
data and program information presentation, instruction repertoire and coding, and constant
and s1torage definitions.
It should be noted that only one processor is detailed herein with the specific differences
between each noted as required. The four system processors are identic all in appearance.
The configuration is shown in Figure 1-1.
This manual is divided into the following basic sections:
• Introduction
• Processor Unit
• Instructions
• Appendix
The appendix contains tables, charts, and diagrams as a convenience to the programmer
and field engineer. The fact that many examples and explanations are given in terms of
punched card input does not imply that any other of the usual input methods may not be
used.

Upa'7546
Rev. 1 1
L UNIVAC
9200/9200 11/9300/9300 II
PROCESSOR AND STORAGE
SECTION:
PAGE:
The UNIV AC 9200/9200 11/9300/9300 II Systems processor shown in Figure 1--1, is
a byte-oriented data processor integrated with an attached printer and an optional
externally-connected card punch and card reader (basic peripherals). A wide range
of other peripheral devices may be incorporated either initially by replacing one or
more of these basic peripheral devices, or later, by adding to the system.
Two major functions of the processor are decoding and storage. The decoding func-
tion analyzes each instruction to determine required operations and the location of
needed information. An instruction containing labels of data in storage is decoded
to find the addresses and lengths of the operands (data to be processed), as well as
the particular operation that is to be performed on the data. The processor then re-
sponds to the instruction by using generated control signals. The storage (memory)
portion of the processor stores the data and instructions required by the program in
addressable locations that are easily accessible to the program.
The major components of the UNIV AC 9200/9200 11/9300/9300 II Systems processor
are shown in Figure 1-2.
CONTROL
TO I/O
DEVICE
DATA AND
STATUS
FROM I/O
DEV ICE
~
....---
r----------,
I
STORAGE
PLATED: ADR I
I
UNIT
I
STORAGE
WIRE I S.
~
ADDR ESS
I
~
STORAGE I REG.
BUFFER
r- - - - -'- - - - I
I STOR.
DATA REG. I
(MA)
L_
-
~
--1--
:....J
INTERNAL INPUT
DATA
STORAG E
OUTPUT AND
~
REGISTER
r-O+-
ADRS.REG.
MULTIPLEXER
~
CHANNEL
(D REG)
(MAREG)
SYNCHRONIZERS
~
TEMPORARY
FUNCTION
DATA STORAGE
.... REGISTER
REG_
(F REG)
(D REG)
~ l
ADDER FUNCTION
INPUT NETWORK
r+-
DECODE
(ACX)
TABLE
~
---y
~
ADDER AND SEQUENCE
-
PARITY
COUNTER A
GENERATOR
(SA CTR)
~
SEQUENCE
-COUNTER B
(SB CTR)
Figure 1-2. UNIVAC 9200/9200 1//9300/9300 /I Systems
Processor Block Diogrom
-
CONTROL
TO ALL
COMPONENT
f
~
FUNCTION
CONTROL FF'S
~
AND GATING
S
2

UP-7546
Rev. 1
UNIVAC 9200/9200 11/9300/9300 II I 1 1-
,________ P_R_O __ C_E_S_S_O_R __ A_N __ D_S_T __ O_R_A_G __E__________ ~ ___________ ~~~~
They are controlled and coordinated by means of internally stored programs which
are derived from a standard instruction repertoire. The function of each of the com po-
nents is as follows:
• Storage Unit
- Comprises registers used in the processing and storage of all
instructions and data that is to be, or has been, processed.
• Data Register
(D Reg)
•
Temporary
Data Storage
Register
(B Reg)
•
Adder Input
Network
(ACX)
•
Adder and
Parity
Generator
Provides temporary storage for data that is currently being
processed. All tran sfer of data between the proc essor or
peripheral units and the storage unit is accomplished through
the data register.
Provides additional temporary storage for data currently being
processed, an d also for various special codes required for
process control and addressing.
- Gates, modifies, and generates data involved in processing
program data or special control codes.
- Performs various processes specified by the instructions,
such as addition, subtraction, and the formation of AN D- and
OR- products. Also generates parity.
• Storage (Memory) - Addresses of data being processed.
Address Buffer
(MA)
• Storage (Memory) - Stores the addresses of data currently being processed.
Address Register
(MA Reg)
• Function Register - Stores the partial decoded function code specified in an
(F Reg) instruction.
• Function Decode
Table
• Sequence
Counters
A and B
(SA
CTR,
SB CTR)
• Function Control
Flip-flops and
Gating
- Interprets instructions and generates the control signals
required for the initiation of the required process.
- Controls sequencing of the various control signals required
to complete a process specified by an instruction. Although
outputs of both counters control the generating of funct,ion
signals, sequence counter A is used as a first-stage input
to the second-stage sequence counter B.
- Contains all of the secondary storage and gating circuitry
for generation of the control signals necessary to initiate
the various subfunctions of a specified process.

UP-7546L
Rev. 1
----------- -
UNIVAC 9200/9200 11/9300/9300 II
PROCESSOR AND STORAGE
1.2. SYSTEM CONFIGURATION
The UNIVAC 9200/9200 11/9300/9300 II Systems processor is housed in two separate
cabinets. The larger of the two cabinets con tains an operator's control panel, a
printer, and the integrated logic circuit packages. The second cabinet is the elec-
tronics cabinet; it contains the storage (memory) circuitry and the power supplies
and power distribution panel for the entire processor.
Table 1-1 lists the basic and optional processor equipment for each of the four
systems (UNIV AC 9200, 9200 II, 9300, 9300 II). Figures 1-3, 1-4, 1-5, and 1-6
illustrate the system configurations for these systems.
UNIVAC
SYSTEMS
9200
9200 II
Printer Processor Printer
Processor
o Control
o Printer
o Form control loop
o 250 lPM bar printer
96 print positions
63 char acter pr int bar
o ElK-byte storage
Expandab Ie to 16K byte
1.2 Ilsec. cycle time
o J~rithmeticControl
Control for printer,
punch, and reader
Multiplexer channel;
accesses up to 8 sub-
5,ystems or another
processor
Multiply, divide, edit
s
2;00 lPM print speed
120 print pOSitions
Print position expansio
132 print pOSitions
Variable speed printing
8 lPI print spacing
Form aI ignment
n
--
LEGEND:
0
0
0
0
0
0
0
*
*
t
I
t
t
t
r
t
o Basic Equipment
Control
Printer
Form control loop
250 lPM bar printer
96 print positions
63 character print bar
8K-byte storage
Expandab Ie to 32K bytes
1.2 Ilsec. cycle time
Ar Ithmet icC ontro I
Control for printer,
punch, and reader
Multiplexer channel;
accesses up to 8 sub-
systems or another
processor
Multiply, divide, edit
Se lector c hanne I
300 lPM print speed
120 print pOSitions
Print pOSition expansion
132 print pOSitions
Variable speed printing
8lPI print spacing
Form alignment
* Processor Optional Features
Printer Optional Features
PROCESSORS
9300
9300 II
Printer Processor
Printer Processor
0 Control
0
Control
0 Printer
0
Printer
0 Form control loop
0
Form control loop
0
600 lPM bar printer
0 600 lPM bar printer
120 print pOSitions
120 print pOSitions
63 character print bar
63 character print bar
0 8K-byte storage
0 16K-byte storage
Expandab Ie to 32K bytes
EXpandable to 32K bytes
0.6Ilsec. cycle time
0.6 Iisec. cycle time
0
Ar ithmetic Control
0
Ar it hmet ic /C ontro I
Control for printer,
Control for printer,
punch, and reader
punch, and reader
*
Multiplexer channel;
0 Multiplexer channel;
accesses up to 8 sub-
accesses up to 8 sub-
sys te ms or another
systems or another
processor
processor
0
Multiply, div ide, ed it
0 Multiply, divide, edit
0
Se lec tor c hanne I
t
Print position expansion
t
Print position expansion
I High speed numeric print
t High speed numeric print
I 8
lPI print spacing
r 8
lPI print spacing
Table 7- 7. Configurations for UNIVAC 9200 and 9300 Systems Processors
4

UP-7546
Rev. 1
UNIVAC 9200/9200 11/9300/9300 II
PROCESSOR AND STORAGE
,--------------------------------------~----------
~--
UNIVAC 9200 SYSTEM PROCESSOR
9200 PR OC ESS OR
3030-00
PR INTER AND
PH INTER CONTROL
250 LF'M
96 PRINT POSITIONS
63··CHARACTER PRINT BAR
FOfIMS CONTROL LOOP
LEGEND:
C==J BASIC EQUIPMENT
CARD
READER.
CONTROL
CARD
,- MULTIPLY;--
DIVI DE/
EDIT
F0882-00
MUL TIPLEXER
I I/O CHANNEL
I
L __ ~8~-~_
1- - -: PROCESSOR OPTIONAL FEATURES
!.._-_.'
PRINTER OPTIONAL FEATURES
NOTIE: ALL HARDWARE AND FEATURE NUMBERS SHOWN
APPLY TO EQUIPMENT FOR 60Hz OPERATION.
COUNTERPARTS ARE AVAILABLE FOR 50Hz
OPERATION.
I
I
---l
ND
OR
8K BYTE
STORAGE
1.2 pSEC
-----.,.----,
I I
4 K. B YTE 14K B VT E I
STORAGE: STORAGE I
EXPANSION I EXPANSIONI
1.2pSEC I
l.2pSEC :
I I
: I
1.--_7_00_7_-9_3---1_ ~~8':'0::8_L! ~:~::7J
r-----, - -- - --,
12K BYTE
STORAGE
1.2pSEC
I
I
4K BYTE I
STORAGE I
EXPANSION I
. I
1.2 pSEC I
I
I
I
,--_7_00_7_-9_2~_ ~1~0'::6J
OR 16K BYTE
STORAGE
1.2 pSEC
7007-91
Figure 1-3. Configuration for UNIVAC 9200 System Processor

UP-7S46~
Rev. 1
---
UNIVAC 9200/9200 11/9300/9300 "
PROCESSOR AND STORAGE 1
SECTION:
UNIVAC 9200 II SYSTEM PROCESSOR
--------------_._---------
9200 II PR OC ESSOR
3030-94 8K B
YT E
STORAGE
1.2 flSEC
-- --1-- --,
I 1
4K BYTE 4K BYTE I
I-AND ,...--
STORAGE I STORAGE I
EXPANSION: EXPANSION I
1.2 fl
SEC
I 1.21
1SEC
I
----------------~---~
PR INTER AND
PRINTER CONTROL
LEGEND:
c=J BASIC EQUIPMENT
CARD
READER.
CONTROL
r---------
I MULTIPLY /
DIVIDE,'
:
EDIT
I F0882-00
MUL TIPLEXER
I/O C HANNE L
SELECTOR CHANNEL
DUAL I/O C HANNE L
F1104-99 I
~-------- ______ I
: ____ J PROCESSOR OPTIONAL FEATURES
C::J PRINTER OPTIONAL FEATURES
NOTE: ALL HARDWARE AND FEATURE NUMBERS SHOWN
APPLY TO EQUIPMENT FOR 60Hz OPERATION.
COUNTERPARTS ARE AVAILABLE FOR 50Hz
OPERATION.
OR
OR
FIRST 1 SECOND 1
EXPANSION IEXPANSION I
I I
,-_70_0_7-_93---, !~9~9~ LF~890-:': J
12K BYTE
STORAGE
1.2 flSEC
----r---l
4K BYTE 116K BYTE 1
STORAGE I STORAGE I
EXPANSION IEXPANSION I
1.2 fl
SEC
1 1.2 fl
SEC
I
I I
FIRST I SECOND I
EXPANSION IEXPANSION I
: I
'--_70_0_7-_92----J ~0890-96_1~0890-9~
16K BYT E
STORAGE
1.2 flSEC
-----,
16K BYTE II
STORAGE
EXPANSION I
- 1.2 flSEC :
OR
OR
I
I
L--7_0_0_7 -_9_1 -' ._F ~90-~ J
--I
24K BYTE 8K BYTE I
STORAGE STORAGE I
1.2 flSEC EXPANSION I
1.2 flSEC I
I
I
I
7007-87 F0890-93 I
L-- __ ---' ____ .J
32K BYTE
STORAGE
1.2 flSEC
7007-85
Figure 7 -4. Configuration for UNIVAC 9200 If System Processor

UP-7546
Rev. 1 UNIVAC
9200/9200 11/9300/9300 II
PROCESSOR AND STORAGE
,----------------------------------------~----------
~~-.
UNIVAC 9300 SYSTEM PROCESSOR
PR INTER AND
PRINTER CONTROL
9300 PROCESSOR
3030-02
CARD
READER.
CONTROL
600 LPN!
120 PRINT POSITIONS CARD
63-CHA,R,A.CTER PRINT BARS •
PUNCH
FORMS CONTROL LOOP CONTROL
MULTIPLY/
DIVIDE/
EDIT
~------~--------------~
LEGEND:
C] BASIC EQUIPMENT
[==~~~~ PROCESSOR OPTIONAL FEATURES
PRINTER OPTIONAL FEATURES
MULTIPLEXER
I/O CHANNEL
NOTE: ALL HARDWARE AND FEATURE NUMBERS SHOWN
APPLY TO EQUIPMENT FOR 60Hz OPERATION.
COUNTERPARTS ARE AVAILABLE FOR 50Hz
OPERATION.
OR
OR
OR
OR
8K BYTE
STORAGE
0.6/lSEC
----r----l
4K BYTE' 4K BYTE I
STORAGE I STORAGE I
EXPANSION IEXPANSION I
0.6/lSEC I 0.6/lSEC I
FIRST I SECOND :
EXPANSION: EXPANSION I
L..-_700_7_-08_.J~ ~9~0:" LF ~8~-~ J
12K BYTE
STORAG E
0.6/lSEC
7007-10
-----r- --- r---l
4K BYTE I 8K BYTE I 8K BYTE I
STORAGE I STORAGE
1 STORAGE I
EXPANSION IEXPANSION I EXPANSION I
0:6/lSEC I 0.6/lSEC I 0.6/lSEC I
I
FIRST I SECOND I THIRD I
EXPANSION IEXPANSION IEXPANSION I
I I I
F0890-92 I F0890-05 I F0890-06 I
L..- __ --'_ - - -,- -- -- ----7
16K BYTE
STORAGE
0.6/lSEC
----1
16K BYTE I
STORAGE I
EXPANSION I
0.6/lSEC I
I
I
I
L..-7_0_07_-_12--, ~ ~~~ J
24K BYTE
STORAGE
0.6/lSEC
----l
8K BYTE I
STORAGE I
EXPANSION
0.6/lSEC I
I
I
I
L-_70_0_7-_18-.J ~ O~~:J
32K BYTE
STORAGE
0.6/lSEC
7007-14
" "" OR /
'r----(
I 16K BYTE. I
I STORAGE I
I
EXPANSION I
I 0.6/lSEC I
I SECOND I
IEXPANSION I
I I
I
F0890-02 I
L. ____ .J
Figure 1-5. Configuration for UNIVAC 9300 System Processor

UP-7S46~
Rev. 1
------
UNIVAC 9200/9200 11/9300/9300 II
PROCESSOR AND STORAGE 1
SECTION:
UNIVAC 9300 II SYSTEM PROCESSOR
9300 1\ PROCESSOR
3030-96
~----------------~C~A=RD~~
PRINTER AND PRINT
CONTROL
600 LPM
READER.
CONTROL
120 PRINT POSITIONS CARD
63-CHARACTER
PRINT BAR ·PUNCH
FORMS CONTROL LOOP CONTROL
LEGEND:
c=J BASIC EQU IPMENT
::=.-_-_-_-j PR OCESSOR OPT10NAL FEAT URES
g~"~:J PRINTER OPTIONAL FEATURES
MULTIPLY/
DIV IDE/
EDIT
MU L TIPLEXER
I/O C HANNE L
SELECTOR
CHANNE L
NOTE: ALL HARDWARE AND FEATURE NUMBERS SHOWN
APPLY TO EQUIPMENT FOR 60Hz OPERAT ION.
COUNTERPARTS ARE AVAILABLE FOR 50Hz
OPERAT ION.
AND
OR
OR
16K BYTE
STORAGE
0.6I1
SEC
----1-----,
SK BYTE I SK BYTE I
STORAG E STORAGE
EXPANSIONI EXPANSIONI
0.6
I1SEC I 0.6I1
SEC
I
FIRST I, SECOND I
EXPANSION EXPANSION I
I I
,--_70_0_7_-1_2--l..!:.OS90-05 J. ~~o~~
....... 'bR \
24K BYTE
STORAGE
0.6I1
SEC
............ " \
---lr-~--1
SKBYTE II 16KBYTEI
STORAGE II STORAGE I
EXPANSION 'I EXPANSION I
0.6I1
SEC
II 0.6I1
SEC
I
1\ I
II I
L.--
7
_O _
O_
7
-_1S _____F OS9~0:J L ~~~~J
32K BYTE
STORAGE
0.6 I1SEC
7007-14
Figure 1-6. Configuration for UNIVAC 9300 /I System Processor
8
P AGE:

UP-7546
Rev. 1
UNIVAC 9200/9200 11/9300/9300 II I 1 I 9
~~~_P_R_O_C_E_S_S_O_R_A_N_D~S_T_O_R_A_G_E~~~~~~~~~~~~~_~_
1.3. COMPONENT DESCRIPTION
Components for the different systems are generally rather similar. For this reason,
the descriptions which follow apply, with exceptions noted, regardless of the system
in which the component is used.
1.3.1. Processor
The major portions of the UNIVAC 9200/9200 11/9300/9300 II Systems processor
are the main storage, control, arithmetic, and input and output.
1.3.1.1. Main Storage
The main storage portions of the processor is a separate free standing unit connected
to the printer processor cabinet. The storage elements are of the plated wire, cylin-
drical thin film type. The storage unit operates either in a read, write, or lockout mode
at a cycle rate of 1.2 microseconds for the UNIVAC 9200 and 9200 II Systems pro-
cessor; and at a rate of 0.6 microseconds for the UNIVAC 9300 and 9300 II Systems
processor. Reading is nondestructive; that is, the data is not erased from storage
by the read process.
The main storage is used to hold data received from input peripherals, results of
processing, data to be distributed to output peripherals, programmed instructions,
and control information.
The minimum basic storage is 8,192 bytes of nine bits each (eight data bits and
one parity bit), except that the UNIVAC 9300 II Systems processor has a minimum
of 16,384 bytes. The basic storage units may be expanded to 12,288, 16,384, 24,576,
or 32,768 bytes except for the UNIVAC 9200 Systems processor, which is limited
to 16,384 bytes.
1.3.1.2. Control
The control portion of the processor controls the sequence, interpretation, and
execution of each instruction. The cycling of main storage is initiated by this
section. All of the hardware aspects of interrupt handling, error checking, and
protection are performed by the con trol section. The control section maintains
the program address location counter and provides for the different processor
modes of operation.
1.3.1.3. Arithmetic
The arithmetic portion of the processor performs data manipulations includ :ing
binary and decimal arithmetic operations, and logical operations. The basic
UNIVAC 9200 and 9200 II Systems processor is limited to machine addition only.
Subtraction is performed by converting the subtrahend to its two's complement
and adding. To multiply and divide, a suitable subroutine must be inserted into
the user's program. The Multiply, Divide, and Edit capability (see 1.3.1.3.1) is
available as an option.
1.3.1.3.1. Multiply, Divide, and Edit
The UNIVAC 9300 and 9300 II Systems processor has a multiply/divide/edit
ins truction set which includes decimal multiplication and di vision, and additional
editing features. This capability is optional for the UNIVAC 9200 and 9200 II
Systems processor.

UP-7546 I
Rev.1 ~
UNIVAC 9200/9200 11/9300/9300 II
PROCESSOR AND STORAGE
1
SECTION:
PAGE:
1.3.1.3.2. Subtraction by Two's Complement Method
Because the fundamental arithmetic operation of the processor is addition, to
perform subtraction it is necessary to add the two's complement of the subtrahend
to the minuend. Let M and S be the absolute values of the minuend and subtrahend
respectively. Then:
(+M)-(+S) ! I(+M)+(+S)'
(+M)-(-S) . (+M)+(-S)'
(-M)-(+S) IS converted to (-M)+(+S)'
(-M)-(-S) (-M)+(-S)'
where (). denotes the two's complement of the original value.
By definition, the two's complement of a binary number (N) with n digit positions
is:
Thus for eight-bit binary number (N), the two's complement is 28_N or, in
binary notation, 1 OOOOOOOO-N.
The two's complement of the binary number 00111001, for example, is:
100000000
·-00111001
- 11000111
Note that actual subtraction is not required, since the two's complement can be
obtained by inspection of the number. Each bit of the number is simply inverted,
that is, a 1 is changed to aD, and a 0 is changed to a 1; a 1 is then added to the
least significant bit at right. Thus the
binary number 00111001
is inverted
1 is added
11000110
+ 1
----
11000111 = two's complement of 00111001,
which agrees with the result obtained above.
Example:
It is desired to subtract +58 from another number. This is done by adding the
two's complement of 58. What is the value?
Binary equivalent
One's complement
0011 1010
1100 0101
t 1
Two's complement 1100 0110 This is the desired value.
Suppose 58 were to be subtracted from 17, where the representation of 17 is
0001 0001.
The addition is represented 0001 0001
1100 0110
1101 0111
10

UP-7546
Rev. 1
UNIVAC 9200/9200 11/9300/9300 II I 1 I
____ P_R_O_C_E_S_SO_R_A_N_D_S_T_O_R_A_G_E _____ ~ ____ ~~~~
The 1 in the most significant bit position indicates a negative value; therefore
the two's complement is required. This is -(0010 1000+1) = -(0010 1001) which
is -41.
1.3.1.4. Input/Output
The input/output portion of the processor, through the use of input/output instruc-
tions, provides the means of initiating the operation of all peripheral devices
associated with the processor and of determining the status of each device. This
portion of the processor also directs the transfer of data between main storage and
the peripheral system. After control of the input/output function has been transferred
to the control unit for a particular device, data transfer is performed concurrently
with the processor functions.
1.3.1.4.1. Multiplexer Channel
The multiplexer channel (standard with the UNIVAC 9200 II and 9300 II Systems
processor and optional with the UNIVAC 9200 and 9300 Sys terns processor)
provides an interface for devices other than the basic peripheral devices, card
punch, and card reader. The multiplexer channel accepts I/O instructions from
the processor and sends I/O requests to the connected peripheral devices, one
at a time. The multiplexer channel places the device address and all signals
needed to ascertain the status of the device on the multiplexer channel output
line (bus) to the device. The peripheral device responds with a byte of information
containing its status. The multiplexer channel decodes this status byte and generates
genera tes a condition code for the processor. If there is no traffic to be executed,
or if the device is not at that time ready to handle traffic, the multiplexer channel
tests the next peripheral device in a predetermined order; if there is no traffic to
be executed, the sequence specified by the processor's program is executed.
The multiplexer channel is asynchronous; it depends on the processor and the
control unit of the peripheral device for instructions. The channel generates the
necessary sequences to respond to sequences initiated by the control unit, making
use of the processor's flip-flop registers and arithmetic circuits on a time-sharing
basis. This permits the multiplexer channel to work several peripheral devices in
sequence by assigning the multiplexer channel interface to the first peripheral
device long enough to transfer one or a few bytes of information. When the pro-
cessor finishes its operation with the first peripheral device, it operates similarly
with the other peripheral devices before returning to the first. The processor must
test each peripheral device for availability before an information transfer can take
place.
The maximum transfer rate for one control unit in burst mode is 98K bytes per
second. To achieve this rate, the control unit must respond with the leading
edge of Service In at the input to the channel within 1.3 microseconds following
the trailing edge of Service Out at the output of the channel. If the control unit
response time is greater than 103 microseconds the maximum transfer rate is
reduced as follows:
• If greater than 1.3 microseconds but less than 2.45 microseconds, the maximum
transfer rate is 87. 7K bytes per second.
• If greater than 2A5 microseconds but less than 3065 microseconds, the maximum
transfer rate is 79.5K bytes per second.

UP-7546 L UNIVAC 9200/9200 1119300/9300 II
Rev. 1 PROCESSOR AND STORAGE
--- -----
The maximum transfer rate for one control unit in multiplex mode is 75.8K bytes
per second. To achieve this rate the control unit must respond with the leading
edge of Address In at the input to the channel within 350 nanoseconds following
the leading edge of Select Out at the output of the channel. This time must include
all delays caused by propagation of the Select signal, cable lengths, control unit
receivers and drivers, and control unit logic. Ordinarily, this can be achieved only
by the highest priority control unit. The typical maximum rate for a control unit,
other than the highest priority control unit is 72.5K bytes per second. To maintain
these two transfer rates (75.8K and 72.5K bytes per second) the control unit
must have the Request In signal active at the channel 1.2 microseconds following
the trailing edge of the Service Out signal at the output of the channel.
For a control unit that does not meet the Request In requirements, the maximum
transfer rate drops to 57.2K bytes per second. This rate uses the average processor
latency time of 805 microseconds. Again to achieve this transfer rate of 57.2
bytes per second, the control unit must respond with the leading edge of the
Request In signal at the input to the channel within 4.5 microseconds following
the trailing edge of Service Out signal at the output of the channel.
The maximum transfer rate, for more than one control unit in multiplex mode when
connected in such a configuration as to keep Request In signal active continuously
is 72.5K bytes per second. This rate considers the typical response times from
the control units, the Select Out propagation time through higher priority control
units and the fact that the channel interface bus cable can be connected to eight
control units.
1.3.1.4.2. Selector Channel
The selector channel, standard with UNIVAC 9300 II Systems processor and
optional with UNIVAC 9200 II System processor, provides additional I/O
capability for eight subsystems such as a disc subsystem. Maximum transfer
rate of the selector channel is 350K bytes per second, including command
chaining when operating in burst mode.
The selector channel operates with a higher priority than the multiplexer channel,
thereby permitting the selector channel to gain access to the storage area at any
time.
1.3.2. Printer
A bar printer with a 63-character print bar is included in the main cabinet of the
processor. For the basic UNIVAC 9200/9200 II equipment, printing speed is 250
lines per minute; there are 96 print positions per line. For the UNIVAC 9300 and
9300 II equipment, printing speed is 600 lines per minute and there are 120 print
positions. See Appendix A for additional type bars available for the printer.
Optional features available for the printer are described in the subsections as
follows.
1.3.2.1. 300 L PM Print Speed
The 300 LPM print speed feature, optional with the UNIVAC 9200 and 9300 II
Systems processor, increases the print speed of the printer from 250 LPM to
300 LPM. When used with variable speed printing feature, the variable speed is
increased from 250/500 LPM to 300/600 LPM.