Sundance Spas SMT335E User manual

SMT335E
SMT375E
User Manual
User Manual (QCF42); Version 3.0, 5/2/01; © Sundance Multiprocessor Technology Ltd. 2001

Version 3.0 Page 2 of 53 SMT335E SMT375E User Manual
Revision History
Date Comments Engineer Version
04/04/01 Copy from SMT335E V1.1 J.V. 1.0
12/06/02 JTAG Header for FPGA reprogramming added
Interrupt control register 6 address corrected
FPGA firmware version 1.1
J.V. 1.1
24/06/02 SDBC and SDBD Added
FPGA firmware version 1.2
Y.C 1.2
Check your firmware revision number with the program read_version_335E.out and
ask for a more recent version if necessary.
E-mail: [email protected]
.

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Table of Contents
Revision History........................................................................................................ 2
Contacting Sundance ............................................................................................... 5
Notational Conventions............................................................................................ 6
SMT335E ................................................................................................................ 6
Register Descriptions .............................................................................................. 6
Outline Description................................................................................................... 7
Block Diagram........................................................................................................... 8
Architecture Description .......................................................................................... 8
TMS320C6201/6701................................................................................................... 9
Boot Mode............................................................................................................... 9
EMIF Control Registers .......................................................................................... 10
SBSRAM ............................................................................................................... 10
SDRAM ................................................................................................................. 10
FLASH................................................................................................................... 10
Reprogramming the firmware and boot code ...................................................... 11
Interrupts ................................................................................................................. 12
Interrupt Control Register ...................................................................................... 12
Communication ports............................................................................................. 14
Overview ............................................................................................................... 14
Comm-ports on the SMT335E............................................................................... 15
Comm-port Status and Control Register ............................................................... 16
Global Status Register .......................................................................................... 19
Data rates.............................................................................................................. 20
SDB .......................................................................................................................... 21
SDB Status Register ............................................................................................. 22
Output Flag Register ............................................................................................. 23
Input Flag Register ................................................................................................ 23
SDB update........................................................................................................... 23
SDB Interrupts....................................................................................................... 24
DMA ...................................................................................................................... 25
SDB Initialisation ................................................................................................... 26

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Suspending SDB transmission.............................................................................. 26
Bus exchange ....................................................................................................... 26
SDB Clock selection.............................................................................................. 27
Data formatting...................................................................................................... 27
Global bus ............................................................................................................... 28
Writing to the Global Bus....................................................................................... 28
Reading from the Global Bus ................................................................................ 29
Global Bus Operation Register.............................................................................. 30
Global Bus Control Register.................................................................................. 30
PCI access ............................................................................................................ 31
Programmable Wait States ................................................................................... 34
Clock Speed ............................................................................................................ 35
LED Setting ............................................................................................................. 35
LED Register......................................................................................................... 35
CONFIG & NMI......................................................................................................... 36
Config Register...................................................................................................... 36
Timer ........................................................................................................................ 37
Timer Control Register .......................................................................................... 37
Code Composer ...................................................................................................... 38
Application Development....................................................................................... 38
Operating Conditions ............................................................................................. 39
Safety .................................................................................................................... 39
EMC ...................................................................................................................... 39
General Requirements .......................................................................................... 39
Power Consumption .............................................................................................. 40
Serial Ports.............................................................................................................. 41
Host Port Interface.................................................................................................. 41
Silicon Serial Number............................................................................................. 41
C6201 Memory Map ................................................................................................ 42
Flash Access........................................................................................................... 42
Virtex Memory Map ................................................................................................. 43
Jumpers................................................................................................................... 45
JP1: Clock speed select ........................................................................................ 45

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JP2: Serial port header.......................................................................................... 45
JP3 - Fan power connector ............................................................................ 46
SDB Pin-Out ............................................................................................................ 46
Virtex Pin-Out.......................................................................................................... 48
Bibliography............................................................................................................ 51
Index ........................................................................................................................ 52
Contacting Sundance
You can contact Sundance for additional information by sending email to
[email protected]

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Notational Conventions
SMT335E
Throughout this document the term SMT335E will usually be used to refer to both the
SMT335E and the SMT375E. It should be clear from the context when a distinction is
being drawn between the two types of module.
Register Descriptions
The format of registers is described using diagrams of the following form:
31–24 23–16 15–8 7–0
OFLAGLEVEL
R,00000000 RW,10000000 R,00000000 R,10000000
The digits at the top of the diagram indicate bit positions within the register and the
central section names bits or bit fields. The bottom row describes what may be done
to the field and its value after reset. Shaded fields are reserved and should only ever
be written with zeroes.
R Readable by the CPU
W Writeable by the CPU
RW Readable and writeable by the CPU
Binary digits indicate the value of the field after reset.

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Outline Description
The SMT335E is a C6000-based size 2 TIM offering the following features:
 SMT335E: TMS320C6201 processor running at 200MHz
 SMT375E: TMS320C6701 processor running at 166MHz
 Six 20MB/s communication ports
 512KB of fast SBSRAM, 16MB of SDRAM
 2MB Flash ROM for boot code and FPGA programming
 Global expansion connector
 High bandwidth data I/O via 4 Sundance Digital Buses (SDB).

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Block Diagram
Ho st Po rt &
Se r i a l Po r t s
Architecture Description
The SMT335E TIM consists of a Texas Instruments TMS320C6201 running at
200MHz while the SMT375E has a TMS320C6701 running at 166MHz. Modules are
populated with 512KB of synchronous burst SRAM (SBSRAM) and 16MB of
synchronous DRAM (SDRAM), giving a total memory capacity of 16.5MB.
A Field Programmable Gate Array (FPGA) is used to manage global bus accesses
and implement six communication ports and four Sundance Digital Buses.

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TMS320C6201/6701
Bother processors will run with zero wait states from internal SRAM, the
TMS320C6201 at 200MHz and the TMS320C6701 at 166MHz.
An on-board synthesiser from MicroClock provides the clock used for the C6000;
jumpers on the TIM allow you to select clock speeds from 118MHz to 200MHz.
Unlike similar TIMs based on the TMS320C4x, there is no option to provide an
external clock source.
The TIM configuration feature is fully implemented. This provides a single open-
collector line that can be held low until software configuration has been completed.
Boot Mode
The SMT335E is configured to use the following boot sequence each time it is taken
out of reset:
1. The processor copies a bootstrap program from the first 32KB of the flash
memory into internal program RAM starting at address 0.
2. Execution starts at address 0.
The standard bootstrap supplied with the SMT335E then performs the following
operations:
1. All relevant C6000 internal registers are set to default values;
2. The FPGA is configured from data held in flash memory and sets up the
communication ports, the global bus and the Sundance Digital Buses. This
step must have been completed before data can be sent to the comm-ports
from external sources such as the host or other TIMs;
3. A C4x-style boot loader is executed. This will continually examine the six
communication ports until data appears on one of them. The bootstrap will
then load a program in boot format from that port; the loader will not read data
arriving on other ports. See “Application Development” on page 38 for details
of the boot loader format;
4. Finally, control is passed to the loaded program.

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EMIF Control Registers
The C6000 contains several registers that control the external memory interface
(EMIF). There is one global control register and a separate register for each of the
memory spaces CE0 to CE3. A full description of these registers can be found in the
C600001 Peripherals Reference Guide[1].
The standard bootstrap will initialise these registers to the following values:
GC (global control) 0x00003779
0x0000377D
For half speed SBSRAM
For full speed SBSRAM (default)
CE0 0x00000040 Indicates SBSRAM
CE1 0x30FF3F23 Defines asynchronous memory timings
CE2 0x00000030 Indicates SDRAM
CE3 0x00000030 VIRTEX FPGA
SBSRAM
Memory space CE0 is used to access 512KB of zero wait-state SBSRAM over the
C6000 external memory interface (EMI).
SBSRAM is normally set to run at the speed of the C6000 core clock, but the GC
register can be used to reduce this to one half of the core clock speed. The
appropriate setting has to be determined in conjunction with the C6000 core speed
and the external memory speed; refer to Clock Speed on page 35 for further details.
SDRAM
Memory space CE2 is used to access 16MB of SDRAM over the EMI. The SDRAM
operates at one half of the core clock speed.
FLASH
A 2MB Flash ROM device is connected to the C6000 EMI. This device is accessed,
16-bit word at a time, with word addresses from 0x0140 0000 to 0x015F FFFF using
strobe CE1 in 32-bit asynchronous mode. Each 32-bit load will give 16 bits of data in
bits 15–0 of the result; the state of bits 31–16 is undefined.
The ROM holds boot code for the C6000, configuration data for the FPGA, and
optional user-defined code.
A software protection algorithm is in place to prevent programs accidentally altering
the ROM’s contents. Please contact Sundance for further information about re-
programming this device [6].