Sys Tec Electronic ECUcore-9G20 User manual

Development Board
ECUcore-9G20
Hardware Manual
Edition March 2010
System House for Distributed Automation

Development Board ECUcore-9G20
© SYS TEC electronic GmbH 2010 L-1256e_01
Status / Changes
Status: released
Date/ Version Section Change Editor
L-1256e_01 initial version K.Becker

Development Board ECUcore-9G20
©SYS TEC electronic GmbH 2010 L-1256e_01 3
In this manual are descriptions for copyrighted products, which are not explicitly
indicated as such. The absence of the trademark (©) symbol does not infer that a
product is not protected. Additionally, registered patents and trademarks are
similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is believed to be
entirely reliable. However, SYS TEC electronic GmbH assumes no responsibility
for any inaccuracies. SYS TEC electronic GmbH neither gives any guarantee nor
accepts any liability whatsoever for consequential damages resulting from the use
of this manual or its associated product. SYS TEC electronic GmbH reserves the
right to alter the information contained herein without prior notification and
accepts no responsibility for any damages, which might result.
Additionally, SYS TEC electronic GmbH offers no guarantee nor accepts any
liability for damages arising from the improper usage or improper installation of
the hardware or software. SYS TEC electronic GmbH further reserves the right to
alter the layout and/or design of the hardware without prior notification and
accepts no liability for doing so.
©Copyright 2010 SYS TEC electronic GmbH. rights – including those of
translation, reprint, broadcast, photomechanical or similar reproduction and
storage or processing in computer systems, in whole or in part – are reserved. No
reproduction may occur without the express written consent from SYS TEC
electronic GmbH.
WORLDWIDE
Address: SYS TEC electronic GmbH
August-Bebel-Str. 29
D-07973 Greiz
GERMANY
Ordering
Information: [phone]
[e-mail]
Technical
Support: [phone]
[e-mail]
Fax: [phone]
Web Site: http://www.systec-electronic.com
1st Edition March 2010

Index of Figures and Tables
©SYS TEC electronic GmbH 2010 L-1256e_01
1Introduction.........................................................................................1
2Ordering Information and Support..................................................3
3Properties of the Development Board...............................................4
3.1 Overview......................................................................................4
3.2 Block Diagram .............................................................................5
3.3 Positions of Elements...................................................................6
3.4 Jumper..........................................................................................7
3.5 Board Connectors.......................................................................10
4Component Descriptions..................................................................14
4.1 Power Supply .............................................................................14
4.2 ICE Interface ..............................................................................15
4.3 JTAG Interface...........................................................................15
4.4 I/O Elements...............................................................................17
4.5 Ethernet ......................................................................................18
4.6 USB............................................................................................18
4.6.1 USB host .......................................................................18
4.6.2 USB device....................................................................18
4.7 SD Card......................................................................................19
4.8 EEPROM....................................................................................19
4.9 ADC............................................................................................19
4.10 CAN............................................................................................20
4.11 RS232.........................................................................................20

Development Board ECUcore-9G20
© SYS TEC electronic GmbH 2010 L-1256e_01
Index of figures and tables
Table 1: Pinout high density connectors................................................ 11
Table 2: Pinout expansion connectors X200 ......................................... 12
Table 3: Pinout expansion connectors X201 ......................................... 13
Table 4: ICE/JTAG connector X403 ..................................................... 15
Table 5: JTAG connector X502............................................................. 16
Table 6: IO elements connected to the ECUcore................................... 17
Table 7: LEDs connected to onboard ICs.............................................. 17
Table 8: Pinout of RJ45-connectors....................................................... 18
Table 9: SD card connection.................................................................. 19
Table 10: EEPROM connection............................................................... 19
Table 11: ADC connection ...................................................................... 19
Table 12: CAN connector pinout............................................................. 20
Table 13: RS232 connector pinout .......................................................... 20
Table 14: RS232 jumper settings............................................................. 20
Figure 1: Developmentboard ECUcore-9G20 .......................................... 4
Figure 2: Block Diagram Developmentboard ECUcore-9G20................. 5
Figure 3: Positions of components............................................................ 6
Figure 4: Default Jumper configuration.................................................... 7
Figure 5: Jumper pincount......................................................................... 7
Figure 6: Pinout (top view) ..................................................................... 10

Introduction
L-1256e_01 © SYS TEC electronic GmbH 2010 1
1Introduction
The ECUcore-9G20 Development Board provides a flexible
development platform, enabling quick and easy start-up and
subsequent programming of the Single Board Computer module. The
design of the Development Board allows easy operation of the
installed ECUcore in Communication Networks (LAN, USB, CAN)
and simple GPIO-Tests by keys and leds. Components for SPI and I²C
enable easy testing of these bus-systems. A connection of additional
expansion board features for various functions is supported, to allow
fast and convenient prototyping and software evaluation.
For the SYS TEC IEC 61131-3 PLC firmware, an additional
RUN/STOP/MRES switch is provided on the Development Board as
well as one RUN LED and one ERROR LED for indicating the
operating mode of the IEC 61131-3 PLC.
This manual describes the functionality of the Development Board.
Precise specifications of the installed ECUcore or the controller that is
implemented on the ECUcore can be found in the applicable Hardware
Manual or the User’s Manual and Data Sheet of the controller. The
functions or descriptions of the ECUcore and the microcontroller are
not included in this Hardware Manual! These documentations are not
relevant for the basic functionality of the Development Board.
Please refer to the corresponding manuals and documentations for any
other board components you may use (USB host, Ethernet switch,
etc.).
Low-active signals are denoted by a „/“ in front of the signal name
(i.e. “/RD”). The representation “0” indicates a logical-zero or low-
level signal. A “1” is the synonym for a logical one or high-level
signal.

Ordering Information and Support
L-1256e_01 © SYS TEC electronic GmbH 2010 3
2Ordering Information and Support
Order Number Version
4002008 Development Board ECUcore-9G20
Development Board features:
•Socket for ECUcore-9G20 (order number: 4001016)
•External power supply from 9-36VDC/24W
•Switching regulator 9-36VDC / 5VDC
•Switching regulator 9-36VDC / 3,3VDC
•4 keys and 4 led's free usable for development
•1 8-position dip-switch
•1 3-position slider switch and 2 leds for using with PLC firmware
•Boot and reset key plus reset and shutdown led
•Battery for buffering Real time clock on ECUcore
•EEPROM 16kiB as SPI example
•Potentiometer as analog input
•microSD-card socket
•1 USB device connector for onboard USB device on ECUcore
•2 USB2.0 host conectors for onboard USB host on ECUcore
•1 Ethernet connector for onboard PHY on ECUcore
•1 CAN interface with D-Sub 9 connector
•3 RS232 interfaces with 2 D-Sub 9 and 1 multi-pin connector
•20pin ICE/JTAG interface for Atmel 9G20 microcontroller
•10pin JTAG interface for FPGA
•All freely usable pins of the ECUcore are brought out to an
expansion connector, 2x 120pol pin contact stripes with user-
friendly 2,54mm contact spacing

Development Board ECUcore-9G20
3Properties of the Development Board
3.1 Overview
The ECUcore-9G20 belongs to SYS TEC’s ECUcore family. The
ECUcore-9G20 integrates all elements of a microcontroller system on
one board. The module only needs an external power supply (3,3V) to
operate. The Development Board was build for accessing all interfaces
of the ECUcore and rapid development of software drivers and
applications. Some special drivers or external controllers are helpful to
interact with the environment (bus-systems and control elements). All
interfaces are brought out on standard connectors (RJ45, D-SUB).
Figure 1: Development Board ECUcore-9G20
The dimensions of the board are 160mm x 115mm.
4 © SYS TEC electronic GmbH 2010 L-1256e_01

Properties of the Development Board
3.2 Block Diagram
Ethernet
CAN
UART
USB-Host
USB-Device
MMC-Interface
Reset
BOOT
ICE/JTAG
JTAG-FPGA
RTC
Power Supply
3V3DC
DIP-Switch
PCB-Version
4 x LED
4 x key
RSM-Switch
Run/Error-LED
EEPROM
ADC
Poti
Reset-LED
Reset-Button
BOOT-Button
Battery
FPGA-IO
Bus-Driver
Bus-Driver
Ethernet
3 x RS232
1 x CAN
microSD-Card
ICE/JTAG9G20
JTAG FPGA
1 x USB-Device
2 x USB-Host
9-36VDC
jack
9-36VDC
screw
9-36V
3,3V
9-36V
5,0V
E
C
U
c
o
r
e
-
9
G
2
0
Figure 2: Block Diagram Development Board ECUcore-9G20
L-1256e_01 © SYS TEC electronic GmbH 2010 5

Development Board ECUcore-9G20
3.3 Positions of Elements
Figure 3: Positions of components
6 © SYS TEC electronic GmbH 2010 L-1256e_01

Properties of the Development Board
3.4 Jumper
J
P405
Figure 4: Default Jumper configuration
1
2
1
2
3
1
3
2
4
1
3
2
4
5
7
6
8
1
3
2
4
5
7
6
8
910
1
3
2
4
5
7
6
8
91
11
13
12
14
15 16
1
3
2
4
57
6
8
0
1
2
3
Figure 5: Jumper pincount
L-1256e_01 © SYS TEC electronic GmbH 2010 7

Development Board ECUcore-9G20
8 © SYS TEC electronic GmbH 2010 L-1256e_01
Jumper Signal Jumper
Setting
(closed)
Function
1-2 Signal TXD2 is on X302
3-4 default Signal DTXD is on X301
5-6 Signal TXD0 is on X300
JP300 TXD1, TXD0
DTXD, TXD2
7-8 default Signal TXD1 is on X300
1-2 Signal RXD2 is on X302
3-4 default Signal DRXD is on X301
5-6 Signal RXD0 is on X300
JP301 RXD1, RXD0
DRXD, RXD2
7-8 default Signal RXD1 is on X300
JP302 CAN-
Termination 1-2 Termination 120R on CAN active
JP303 CAN-VCC 1-2 CAN-VCC (5,0VDC) is on Pin 1 of X303 present
(Fuse with 125mA)
1-2 default LED D400 is on FPGA_IO_69
3-4 default LED D401 is on FPGA_IO_70
5-6 default LED D402 is on FPGA_IO_71
7-8 default LED D403 is on FPGA_IO_72
9-10 default Button S400 is on FPGA_IO_73
11-12 default Button S401 is on FPGA_IO_74
13-14 default Button S402 is on FPGA_IO_75
JP400
FPGA_IO_69
FPGA_IO_70
FPGA_IO_71
FPGA_IO_72
FPGA_IO_73
FPGA_IO_74
FPGA_IO_75
FPGA_IO_76
15-16 default Button S403 is on FPGA_IO_76
1-2 default LED D405 is on FPGA_IO_77
3-4 default LED D406 is on FPGA_IO_78
JP401 FPGA_IO_77
FPGA_IO_78
FPGA_IO_79
FPGA_IO_80
FPGA_IO_81
5-6 default Switch Status MRES is on FPGA_IO_79

Properties of the Development Board
L-1256e_01 © SYS TEC electronic GmbH 2010 9
Jumper Signal Jumper
Setting
(closed)
Function
7-8 default Switch Status Stop is on FPGA_IO_80
9-10 default Switch Status Run is on FPGA_IO_81
JP402 BMS 1-2 Signal BMS is set to 1 (high)
1-2 Signal /BOOT is set to 0 (low)
JP403 /BOOT
WKUP 3-4 Signal WKUP is set to 0 (low)
1-2 default EEPROM Signal SPI-CLK is on FPGA_IO_49
3-4 default EEPROM Signal SPI-DI is on FPGA_IO_48
5-6 default EEPROM Signal SPI-DO is on FPGA_IO_47
JP404
FPGA_IO_44
FPGA_IO_47
FPGA_IO_48
FPGA_IO_49 7-8 default EEPROM Signal SPI-/CS is on FPGA_IO_44
1-2 default Signal SD_SLOT (Open/close) is present on AD2
3-4 Potentiometer R429 is present on AD2
5-6 Potentiometer R429 is present on AD1
JP405 AD0 AD1
AD2 7-8 default Potentiometer R429 is present on AD0
1-2 default JTAG-Signal FPGA_TCK is present on Pin 1 of X502
JP500 ARM_TCK
FPGA_TCK 3-4 default JTAG-Signal ARM_TCK is present on Pin 1 of X502
1-2 default JTAG-Signal FPGA_TMS is present on Pin 3 of X502
JP501 ARM_TMS
FPGA_TMS 3-4 default JTAG-Signal ARM_TMS is present on Pin 3 of X502
1-2 default JTAG-Signal FPGA_TDI is present on Pin 7 of X502
3-4 JTAG-Signal ARM_TDI is present on Pin 7 of X502
5-6 JTAG-Signal FPGA_TDO is present on Pin 5 of X502
JP502
ARM_TDO
FPGA_TDO
ARM_TDI
FPGA_TDI 7-8 default JTAG-Signal ARM_TDO is present on Pin 7 of X502
JP503 /JTAGSEL 1-2 Signal /JTAGSEL is set to 1 (high)
Boundary Scan Mode
1-2 Bit0 of Version on EBI D8
3-4 default Bit1 of Version on EBI D9
5-6 Bit2 of Version on EBI D10
J400 PCB-Version
7-8 Bit3 of Version on EBI D11
1-2 Write Protect of EEPROM is active
J401 EEPROM Write
Protect 2-3 default Write Protect of EEPROM is not active

Development Board ECUcore-9G20
3.5 Board Connectors
See figure 3 for the position of board connetor X100 and its connector
rows.
The Development Board ECUcore-9G20 has two board connectors.
Each of the SMT male header consists of 100 contacts divided into
double rows. In total, the board has 200 contacts. For better emc-
properties, 20% of pins are GND.
A third connector at the front side is for connecting debug interfaces
of the CPU, Power sequencer and FPGA. It is not mounted by default.
X500
X500
X501
A
B
C
D
AB
1
1
1
50
50
12
Figure 6: Pinout (top view)
The board connectors are equipped with the common and durable
1,27mm pitch. The type of the male header used on the Development
Board is the '7072'-series provided by "W+P PRODUCTS".
Please refer to the datasheet and the electrical specifications.
Connectors:
ECUcore-9G20:
•W+P 6060-100-36-00-00-00-PPST (2x50pol. female)
•W+P 6060-024-36-00-00-00-PPST (2x12pol. female)
Development Board:
•W+P 7072-100-10-00-10-PPST (2x50pol. male)
10 © SYS TEC electronic GmbH 2010 L-1256e_01

Properties of the Development Board
L-1256e_01 © SYS TEC electronic GmbH 2010 11
•W+P 7072-024-10-00-10-PPST (2x12pol. male)
The following table defines the pinout.
Signal Pin Pin Signal Signal Pin Pin Signal
GND A01 B01 GND GND
C01 D01 +2V5_EPHY
/BOOT A02 B02 /MR ETH0_TX-
C02 D02 GND
WKUP A03 B03 /RESET ETH0_TX+
C03 D03 ETH_SPEED
SHDN A04 B04 /PFI ETH0_RX+
C04 D04 ETH_LINK/ACT
BMS A05 B05 WDI ETH0_RX-
C05 D05 GND
GND A06 B06 PS_IO GND
C06 D06 AD0
DRXD A07 B07 GND ADTRG
C07 D07 AD1
DTXD A08 B08 RTS0 ADVREF
C08 D08 AD2
DSR0 A09 B09 CTS0 GND
C09 D09 GND
DTR0 A10 B10 RTS1 SD_MCDA0
C10 D10 SD_MCDB0
DCD0 A11 B11 CTS1 SD_MCDA1
C11 D11 SD_MCDB1
GND A12 B12 GND SD_MCDA2
C12 D12 SD_MCDB2
TXD0 A13 B13 TXD1 SD_MCDA3
C13 D13 SD_MCDB3
RXD0 A14 B14 RXD1 SD_MCCK
C14 D14 SD_MCCDA
TXD2 A15 B15 TXD3 GND
C15 D15 SD_MCCDB
RXD2 A16 B16 RXD3 SCK0
C16 D16 GND
GND A17 B17 TXD5 SCK1
C17 D17 TIOA1
USB_HDPA A18 B18 RXD5 SCK2
C18 D18 TIOB1
USB_HDMA A19 B19 GND PCK1
C19 D19 TIOA2
USB_HDPB A20 B20 USB_DDP RK0
C20 D20 TIOB2
USB_HDMB A21 B21 USB_DDM TK0
C21 D21 TD0
GND A22 B22 GND RF0
C22 D22 RD0
I2C_DATA A23 B23 CAN_TXD TF0
C23 D23 GND
I2C_CLK A24 B24 CAN_RXD GND
C24 D24 FPGA_IO0
GND A25 B25 CAN_VCC FPGA_IO1
C25 D25 FPGA_IO2
FPGA_IO44 A26 B26 GND FPGA_IO3
C26 D26 FPGA_IO4
FPGA_IO46 A27 B27 FPGA_IO45 FPGA_IO5
C27 D27 FPGA_IO6
FPGA_IO48 A28 B28 FPGA_IO47 FPGA_IO7
C28 D28 GND
FPGA_IO50 A29 B29 FPGA_IO49 GND
C29 D29 FPGA_IO8
FPGA_IO52 A30 B30 FPGA_IO51 FPGA_IO9
C30 D30 FPGA_IO10
Table 1: Pinout high density connectors

Development Board ECUcore-9G20
12 © SYS TEC electronic GmbH 2010 L-1256e_01
Most Signals are brought out of expansion connectors X200 and
X201. These are pin contact stripes with standard 2,54mm contact
spacing. So you can easily connect extensions for fast development.
X200 A B C D
1 /BOOT GND /MR GND
2 WKUP /RESET /SHDN /PFI
3 BMS GND WDI GND
4 PS_IO DRXD DTXD RTS0
5 DSR0 GND CTS0 GND
6 DTR0 RTS1 DCD0 CTS1
7 TxD0 GND TxD1 GND
8 RxD0 RxD1 TxD2 TxD3
9 RXD2 GND RxD3 GND
10 USB_HDMA USB_HDPA RxD5 TxD5
11 USB_HDMB USB_HDPB NC GND
12 USB_DDM USB_DDP I2C_DATA CAN1_TxD
13 I2C_CLK GND CAN1_RxD GND
14 CAN_VCC FPGA_IO44 FPGA_IO46 FPGA_IO45
15 FPGA_IO48 GND FPGA_IO47 GND
16 FPGA_IO50 FPGA_IO49 FPGA_IO52 FPGA_IO51
17 FPGA_IO53 GND FPGA_IO54 GND
18 FPGA_IO56 FPGA_IO55 FPGA_IO58 FPGA_IO57
19 FPGA_IO60 GND FPGA_IO59 GND
20 FPGA_IO62 FPGA_IO61 FPGA_IO63 FPGA_IO64
21 FPGA_IO66 GND FPGA_IO65 GND
22 FPGA_IO68 FPGA_IO67 FPGA_IO70 FPGA_IO69
23 FPGA_IO72 GND FPGA_IO71 GND
24 FPGA_IO73 FPGA_IO74 FPGA_IO76 FPGA_IO75
25 FPGA_IO78 GND FPGA_IO77 GND
26 FPGA_IO80 FPGA_IO79 VBAT FPGA_IO81
27 NC GND NC GND
28 NC NC NC NC
29 NC GND NC GND
30 3V3 NC 3V3 NC
Table 2: Pinout expansion connectors X200

Properties of the Development Board
L-1256e_01 © SYS TEC electronic GmbH 2010 13
X201 A B C D
1 +2V5_EPHY GND
GND GND
2 GND ETH_SPEED
GND ETH_LINK/ACT
3 GND GND AD0 GND
4 ADTRG AD1 ADVREF AD2
5 SD_MCDA0 GND SD_MCDB0 GND
6 SD_MCDA1 SD_MCDB1 SD_MCDA2 SD_MCDB2
7 SD_MCDA3 GND SD_MCDB3 GND
8 SD_MCCK SD_MCCDA SD_MCCDB SCK0
9 SCK1 GND TIOA1 GND
10 SCK2 TIOB1 PCK1 TIOA2
11 RK0 GND TIOB2 GND
12 TK0 TD0 RF0 RD0
13 TF0 GND FPGA_IO0 GND
14 FPGA_IO1 FPGA_IO2 FPGA_IO3 FPGA_IO4
15 FPGA_IO5 GND FPGA_IO6 GND
16 FPGA_IO7 FPGA_IO8 FPGA_IO9 FPGA_IO10
17 FPGA_IO11 GND FPGA_IO12 GND
18 FPGA_IO13 FPGA_IO14 FPGA_IO15 FPGA_IO17
19 FPGA_IO16 GND FPGA_IO18 GND
20 FPGA_IO19 FPGA_IO20 FPGA_IO21 FPGA_IO22
21 FPGA_IO23 GND FPGA_IO24 GND
22 FPGA_IO25 FPGA_IO26 FPGA_IO27 FPGA_IO28
23 FPGA_IO29 GND FPGA_IO30 GND
24 FPGA_IO31 FPGA_IO32 FPGA_IO33 FPGA_IO34
25 FPGA_IO35 GND FPGA_IO36 GND
26 FPGA_IO37 FPGA_IO38 FPGA_IO39 FPGA_IO40
27 FPGA_IO41 GND FPGA_IO42 GND
28 FPGA_IO43 NC NC NC
29 NC GND NC GND
30 3V3 NC 3V3 NC
Table 3: Pinout expansion connectors X201

Development Board ECUcore-9G20
4Component Descriptions
4.1 Power Supply
The Development Board needs a power supply of 9VDC to 28VDC
unregulated. Power should be 12W minimum to supply the module
and any peripheral circuits.
External power supply can be connected via Low Voltage Socket
X600 or Terminal Block X601.
+9..+24VDC
GND
500mA center hole
2.0mm
5
.5mm
-+
polarity:
Please ensure that the correct polarity is applied to the terminal block.
This is shown on the silkscreen on the PCB next to the terminal block.
From this voltage two switching regulators produce the onboard
voltages (5VDC and 3,3VDC).
5VDC are only used for USB host. 3,3VDC supplies the ECUcore and
all other peripheral elements.
14 © SYS TEC electronic GmbH 2010 L-1256e_01