TEWS DATENTECHNIK TIP850 User manual

TIP850
16 channel 12 bit ADC 4 channel 12 bit DAC
Version 1.1 Revision C
User Manual
Issue 1.2
28 February 1996
D75850800
TEWS DATEN
TECHNIK GmbH
Am Bahnhof 7
D-25469 Halstenbek
Germany
Tel [phone]
Fax [phone]

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TIP850-10
16 channel 12 bit ADC
(gain 1, 10, 100),
4 channel 12 bit DAC
TIP850-11
16 channel 12 bit ADC
(gain1,2,4,8),
4 channel 12 bit DAC
This manual covers both products
This document contains information, which is proprietary to TEWS DATEN
TECHNIK GmbH. Any reproduction
without written permission is forbidden.
TEWSDATEN
TECHNIK GmbH has madeany effort to ensure that this manual is accurateand complete. How-
everTEWSDATEN
TECHNIK GmbH reservesthe rightto changetheproduct described inthisdocument at any
time without notice.
This product has been designed to operate with IndustryPackXcompatible carriers. Connection toincompatible
hardware is likely to cause serious damage.
TEWS DATEN
TECHNIK GmbH is not liable for any damage arising out of the application or use of the device
described herin.
Issue Desscription Date
1.0 First issue 30 June 1994
1.1 Change of settling time 7 Dec 1994
1.2 Change of settliung time 28 Feb 1996
K1996 by TEWS DATEN TECHNIK GmbH
IndustryPack is a registered trademark of GreenSpring Computers, Inc

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1. Product Description 5................................
2. Technical Specification 6.............................
3. Functional Description 7.............................
3.1. Analog Input 7.............................................
3.2. Analog Output 7............................................
3.3. Data Correction 8...........................................
3.3.1. ADC Correction formula 8..................................
3.3.2. DAC Correction formula 9..................................
4. ID Prom Contents 10..................................
5. IP Addressing 12......................................
5.1. ADC Register Set 12........................................
5.1.1. ADC Control and Status Register 12..........................
5.1.1.1. ADC Channel Selection 12.................................
5.1.1.2. ADC Gain Selection 13....................................
5.1.1.3. ADC Automatic Settling Time Control 13.....................
5.1.1.4. ADC Interrupt Enable 13...................................
5.1.1.5. ADC Status 14...........................................
5.1.2. ADC Convert Register 14...................................
5.1.3. ADC Data Register 14.......................................
5.2. DAC Register Set 15........................................
5.2.1. DAC Data Register 15.......................................
5.2.2. DAC Load Register 15......................................
5.2.3. Interrupt Vector Register 15..................................
6. IP I/O connector 16....................................
6.1. Analog Input Connections 16..................................
6.2. Analog Output Connections 17................................
6.3. Miscellaneous Output Connections 17.........................

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Figure 1: TIP850 Block Diagram 5.................................
Figure 2: ID PROM contents TIP850-10 V1.0 10.....................
Figure 3: ID PROM contents TIP850 V1.1 11........................
Figure 4: ADCCSR Input Channel Selection and Mode 12.............
Figure 5: ADCCSR Input Gain Selection 13..........................
Figure 6: ADCCSR Automatic Settling Time Control 13................
Figure 7: Table of Settling Time 13..................................
Figure 8: ADCCSR Interrupt Enable 14.............................
Figure 9: ADCCSR ADC Status 14.................................
Figure 10: ADC Data Register Layout 14............................
Figure 11: DAC Data Register Layout 15............................
Figure 12: TIP850 Analog Input Connections 16......................
Figure 13: TIP850 Analog Output Connections 17....................
Figure 14: TIP850 Miscellaneous Output Connections 17..............

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1. Product Description
The TIP850 is an IndustryPack
9
compatible module combining a 16 channel multiplexed 12 bit ADC with a 4
channel 12 bit DAC.
The 16 input channels of the multiplexer can be software configured to operate in single ended mode, or to ope-
rate as a 8 channel differential input. The multiplexer of the ADC circuit is over voltage protected up to 70 Vp-p.
A programmable gain amplifier allows gains of 1, 10, 100 or 1, 2, 4, 8 . Full scale input range is ±10V (for a gain
of 1).
ThefourD/A channelsprovidesimultaneousloadingandoutputvoltagesof±10V.After RESETallD/Achannels
default to 0 V.
Each TIP850 is calibrated at the factory. Calibration information for both, A/D and D/A circuits are stored in the
Identification PROM unique to each IP.
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2. Technical Specification
Logic Interface IndustryPack9Logic Interface
Size single wide IP
I/O Interface 50-conductor flat cable
Number of Analog Inputs 16 single ended channels or
8 differential channels
Input Gain Amplifier programmable for gain 1, 10, 100 (TIP850-10 only)
programmable for gain 1, 2, 4, 8 (TIP850-11 only)
Input Voltage Range for TIP850-10:
±10V (gain = 1)
±1V (gain = 10)
±0.1V (gain = 100)
for TIP850-11:
±10V (gain = 1)
±5V (gain = 2)
±2.5V (gain = 4)
±1.25V (gain = 8)
NOTE: The module accuracy is guarantied at the ±10V input
voltage range only for voltage range of ±9.6V.
Input Over Voltage Input over voltage protection up to 70V p-p
Input ADC 12 bit, 10³sec sampling time (ADS7804)
Number of Analog Outputs 4 channels
Output Voltage Range ±10V
Output Current minimum ±5mA
Output ADC 12 bit, maximum of 6³sec settling time (DAC4813)
Calibration Data Calibration data for gain and offset correction in ID PROM
Wait States IDPROM no wait states
Power Requirements 250mA @ 5V
70mA @ +12V
35mA @ -12V
Temperature Range Operating 0ECto70EC
Storage -45EC to 125EC
Humidity 5 - 95% non-condensing

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3. Functional Description
3.1. Analog Input
The TIP850provides 16single endedor 8differentialmultiplexed analoginputs. The desired input and the mode
(single ended or differential) is selected by programming the input multiplexer.
A software programmable gain amplifier with gain settings of 1, 10 and 100 for the TIP850-10 and 1, 2, 4 and
8 for the TIP850-11 allows a direct connection of a wide rage of sensors and instrumentation. The maximum
analog input voltage range is ±10V at a gain of 1.
The ADC is a 12 bit ADS7804 with a minimum sampling rate of 100kHz. The 12 data bit are alined in the least
significant 12 bit of a 16 bit data word. The sign bit is extend by hardware into the upper 4 bit of the 16 bit word.
For this reason the data value can be directly used in 16 bit integer arithmetic as two’s complement value.
Inmultiplexedanaloginputsystemsasettlingtimemustexpirebeforethedatacanbeconvertedafterthechange
of the input channel. This settling time is depended on the programmed gain. At the most analog input solutions
itistheresponsibility of theuser toobservethesettlingtime. TheTIP850modulehasanAutomaticSettlingTime
Control mode. If this mode is enabled, a write to the ADC Control and Status Register, which is necessary to
select a new input channel by the multiplexer, initiates a data conversion automatically after the settling time has
expired.
The absolute accuracy of the module is increased by using the possibility to correct the data by software with
factory calibration factors, which are stored in the individual ID PROM of the module.
3.2. Analog Output
The TIP850 has four 12 bit analog outputs with a voltage range of ±10V. The four DAC are implemented in a
single converter DAC4813.
The DAC4813 has a double data buffer. New data values for the outputs can be loaded for all four channels wi-
thout affecting the output voltage. Then, with a single command, all four channels update simultaneously to the
new values.

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3.3. Data Correction
There are two errors which affect the DC accuracy of the ADC and DAC. The first is the zero error (offset). For
the ADC this is the data value when converting with the input connected with its own ground in single ended
mode, or with shorted inputs in differential mode. For the DAC it is the data value required to produce a zero
voltage output signal. This error is corrected by subtracting the known error from all readings.
The second error is the gain error. Gain error is the difference between the ideal gain and the actual gain of the
programmable gain amplifier and the ADC, respectively DAC. It is corrected by multiplying the data value by a
correction factor.
The data correction values are obtained during factory calibration and are stored in the modules individual ver-
sionoftheIDPROM.TheADChasapairofoffsetandgaincorrectionvaluesforeachoftheprogrammablegains.
The DAC has a pair of offset and gain correction values for each single output channel.
The correction values are stored in the ID PROM as two’s complement byte wide values in the range -128 to
127. For higher accuracy they are scaled to ¼ LSB.
3.3.1. ADC Correction formula
The basic formula for correcting any ADC reading is:
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Value is the corrected result, Reading is the data read from the ADC, Gaincorr and Offsetcorr are the correction
factors from the ID PROM.
Gaincorr and Offsetcorr correction factors are stored for each for the possible gain settings.
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3.3.2. DAC Correction formula
The basic formula for correcting any DAC output is:
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Data is the number that will be sent to the DAC, Value is the desired output value, Gaincorr and Offsetcorr are
the correction factors from the ID PROM.
Gaincorr and Offsetcorr correction factors are stored for each of the four DAC outputs.
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4. ID Prom Contents
ADDRESS FUNCTION
$ 01 ASCII ’I’ $ 49
$ 03 ASCII ’P’ $ 50
$ 05 ASCII ’A’ $ 41
$07 ASCII’C’ $43
$ 09 Manufacturer ID $ B3
$ 0B Model Number $ 09
$ 0D Revision $ 10
$ 0F RESERVED $ 00
$ 11 Driver-ID low-byte $ 00
$ 13 Driver-ID high-byte $ 00
$ 15 number of bytes used $ 1A
$ 17 C R C $ board dependend
$ 19 DAC1 Offset $ board dependent
$ 1B DAC2 Offset $ board dependent
$ 1D DAC3 Offset $ board dependent
$ 1F DAC4 Offset $ board dependent
$ 21 DAC1 Gain $ board dependent
$ 23 DAC2 Gain $ board dependent
$ 25 DAC3 Gain $ board dependent
$ 27 DAC4 Gain $ board dependent
$ 29 ADC Offset (Gain = 1) $ board dependent
$ 2B ADC Offset (Gain = 10) $ board dependent
$ 2D ADC Offset (Gain = 100) $ board dependent
$ 2F ADC Gain (Gain = 1) $ board dependent
$ 31 ADC Gain (Gain = 10) $ board dependent
$ 33 ADC Gain (Gain = 100) $ board dependent
Figure 2: ID PROM contents TIP850-10 V1.0
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ADDRESS FUNCTION
$ 01 ASCII ’I’ $ 49
$ 03 ASCII ’P’ $ 50
$ 05 ASCII ’A’ $ 41
$07 ASCII’C’ $43
$ 09 Manufacturer ID $ B3
$ 0B Model Number $ 09 for TIP850-10
$ 11 for TIP850-11
$ 0D Revision $ 11
$ 0F RESERVED $ 00
$ 11 Driver-ID low-byte $ 00
$ 13 Driver-ID high-byte $ 00
$ 15 number of bytes used $ 1C
$ 17 C R C $ board dependend
$ 19 DAC1 Offset $ board dependent
$ 1B DAC2 Offset $ board dependent
$ 1D DAC3 Offset $ board dependent
$ 1F DAC4 Offset $ board dependent
$ 21 DAC1 Gain $ board dependent
$ 23 DAC2 Gain $ board dependent
$ 25 DAC3 Gain $ board dependent
$ 27 DAC4 Gain $ board dependent
$ 29 ADC Offset (Gain = 1) $ board dependent
$ 2B ADC Offset (Gain = 2,10) $ board dependent
$ 2D ADC Offset (Gain = 4,100) $ board dependent
$ 2F ADC Offset (Gain = 8) $ board dependent
$ 31 ADC Gain (Gain = 1) $ board dependent
$ 33 ADC Gain (Gain = 2,10) $ board dependent
$ 35 ADC Gain (Gain = 4,100) $ board dependent
$ 37 ADC Gain (Gain = 8) $ board dependent
Figure 3: ID PROM contents TIP850 V1.1
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5. IP Addressing
The TIP850 is controlled by a set of registers, which are directly accessible in the IO address space of the IP.
ADDRESS NAME FUNCTION SIZE
$ 00 ADCCSR ADC Control and Status Register word
$ 02 ADCCON ADC Convert Register word
$ 04 ADCDAT ADC Data Register word
$ 06 DACDA1 DAC 1 Data Register word
$ 08 DACDA2 DAC 2 Data Register word
$ 0A DACDA3 DAC 3 Data Register word
$ 0C DACDA4 DAC 4 Data Register word
$ 0E DACLOA DAC Load Register word
$ 41 INTVEC Interrupt Vector Register byte
5.1. ADC Register Set
The ADC part of the TIP850 is controlled by a set of 3 register.
5.1.1. ADC Control and Status Register
The ADC Control and Status Register ADCCSR is used to select an input channel, the gain and the mode for
the next data conversion. This is done by writing the corresponding bit pattern into bit 0 to bit 8. The status of
the ADC can be obtained by reading bit 14 and bit 15.
5.1.1.1. ADC Channel Selection
Bit 0 to bit 3 of the ADCCSR determine the input channel for the next data conversion. These bits are write only.
The write only bit 4 of the ADCCSR is controlling if the module operates in differential or in single ended mode.
If this bit is set to ’1’ differential mode is selected.
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5.1.1.2. ADC Gain Selection
Bit 5 and bit 6 of the ADCCSR are used to program the gain of the input amplifier. These bits are write only.
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Figure 5: ADCCSR Input Gain Selection
5.1.1.3. ADC Automatic Settling Time Control
If thewriteonly bit 7of theADCCSRis set to’1’, theautomatic controlof thesettling timeisenabled.Inthismode
a data conversion is initiated by writing to the ADCCSR, but however is automatically delayed by hardware until
the gain depended settling time has expired.
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Figure 7: Table of Settling Time
5.1.1.4. ADC Interrupt Enable
The write only bit 8 of the ADCCSR is used to enable interrupt generation of the module. If this bit is set to ’1’
aninterruptisalwaysinitiated,wheneveradataconversionhasbeencompleted. Ifthe moduleisnotinthemode
of automatic settling time controlan additionalinterrupt is being generatedwhen thesettling time has beenelap-
sed after writing to the ADCCSR.

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5.1.1.5. ADC Status
The status of the ADC converter can be obtained by ready the bit 14 and bit 15 of the ADCCSR. As long as bit
14 is in the ’1’ state, the settling time did not expire after writing to the ADCCSR. Bit 15 indicates the busy status
of the ADC converter itself.
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5.1.2. ADC Convert Register
By writing any value into the ADC Convert Register ADCCON a data conversion is started immediately. This
mode is most useful, if a single input channel must be sampled with a maximum data rate.
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5.1.3. ADC Data Register
The ADC Data Register ADCDAT contains the converted data value. The data bit 11 (sign bit) of the ADC is
extended into bits 12 to 15 by hardware. This allows direct precessing of the data as a 16 bit two’s complement
integer value.
Figure 10: ADC Data Register Layout
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5.2. DAC Register Set
5.2.1. DAC Data Register
Each analog output channel has its own DAC Data Register (DACDA1, DACDA2, DACDA3 and DACDA4).
Theseregisterscanbeloadedwithatwo’scomplementvalue.Bit12tobit15areignored,duetothe12bitresolu-
tion of the DAC itself. The DAC Data Registers are write only.
However loadingthe DAC Data Registers does not affect the analog output voltage directly.All output channels
will change their voltage at the same time by a write access to the DAC Load Register DACLOA.
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5.2.2. DAC Load Register
A write access to the DACLoad Register with anydata value is starting the conversion of the DAC DataRegister
content to analog for all for channels at the same time.
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5.2.3. Interrupt Vector Register
The Interrupt Vector Register INTVEC is a byte wide read/writeregister. It must beloaded withthe desired inter-
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6. IP I/O connector
6.1. Analog Input Connections
Mode
Pin-Number Single Ended Differential
01 ADC Input 1 ADC Input 1 +
02 ADC Input 9 ADC Input 1 -
03 AGND AGND
04 ADC Input 10 ADC Input 2 -
05 ADC Input 2 ADC Input 2 +
06 AGND AGND
07 ADC Input 3 ADC Input 3 +
08 ADC Input 11 ADC Input 3 -
09 AGND AGND
10 ADC Input 12 ADC Input 4 -
11 ADC Input 4 ADC Input 4 +
12 AGND AGND
13 ADC Input 5 ADC Input 5 +
14 ADC Input 13 ADC Input 5 -
15 AGND AGND
16 ADC Input 14 ADC Input 6 -
17 ADC Input 6 ADC Input 6 +
18 AGND AGND
19 ADC Input 7 ADC Input 7 +
20 ADC Input 15 ADC Input 7 -
21 AGND AGND
22 ADC Input 16 ADC Input 8 -
23 ADC Input 8 ADC Input 8 +
24 AGND AGND
Figure 12: TIP850 Analog Input Connections

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6.2. Analog Output Connections
Pin-Number Function
27 DAC 1 Output
28 AGND
29 DAC 2 Output
30 AGND
31 DAC 3 Output
32 AGND
33 DAC 4 Output
34 AGND
Figure 13: TIP850 Analog Output Connections
6.3. Miscellaneous Output Connections
Pin-Number Function
44 GND
45 -12V
46 GND
47 +12V
48 GND
49 +5V
50 GND
Figure 14: TIP850 Miscellaneous Output Connections