Texas Instruments AMIC110 ICE User manual

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AMIC110 Industrial Communications Engine (AMIC110 ICE)
User's Guide
SPRUIE6–April 2017
AMIC110 Industrial Communications Engine
(AMIC110 ICE)
This user's guide details the hardware architecture of the AMIC110 Industrial Communications Engine
(AMIC110 ICE). The AMIC110 is a Sitara™ AMIC110 ARM®Cortex®-A8 processor System-on-Chip
(SoC).
Contents
1 Introduction ................................................................................................................... 2
1.1 Key Features ........................................................................................................ 2
1.2 Functional Block Diagram ......................................................................................... 3
1.3 Basic Operation..................................................................................................... 3
1.4 Power Supply........................................................................................................ 5
2 Interface Details.............................................................................................................. 5
2.1 Boot Configuration.................................................................................................. 5
2.2 Clock Distribution ................................................................................................... 7
2.3 Reset Circuit Distribution .......................................................................................... 7
2.4 DP83822 – 10/100 Ethernet PHY ................................................................................ 8
2.5 Ethernet Protocol Specific Indicator LEDs..................................................................... 11
2.6 JTAG Emulation Circuit........................................................................................... 13
2.7 Memory Interfaces ................................................................................................ 14
3 AMIC110 ICE Physical Specifications................................................................................... 18
3.1 Board Layout....................................................................................................... 18
3.2 Connector Index................................................................................................... 19
4 Power Supply............................................................................................................... 22
4.1 Power Distribution................................................................................................. 23
4.2 Sitara AMIC110 Current Consumption ......................................................................... 23
4.3 Additional Components – Current Consumption.............................................................. 23
4.4 Overall System Current Consumption.......................................................................... 24
4.5 TPS650250 Power Dissipation.................................................................................. 24
4.6 Measured Power Consumption of System..................................................................... 25
4.7 Thermal Test....................................................................................................... 26
4.8 Power-Up Sequence.............................................................................................. 26
4.9 Power-Up Behavior of Onboard Supply Rails ................................................................. 27
4.10 Power-Down Behavior of Onboard Supply Rails.............................................................. 29
5 Known Issues............................................................................................................... 30
Appendix A ....................................................................................................................... 31
Trademarks
Sitara, Texas Instruments, C2000, LaunchPad, BoosterPack, Code Composer Studio are trademarks of
Texas Instruments.
ARM, Cortex are registered trademarks of ARM Limited.
EtherCAT is a registered trademark of Beckhoff Automation GmbH.
Ethernet/IP is a trademark of ODVA, Inc.
All other trademarks are the property of their respective owners.

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AMIC110 Industrial Communications Engine (AMIC110 ICE)
1 Introduction
1.1 Key Features
The AMIC110 ICE is a high-performance, low-power platform that enables users to evaluate and develop
industrial communications applications for the Sitara AMIC110 ARM Cortex-A8 processor SoC from Texas
Instruments™. The AMIC110 SoC has the following key features:
• Sitara ARM Cortex-A8 32-bit RISC processor (up to 300 MHz)
• Two programmable real-time unit and industrial communication subsystems (PRU-ICSS)
• 64KB of general-purpose, on-chip memory controller (OCMC) RAM (shared L3 RAM)
• Supports protocols such as EtherCAT®, PROFIBUS, PROFINET, and Ethernet/IP™
• Two multichannel audio serial port (McASP) peripherals
• Two master and slave McASPI serial interfaces
• Three I2C master and slave interfaces and six UART interfaces
• Eight 32-bit general-purpose timers
• Three enhanced high-resolution PWM modules (eHRPWMs)
• Three external DMA event inputs that can be used as interrupt inputs
• Three MMC, SD, and SDIO ports
• Two USB 2.0 high-speed OTG ports with integrated PHY
• 324-pin, S-PBGA-N324 package with 0.80-mm ball pitch
The AMIC110 ICE has the following key features:
• AMIC110 is based on the Sitara ARM Cortex-A8 32-bit RISC processor at 300 MHz
• 512MB of DDR3
• 8MB of SPI Flash
• 32KB of I2C EEPROM
• Two 10/100 industrial Ethernet connectors with external magnetics
• RoHS compliant design
• 20-pin JTAG header to support all types of external emulators
• EMC compliant, industrial temperature dual-port EtherCAT slave with an SPI interface
• 5-V input supply, single-chip power management IC (TPS650250) to power the entire board
• AMIC110 can be configured to boot EtherCAT firmware from SPI Flash and also supports boot through
the SPI host processor
• No DDR or other external RAM required when the EtherCAT slave stack runs on an external host
processor (such as the C2000™)
• Texas Instruments™ LaunchPad™ compatible BoosterPack™ format
• 3.3-V SPI interface to C2000 F28069M LaunchPad
The AMIC110 ICE featured applications are:
• Industrial drivers
• Industrial sensors
• Factory automation and control

AMIC110
SPI JTAG UART0
McASP1_AXR0_MDRB
McASP1_AXR1_MDXB
McASP1_ACLKR_MCLKXB
McASP1_ACLKX_MCLKXB
McASP1_FSR_MDRB
McASP
SPI_D1_McASP1_FSX_MFSRB
SPICLK
SPI_D1
SPICS
SPI_D0
DDR3 EEPROM
Board ID
DDR3 is not required when the EtherCAT slave stack
runs on the host controller (for example: C2000).
SPI
ECAT_LATCH0
ECAT_LATCH1
ECAT_SYNC0
ECAT_SYNC1
IRQ
Firmware_Loaded
SYS_RESETn
ECAT and Sys
UART1_TX
UART1_RX
UART1_DE
I/O connections
Fail-safe I/O (3.3 V)
C2000TM MCU with
EtherCAT stack and
driver for ET1100
SPI Flash
JTAG
header
3.3-V TTL,
fail-safe I/O
Header
6-pin header for
3.3-V TTL serial-
to-USB cable
PMIC
TPS650250
DC jackInput: 5 V EMI filter
3V3
1V8
1V5
1V1
10/100 Mbps
Ethernet PHY1
DP83822
10/100 Mbps
Ethernet PHY2
DP83822
Magnetics
RJ45
Status LEDs
Magnetics
RJ45
Status LEDs
Status LED per
EtherCAT standard
requirements
Jack with external
magnetics
Copyright © 2017, Texas Instruments Incorporated
3V3
PROFIBUS
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1.2 Functional Block Diagram
Figure 1 shows the functional block diagram of the AMIC110 ICE device.
Figure 1. AMIC110 ICE Functional Block Diagram
1.3 Basic Operation
For detailed information and resources on the AMIC110 ICE, see TMDXICE110.
Follow the steps in Section 1.3.1 and Section 1.3.2 to quickly get started with the AMIC110 ICE.
1.3.1 Hardware Setup
See the following steps to set up the hardware of the AMIC110 ICE.
1. Unbox the AMIC110 ICE and identify the components and connectors detailed in Section 3.
2. Connect a 20-pin JTAG emulator to J1 on the AMIC110 ICE (see Figure 2) to download a bootable
image to the onboard SPI Flash. For example, XDS100 or XDS200 emulators may be used for this
purpose and are available at XDS110 and XDS200.

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Figure 2. AMIC110 ICE JTAG Connection
3. Connect the pin header connector of the TTL-232R-3V3 serial cable to J3 on the AMIC110 ICE (see
Figure 3). Ensure that pin 1 of the serial cable (black wire, marked with a triangle) is connected to pin 1
of J3 (indicated by a dot on the silk screen).
See TTL to USB Serial Converter Range of Cables Datasheet for information about the TTL-232R-3V3
cable.
4. Connect the USB connector of the serial cable to a PC host port.
5. Connect a CAT5 Ethernet cable from a PC running TwinCAT software to PHY1 (J6 – ECAT IN) of the
ICE board. If users have multiple ICE boards in a chain, connect another CAT5 Ethernet cable from
PHY2 (J7 – ECAT OUT) to PHY1 of the next ICE board. PHY2 of the last ICE board in the chain is left
open.
Figure 3. AMIC110 ICE Serial Port Connection

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AMIC110 Industrial Communications Engine (AMIC110 ICE)
6. Apply power to the power supply of the AMIC110 ICE as detailed in Section 1.4. Do not hot plug the
5-V supply into the ICE board.
Figure 4. AMIC110 ICE Power Supply Connection
1.3.2 Software Setup
See AMIC110SW for software setup.
1.4 Power Supply
Use the recommended power supply (CUI Inc. SMI18-5-V-P5) or an equivalent (output voltage and
current: 5 V, DC ±10% at 1.2 A; output connector: 2.1-mm ID, 5.5-mm OD barrel plug, center positive)
power supply to connect to J8 on the ICE board.
To apply power to the AMIC110 ICE, insert the DC plug of the power supply into the AMIC110 ICE. Then,
connect the AC plug of the power supply to the AC power source. Hot plugging the AMIC110 ICE
(connecting the AC plug before the DC plug) may damage the board.
To remove power from the AMIC110 ICE, disconnect the AC plug of the power supply from the AC power
source. Then, disconnect the DC plug of the power supply from the AMIC110 ICE.
2 Interface Details
2.1 Boot Configuration
Various boot configurations can be set by using pullup and pulldown resistor combinations on the
SYSBOOT inputs (LCD_DATA[15:0] pins). Boot configuration inputs are latched upon de-assertion of the
PORz input (PWRONRSTn pin).
The default SYSBOOT settings for the AMIC110 ICE are 1000_0000_0001_1000b. These settings
correspond to a boot sequence of SPI0, MMC0, USB0, and UART0.
See the SYSBOOT configuration pins section in AM335x and AMIC110 Sitara™ Processors Technical
Reference Manual and the pin attributes table in AMIC110 Sitara™ SoC for the definitions of each
SYSBOOT input.
Table 1 lists the AMIC110 ICE boot configuration pins. PD indicates a pulldown resistor is used to hold the
respective SYSBOOT input low during reset. PU indicates a pullup resistor is used to hold the respective
SYSBOOT input high during reset.

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Table 1. Boot Configuration Pins
SYSBOOT Input Resistor
15 PU
14 PD
13 PD
12 PD
11 PD
10 PD
9 PD
8 PD
7 PD
6 PD
5 PD
4 PU
3 PU
2 PD
1 PD
0 PD
2.1.1 AMIC110 Bootstrap Hardware
Several Ethernet PHY1 (U3) signals are connected to AMIC110 pins that operate as SYSBOOT inputs.
Two of the PHY1 signals must be isolated from AMIC110 SYSBOOT inputs during power on. A dual FET
switch (U10) performs this task. The switch control inputs are connected to the MII1_RXD3 pin operating
as GPIO2_18, which defaults to a high-z input with an internal pull-down after power is applied. The
internal pull-down along with an external pull-down ensures the switch is off as soon as power is applied.
The SYSBOOT buffers (U8 and U9) have an active low enable controlled by the MII1_RXD2 pin operating
as GPIO2_19, which defaults to a high-z input with an internal pull-down after power is applied. The
internal pull-down along with an external pull-down ensures the buffer is enabled as soon as power is
applied. The buffer over-drives any internal pull resistors in the Ethernet PHYs to ensure the SYSBOOT
inputs are the value defined by the SYSBOOT resistor array.
The LCD_DATA[15:0] pins are the AMIC110 SYSBOOT inputs. These pins default to high-z inputs without
any internal pull resistors turned on after power is applied. The value driven by SYSBOOT buffers will be
sampled on the rising edge of the PWRONRSTn input. These values determine the boot mode of the
AMIC110.
See the AMIC110 ICE Schematic Files for more details related to bootstrap hardware.

AMIC110
LaunchPadTM
J5
JTAG
J1
PWRONRST
WARMRST
Buffer
SN74CB3Q3245
O E
EMU_RSTn
PMIC
TPS650250
10 K 100 K
3.3 V
SYS_RESETn
PMIC_RESETOUTn
Copyright © 2017, Texas Instruments Incorporated
AMIC110
XTALIN
XTALOUT
PHY1_TXCLK
PHY1_RXCLK
PHY2_TXCLK
PHY2_RXCLK
PHY1
PHY2
25 MHz
25 MHz
25 MHz
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2.2 Clock Distribution
Figure 5 shows the clock distribution circuit. Three 25-MHz crystals are used onboard. One 25-MHz
crystal is connected to the AMIC110, the second crystal is connected to PHY1, and the third crystal is
connected to PHY2.
Figure 5. Clock Distribution
2.3 Reset Circuit Distribution
Figure 6 shows the reset distribution. All devices on the AMIC110 ICE can be reset by the following:
• ICE onboard RESET button (SW1)
• Power ON reset signal from the PMIC
Figure 6. Reset Distribution

Status LEDs
Ethernet Connector
Magnetics
DP83822
(PHY1)
AMIC110
ETH_TX_D0:3
ETH_RX_D0:3
ETH_TX_EN
ETH_TX_CLK
ETH_RX_DV
ETH_RX_CLK
ETH_RX_ER
ETH_MDC
ETH_MDIO
ETH_RESET
3.3 V
Reset XI XO
Status LEDs
Ethernet Connector
Magnetics
DP83822
(PHY2)
ETH_TX_D0:3
ETH_RX_D0:3
ETH_TX_EN
ETH_TX_CLK
ETH_RX_DV
ETH_RX_CLK
ETH_RX_ER
ETH_MDC
ETH_MDIO
ETH_RESET
3.3 V
Reset XI XO
25 MHz
25 MHz
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2.4 DP83822 – 10/100 Ethernet PHY
The AMIC110 includes two PRU-ICSSs, which can be configured to support numerous industrial
protocols. The PRU subsystem supports two IEEE 802.3 Standard Media Independent Interface (MII)
interfaces, which can be connected to 10/100 Ethernet PHYs. The AMIC110 ICE includes two DP83822
10/100 Ethernet PHYs, which provide two Ethernet connections (see Figure 7). The PHYs are
implemented to support dual EtherCAT slave ports.
Figure 7. Ethernet Interface Without Bootstrap Hardware
2.4.1 Industrial Ethernet PHY Default Configuration
The default configuration of the DP83822 is determined using a number of resistor pullup and pulldown
values on specific pins of the PHY. Depending on the values installed, each of the configuration pins can
be set to one of four modes. A configuration pin or groups of configuration pins are used to set the
configuration of the PHY after it is released from reset. Configuration settings differ depending on the
package type selected for the PHY.

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2.4.2 Industrial Ethernet Resistor Strapping
The DP83822 PHY uses a four-level configuration based on resistor strappings, which generate four
distinct voltages ranges. These resistors are connected to the RX data and control pins that are normally
driven by the PHY and are inputs to the AMIC. The voltage ranges follow:
• Mode 1 – 0 V to 0.3234 V
• Mode 2 – 0.4884 V to 0.5973 V
• Mode 3 – 0.7491 V to 0.9141 V
• Mode 4 – 2.2902 V to 3.3 V
Mid-level voltages can result in high leakage currents and are detrimental to the long-term reliability of the
AMIC 110 I/O cells connected to the strapping resistor. To avoid this situation, only pullup and pulldown
resistors are used to pull the I/O cells as close as possible to 0 V or 3.3 V; this limits the selection of
configurations to those that can be selected by using Mode 1 or Mode 4. The DP83822 device and the
AMIC110 include internal pulling resistors. The values of the external pull resistors are selected to provide
a voltage at the pins of the AMIC110 as close to ground or 3.3 V as possible.
2.4.3 Software Steps for Industrial Ethernet Resistor Strapping
The following steps should be performed before the AMIC110 pins are configured to operate in their
intended application.
Software should maintain the power on default state for LCD_DATA[15:0] pins (except LCD_DATA6 and
LCD_DATA7). LCD_DATA6 and LCD_DATA7 should have their internal pulldown resistors turned on; this
holds the LCD_DATA6 and LCD_DATA7 pins in a valid logic state once the SYSBOOT buffers are turned
off.
The GPMC_AD9 and LCD_PCLK pins should be in their power-on default configuration operating in their
respective GPIO mode with internal pullown resistors turned on. Software should turn off the internal pull
resistors on these pins; this prevents AMIC110 internal pull resistors from interfering with the
bootstrapping of Ethernet PHY1.
The power on default state of the GPMC_A[11:0] and LCD_AC_BIAS_EN pins are configured to their
respective GPIO mode with internal pulldown resistors turned on. The power-on default state of the
GPMC_WPn and GPMC_WAIT0 pins are configured to their respective GPIO mode with internal pull-up
resistors turned on. Software should turn off internal pull resistors on all of these pins to prevent AMIC110
internal pull resistors from interfering with the bootstrapping of Ethernet PHY2 (U5).
Next, software should configure GPIO2_19 to be an output that is driven high to turn off the SYSBOOT
buffers. After a 100-µs delay, the GPMC_AD13 pin should be configured to operate as GPIO1_13 with its
output enabled and driven high; this releases the reset to both Ethernet PHYs, allowing them to latch their
bootstrap inputs.
After another delay of 100 µs, isolation switch U10 must be turned on by enabling the output of GPIO2_18
and driving it high.
The next step is to configure all AMIC110 pins to their intended application and execute the application
code.

AMIC110 (SoC) DP83822 (PHY)
PHY_COL Mode 4
50 K 3.3 V
9 K
PHY1_RXD0 Mode 1
9 K
PHY1_RXD1 Mode 1
9 K
PHY1_RXD2 Mode 1
9 K
PHY1_RXD3 Mode 1
PHY1_LED0 Mode 4
50 K 3.3 V
PHY1_CRS Mode 4
50 K 3.3 V
PHY1_RXER Mode 4
50 K 3.3 V
9 K
PHY1_RXDV Mode 1
2.49 K
R188 4.7 K3.3 V
R53
PU/PD
disabled
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Figure 8 shows the industrial Ethernet PHY1 strapping resistors.
Figure 8. Industrial Ethernet PHY1 Strapping Resistors
Table 2 lists the configurations for PHY1. See the hardware bootstrap configurations section of DP83822
Robust, Low Power 10/100 Mbps Ethernet Physical Layer Transceiver for more information.
Table 2. Ethernet PHY1 Strap Configuration
Strap Setting Pin Name Strap Function Value of Strap
Function Description
Address
COL PHY_AD0 1 1
RX_D0 PHY_AD1 0
RX_D1 PHY_AD2 0
RX_D3 PHY_AD3 0
Modes of operation
COL FX_EN 0 10BASE-Te, half duplex
100BASE-TX, half duplex
RX_D3 AN_EN 1
RX_D0 AN_1 1
LED_0 AN_0 0
EEE operation RX_D1 EEE_EN 0 Disabled
Fast link drop RX_D2 FLD_EN 0 Disabled
Auto MDIX RX_ER AMDIX_EN 1 Disabled
MAC interface RX_ER RGMII_EN 0 MII, 24-MHz reference clock RX_DV RMII_EN 0
RX_DV XI_50 0
LED_0 CRS LED_CFG 1 ON for good link, OFF for no link
LED_1 CRS LED_SPEED 0 Tri-state condition

AMIC110 (SoC) DP83822 (PHY)
PHY2_COL
50 K 3.3 V
9 K
PHY2_RXD0
9 K
PHY2_RXD1
9 K
PHY2_RXD2
9 K
PHY2_RXD3
PHY2_LED0 50 K 3.3 V
PHY2_CRS 50 K 3.3 V
PHY2_RXER 50 K 3.3 V
9 K
PHY2_RXDV
2.49 K
R188 4.7 K3.3 V
R53
PU/PD
disabled
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2.49 K3.3 V
R68
2.49 K 3.3 V
R67
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Figure 9 shows the industrial Ethernet PHY2 strapping resistors. As shown in Figure 9, PHY2 has an
address of 13. All other PHY2 bootstrap settings are the same as PHY1.
Figure 9. Industrial Ethernet PHY2 Strapping Resistors
2.5 Ethernet Protocol Specific Indicator LEDs
The AMIC110 ICE was built with a focus on EtherCAT. The indicator LEDs enable multiprotocol operation.
The following protocols were chosen to be included for potential updates for other RT Ethernet protocols.
• EtherCAT
• SERCOS-III
• PROFINET
• Ethernet/IP
• Powerlink

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Table 3 lists a summary of the required indicator LEDs for the five protocols.
Table 3. RT Ethernet Indicator LED Summary
LED Powerlink EtherCAT Ethernet/IP SERCOS-III PROFINET
Link and activity
LED
Color Green (per port) Green (per port) Green (per port) Green (per port) Green (per port)
Behavior Solid on link;
blink on activity Solid on link; blink on activity Solid on link;
blink on activity
(optional) Solid on link
Solid on link;
blink on
command from
PLC (not on
activity)
Activity LED Color – – Orange (per
port) Orange (per port) –
Behavior – – Blink on activity Blink on activity –
Status and error
LED Color Bicolor: green
and red ––––
Behavior – – – – –
RUN LED
Color
– Green – – –
ERROR LED – Red – – –
Module status – – Bicolor: green
and red – –
Network status – – Bicolor: green
and red – –
S LED – – – Tricolor: orange,
green, and red –
SD1 LED – – – Tricolor: orange,
green, and red –
ON Color – – – – Green
Behavior – – – – Device is on
BF Color – – – – Red
SF – – – – Red
MT – – – – Yellow

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Figure 10 shows the LED configuration on the AMIC110 ICE. To attain REACH compliance, the multicolor
LEDs were separated to three single LEDs. This shows the LED functionality but must be combined with a
lens or changed to a multicolor LED to comply with standards such as SERCOS-III, Ethernet/IP, and
Powerlink. The parallel resistors R188, R189, R235, and R236 are required for the boot-time configuration
of the PHY.
Figure 10. AMIC110 ICE Indicator LEDs
2.6 JTAG Emulation Circuit
The AMIC110 ICE supports a compact TI 20-pin connector in the design. An external emulator and
debugger pod, such as the XDS100 or the XDS200, may be connected to the 20-pin connector for JTAG
connectivity. For more information on JTAG connections, see JTAG Connectors.

AMIC110
DDR3
MT41K256M16TW
VDDS_DDR
DDR_D[0:15]
DDR_DQS[0:1]
DDR_DQSn[0:1]
DDR_DQM[0:1]
1.5 V
1.5 V
DDR_CKn
DDR_CK
DDR_BA[0:2]
DDR_A[0:14]
DDR_CASn
DDR_WEn
DDR_CSn
DDR_CKE
DDR_RESETn
DDR_RASn
DDR_ODT
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VDD
VDDQ
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2.7 Memory Interfaces
2.7.1 DDR3 Interface
The AMIC110 ICE supports one 4-Gb (256Mx16) DDR3 chip (MT41K256M16TW-107 from Micron) to
obtain a memory size of 512MB. Figure 11 shows the DDR3 circuit.
NOTE: No DDR or other external RAM is required when the EtherCAT slave stack runs on an
external host processor (such as the C2000).
Figure 11. DDR3 Interface

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2.7.2 DDR Timing Control and Software Leveling
See AM335x DDR PHY register configuration for DDR3 using Software Leveling for more information
about software leveling.
Table 4 lists the seed values used as inputs to the Code Composer Studio™ (CCS) based application.
Table 4. Seed Values
Parameters
DDR3 clock frequency 400 MHz
Invert Clkout 0
Trace length (inches)
Byte 0 Byte 1
CK trace 0.94463 0.94463
DQS trace 0.915736 0.797452
Seed values (per byte lane)
WR DQS 0 2
RD DQS 34 34
RD DQS GATE 67 62
Seed values to input to program
WR DQS 0
RD DQS 1A
RD DQS GATE 32
The following code snippet shows the optimum values obtained after running the
DDR3_slave_ratio_search_auto.out file in CCS.
******************************************************
The Slave Ratio Search Program Values are...
***************************************************************
PARAMETER MAX | MIN | OPTIMUM | RANGE
***************************************************************
0x06d | 0x007 | 0x03a | 0x066
DATA_PHY_FIFO_WE_SLAVE_RATIO 0x12c | 0x000 | 0x096 | 0x12c
DATA_PHY_WR_DQS_SLAVE_RATIO 0x070 | 0x003 | 0x039 | 0x06d
DATA_PHY_WR_DATA_SLAVE_RATIO 0x0a8 | 0x03b | 0x071 | 0x06d
**************************************************************

AMIC110 SPI Flash
3.3 V
SPI_CLK
SPI_D0
SPI_D1
SPI_CS0#
3.3 V3.3 V 3.3 V
CLK
D0
D1
CS#
HOLD#
WP#
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2.7.3 SPI Flash
The AMIC110 ICE includes an 8-MB serial Flash (W25Q64FV from Winbond) that is interfaced to the
AMIC110 (see Figure 12). The SPI port of the ICE is shared with the SPI Flash and the LaunchPad that is
selected through chip select SPI0_CS0 and SPI1_CS0.
The hold function (to pause the serial communication without deselecting the device) is disabled with a
pullup resistor attached to the HOLD# pin. Pullup options are provided for the write protect signal that is
enabled in the default configuration.
Figure 12. SPI Flash Interface

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2.7.4 CAT24C256 EEPROM Board ID Memory
The AMIC110 ICE is identified by its version and serial number, which are stored in the onboard
EEPROM. The EEPROM is accessible on the address 0x50.
The AMIC110 ICE includes a CAT24C256W I2C EEPROM ID memory. The first 72 bytes of addressable
EEPROM memory are preprogrammed with identification information for each board. The remaining
32696 bytes are available to the user for data or code storage.
NOTE: The first 72 bytes of addressable EEPROM memory should never be overwritten.
Table 5 lists the ID memory header information.
Table 5. ID Memory Header Information
Name Size (Bytes) Contents Description
Header 4 MSB 0xEE3355AA LSB Start code
Board name 8 ICE110 Board name in ASCII
Version 4 1.1 Hardware revision code in ASCII
Serial number 12 WWYY4P63nnnn WW – week of production
YY – year of production
4P63 – AMIC110 ICE code
nnnn – serial number
Configuration option 32 Reserved for board configuration codes.
Available 32696 Available space for user data or code.

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AMIC110 Industrial Communications Engine (AMIC110 ICE)
3 AMIC110 ICE Physical Specifications
3.1 Board Layout
The ICE board has dimensions of 2.204 inches × 3.464 inches (56 mm × 88 mm), and is an 8-layer board
fabricated with epoxy fiberglass FR4 grade material. Figure 13 shows the top view of the AMIC110 ICE.
Figure 13. AMIC110 ICE (Top)

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AMIC110 Industrial Communications Engine (AMIC110 ICE)
Figure 14 shows the bottom view of the AMIC110 board.
Figure 14. AMIC110 ICE (Bottom)
3.2 Connector Index
The AMIC110 ICE has several connectors that provide access to various interfaces on the board; Table 6
lists these connectors.
Table 6. AMIC110 ICE Connectors
Connector Part Number Pins Function
J1 FTR-110-51-S-D-06 20 JTAG Header
J2 DF40HC(4.0)-60DS-0.4V(51) 60 High Density Interface Connector
J3 PEC06SAAN 6 UART Header
J4,J5 SSW-110-23-F-D 20 LaunchPad Headers
J7, J8 1-406541-1 8 Ethernet Connectors

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AMIC110 Industrial Communications Engine (AMIC110 ICE)
3.2.1 JTAG Header
Table 7 lists the JTAG header pinout information.
Table 7. JTAG Header Pinout
Pin Number Description Pin Number Description
1 JTAG test mode select 2 Reset
3 JTAG test data input 4 JTAG test data select
5 Power supply 6 NC
7 JTAG test data output 8 Ground
9 Return Clock 10 Ground
11 Clock into the core 12 Ground
13 Emulation 0 14 Emulation 1
15 Emulation Reset 16 JTAG test data output
17 Emulation 2 18 Emulation 3
19 Emulation 4 20 Ground
3.2.2 UART Header
Table 8 lists the UART header pinout information.
Table 8. UART Header Pinout
Pin Number Description
1 Ground
2 NC
3 NC
4 UART receive
5 UART transmit
6 NC
3.2.3 High Density Interface Connector
Table 9 lists the high density interface connector pinout information.
Table 9. High Density Interface Connector Pinout
Pin Number Description Pin Number Description
1 NC 2 Ground
3 NC 4 NC
5 NC 6 NC
7 NC 8 NC
9 Ground 10 NC
11 NC 12 NC
13 NC 14 NC
15 NC 16 NC
17 NC 18 NC
19 EtherCAT ready signal 20 Ground
21 NC 22 NC
23 NC 24 NC
25 NC 26 NC
27 NC 28 NC
29 Chip-select signal; active low 30 Ground