Texas Instruments TMS320DM35 Series User manual

TMS320DM35x Digital MediaSystem-on-Chip (DMSoC)Pulse-Width Modulator (PWM)
Reference Guide
Literature Number: SPRUEE7AMay 2006 – Revised September 2007

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Contents
Preface ............................................................................................................................... 51 Introduction ................................................................................................................ 81.1 Purpose of the Peripheral ....................................................................................... 81.2 Features ........................................................................................................... 81.3 Industry Standard(s) Compliance Statement ................................................................. 82 Peripheral Architecture ................................................................................................ 92.1 Clock Control ..................................................................................................... 92.2 Signal Descriptions .............................................................................................. 92.3 Functional Operation ........................................................................................... 102.4 Reset Considerations .......................................................................................... 122.5 Initialization ...................................................................................................... 122.6 Interrupt Support ................................................................................................ 122.7 EDMA Event Support .......................................................................................... 132.8 Power Management ............................................................................................ 132.9 Emulation Considerations ..................................................................................... 133 Registers .................................................................................................................. 143.1 Pulse Width Modulator (PWM) Peripheral Identification Register (PID) ................................. 143.2 Pulse Width Modulator (PWM) Peripheral Control Register (PCR) ...................................... 143.3 Pulse Width Modulator (PWM) Configuration Register (CFG) ............................................ 153.4 Pulse Width Modulator (PWM) Start Register (START) ................................................... 163.5 Pulse Width Modulator (PWM) Repeat Count Register (RPT) ........................................... 163.6 Pulse Width Modulator (PWM) Period Register (PER) .................................................... 173.7 Pulse Width Modulator (PWM) First-Phase Duration Register (PH1D) ................................. 17
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List of Figures
1 PWM Waveform Polarity Control (PWM_RPT = 2, for 3 periods) ..................................................... 92 PWM One-Shot Mode Operation (P1OUT = 1, INACTOUT = 0, EVTRIG = 0, PWM_RPT = 2) ................ 103 PWM Event-Triggered One-Shot Mode Operation (P1OUT = 1, INACTOUT = 0, EVTRIG = 1,PWM_RPT = 1) ............................................................................................................. 114 PWM Continuous Mode Operation (P1OUT = 1, INACTOUT = 0, EVTRIG = 1, PWM_RPT = 0) .............. 125 Pulse Width Modulator (PWM) Peripheral Identification Register (PID) ............................................ 146 Pulse Width Modulator (PWM) Peripheral Control Register (PCR) .................................................. 157 Pulse Width Modulator (PWM) Configuration Register (CFG) ....................................................... 158 Pulse Width Modulator (PWM) Start Register (START) .............................................................. 169 Pulse Width Modulator (PWM) Repeat Count Register (RPT) ....................................................... 1710 Pulse Width Modulator (PWM) Period Register (PER) ................................................................ 1711 Pulse Width Modulator (PWM) First-Phase Duration Register (PH1D) ............................................. 17
List of Tables
1 Pulse Width Modulator (PWM) Registers ............................................................................... 142 Pulse Width Modulator (PWM) Peripheral Identification Register (PID) Field Descriptions ...................... 143 Pulse Width Modulator (PWM) Peripheral Control Register (PCR) Field Descriptions ........................... 154 Pulse Width Modulator (PWM) Configuration Register (CFG) Field Descriptions ................................. 155 Pulse Width Modulator (PWM) Start Register (START) Field Descriptions ........................................ 166 Pulse Width Modulator (PWM) Repeat Count Register (RPT) Field Descriptions ................................. 177 Pulse Width Modulator (PWM) Period Register (PER) Field Descriptions ......................................... 178 Pulse Width Modulator (PWM) First-Phase Duration Register (PH1D) Field Descriptions ....................... 18
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PrefaceSPRUEE7A – May 2006 – Revised September 2007
Read This First
This document describes the Pulse-Width Modulator (PWM) on the TMS320DM35x Digital MediaSystem-on-Chip (DMSoC).
Notational Conventions
This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.
TMS320DM355 Digital Media System-on-Chip (DMSoC)
Related Documentation From Texas InstrumentsThe following documents describe the TMS320DM355 Digital Media System-on-Chip (DMSoC). Copies ofthese documents are available on the internet at www.ti.com. Contact your TI representative for Extranetaccess.
SPRS463— TMS320DM355 Digital Media System-on-Chip (DMSoC) Data Manual This documentdescribes the overall TMS320DM355 system, including device architecture and features, memorymap, pin descriptions, timing characteristics and requirements, device mechanicals, etc.
SPRZ264— TMS320DM355 DMSoC Silicon Errata Describes the known exceptions to the functionalspecifications for the TMS320DM355 DMSoC.
SPRUFB3— TMS320DM355 ARM Subsystem Reference Guide This document describes the ARMSubsystem in the TMS320DM355 Digital Media System-on-Chip (DMSoC). The ARM subsystem isdesigned to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM isresponsible for configuration and control of the device; including the components of the ARMSubsystem, the peripherals, and the external memories.
SPRUED1— TMS320DM35x DMSoC Asynchronous External Memory Interface (EMIF) ReferenceGuide This document describes the asynchronous external memory interface (EMIF) in theTMS320DM35x Digital Media System-on-Chip (DMSoC). The EMIF supports a glueless interface toa variety of external devices.
SPRUED2— TMS320DM35x DMSoC Universal Serial Bus (USB) Controller Reference Guide Thisdocument describes the universal serial bus (USB) controller in the TMS320DM35x Digital MediaSystem-on-Chip (DMSoC). The USB controller supports data throughput rates up to 480 Mbps. Itprovides a mechanism for data transfer between USB devices and also supports host negotiation.
SPRUED3— TMS320DM35x DMSoC Audio Serial Port (ASP) Reference Guide This documentdescribes the operation of the audio serial port (ASP) audio interface in the TMS320DM35x DigitalMedia System-on-Chip (DMSoC). The primary audio modes that are supported by the ASP are theAC97 and IIS modes. In addition to the primary audio modes, the ASP supports general serial portreceive and transmit operation, but is not intended to be used as a high-speed interface.
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TMS320DM355 Digital Media System-on-Chip (DMSoC)
SPRUED4— TMS320DM35x DMSoC Serial Peripheral Interface (SPI) Reference Guide Thisdocument describes the serial peripheral interface (SPI) in the TMS320DM35x Digital MediaSystem-on-Chip (DMSoC). The SPI is a high-speed synchronous serial input/output port that allowsa serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at aprogrammed bit-transfer rate. The SPI is normally used for communication between the DMSoCand external peripherals. Typical applications include an interface to external I/O or peripheralexpansion via devices such as shift registers, display drivers, SPI EPROMs and analog-to-digitalconverters.
SPRUED9— TMS320DM35x DMSoC Universal Asynchronous Receiver/Transmitter (UART)Reference Guide This document describes the universal asynchronous receiver/transmitter(UART) peripheral in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The UARTperipheral performs serial-to-parallel conversion on data received from a peripheral device, andparallel-to-serial conversion on data received from the CPU.
SPRUEE0— TMS320DM35x DMSoC Inter-Integrated Circuit (I2C) Peripheral Reference Guide Thisdocument describes the inter-integrated circuit (I2C) peripheral in the TMS320DM35x Digital MediaSystem-on-Chip (DMSoC). The I2C peripheral provides an interface between the DMSoC and otherdevices compliant with the I2C-bus specification and connected by way of an I2C-bus. Externalcomponents attached to this 2-wire serial bus can transmit and receive up to 8-bit wide data to andfrom the DMSoC through the I2C peripheral. This document assumes the reader is familiar with theI2C-bus specification.
SPRUEE2— TMS320DM35x DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card ControllerReference Guide This document describes the multimedia card (MMC)/secure digital (SD) cardcontroller in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The MMC/SD card isused in a number of applications to provide removable data storage. The MMC/SD controllerprovides an interface to external MMC and SD cards. The communication between the MMC/SDcontroller and MMC/SD card(s) is performed by the MMC/SD protocol.
SPRUEE4— TMS320DM35x DMSoC Enhanced Direct Memory Access (EDMA) Controller ReferenceGuide This document describes the operation of the enhanced direct memory access (EDMA3)controller in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The EDMA controller'sprimary purpose is to service user-programmed data transfers between two memory-mapped slaveendpoints on the DMSoC.
SPRUEE5— TMS320DM35x DMSoC 64-bit Timer Reference Guide This document describes theoperation of the software-programmable 64-bit timers in the TMS320DM35x Digital MediaSystem-on-Chip (DMSoC). Timer 0, Timer 1, and Timer 3 are used as general-purpose (GP) timersand can be programmed in 64-bit mode, dual 32-bit unchained mode, or dual 32-bit chained mode;Timer 2 is used only as a watchdog timer. The GP timer modes can be used to generate periodicinterrupts or enhanced direct memory access (EDMA) synchronization events and Real TimeOutput (RTO) events (Timer 3 only). The watchdog timer mode is used to provide a recoverymechanism for the device in the event of a fault condition, such as a non-exiting code loop.
SPRUEE6— TMS320DM35x DMSoC General-Purpose Input/Output (GPIO) Reference Guide Thisdocument describes the general-purpose input/output (GPIO) peripheral in the TMS320DM35xDigital Media System-on-Chip (DMSoC). The GPIO peripheral provides dedicated general-purposepins that can be configured as either inputs or outputs. When configured as an input, you candetect the state of the input by reading the state of an internal register. When configured as anoutput, you can write to an internal register to control the state driven on the output pin.
SPRUEE7— TMS320DM35x DMSoC Pulse-Width Modulator (PWM) Reference Guide This documentdescribes the pulse-width modulator (PWM) peripheral in the TMS320DM35x Digital MediaSystem-on-Chip (DMSoC).
SPRUEH7— TMS320DM35x DMSoC DDR2/Mobile DDR (DDR2/mDDR) Memory ControllerReference Guide This document describes the DDR2 / mobile DDR memory controller in theTMS320DM35x Digital Media System-on-Chip (DMSoC). The DDR2 / mDDR memory controller isused to interface with JESD79D-2A standard compliant DDR2 SDRAM and mobile DDR devices.
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TMS320DM355 Digital Media System-on-Chip (DMSoC)
SPRUF71— TMS320DM35x DMSoC Video Processing Front End (VPFE) Users Guide This documentdescribes the Video Processing Front End (VPFE) in the TMS320DM35x Digital MediaSystem-on-Chip (DMSoC).
SPRUF72— TMS320DM35x DMSoC Video Processing Back End (VPBE) Users Guide This documentdescribes the Video Processing Back End (VPBE) in the TMS320DM35x Digital MediaSystem-on-Chip (DMSoC).
SPRUF74— TMS320DM35x DMSoC Real Time Out (RTO) Controller Reference Guide This documentdescribes the Real Time Out (RTO) controller in the TMS320DM35x Digital Media System-on-Chip(DMSoC).
The following documents describe TMS320DM35x Digital Media System-on-Chip (DMSoC) that are notavailable by literature number. Copies of these documents are available (by title only) on the internet atwww.ti.com. Contact your TI representative for Extranet access.
—TMS320DM35x DDR2 / mDDR Board Design Application Note This provides board designrecommendations and guidelines for DDR2 and mobile DDR.
—TMS320DM35x USB Board Design and Layout Guidelines Application Note This providesboard design recommendations and guidelines for high speed USB.
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1 Introduction
1.1 Purpose of the Peripheral
1.2 Features
1.3 Industry Standard(s) Compliance Statement
Reference GuideSPRUEE7A – May 2006 – Revised September 2007
Pulse-Width Modulator (PWM) Peripheral
This document describes the pulse-width modulator (PWM) peripheral in the TMS320DM35x Digital MediaSystem-on-Chip (DMSoC).
The pulse width modulator (PWM) feature is very common in embedded systems. It provides a way togenerate a pulse periodic waveform for motor control or can act as a digital-to-analog converter with someexternal components. This PWM peripheral is basically a timer with a period counter and a first-phaseduration comparator, where bit width of the period and first-phase duration are both programmable.
The PWM has the following features:•32-bit period counter•32-bit first-phase duration counter•8-bit repeat counter for one-shot operation. One-shot operation will produce N + 1 periods of thewaveform, where N is the repeat counter value.•Configurable to operate in either one-shot or continuous mode.•One-shot operation can be triggered by the CCD VSYNC output of the video processing subsystem toallow any of the PWM instantiations to be used as a CCD timer.•Configurable PWM output pin inactive state.•Interrupt and EDMA synchronization events.•Emulation support for stop or free-run operation.
The PWM does not conform to any recognized industry standards.
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2 Peripheral Architecture
2.1 Clock Control
2.2 Signal Descriptions
Start Stop
P1D
PER+1
Inactive low,
high−then−low
Inactive low,
low−then−high
inactive high,
high−then−low
Inactive high
low−then−high
Peripheral Architecture
The PWM peripheral is driven by the auxiliary clock of the PLL controller. The frequency of the auxiliaryclock is equal to the input reference clock of the PLL controller, and therefore is not affected by themultiplier and divider values of the PLL controller. The PWM timer counts are referenced to this clock. Formore information on the PLL controller and device clocking, refer to the TMS320DM35x DMSoC ARMSubsystem Reference Guide (SPRUEE8).
Each instance of the PWM peripheral has a single output signal, PWM n. The output signal is driven basedon the state of the PWM as described below:•Inactive state: When the PWM is idle, the output pin is driven to its inactive output level. This inactivelogic state is determined by configuring the INACTOUT bit in the PWM configuration register (CFG).•First-phase active state: During the first phase of an active PWM period, the output signal is driven tothe state defined in the P1OUT bit in the PWM configuration register (CFG). The duration of the firstphase is controlled by the PWM first-phase duration register (PH1D). The duration of the entire periodis controlled by the PWM period register (PER).•Second-phase active state: After the first phase of the period is complete, the output signal is drivento the opposite state of the first phase for the remainder of the period (the second phase).
Figure 1 shows the behavior of PWM nwith different combination of active and inactive polarities.
Figure 1. PWM Waveform Polarity Control (PWM_RPT = 2, for 3 periods)
If PH1D value is 0, the first phase has zero time and the opposite of the first-phase output value is drivenon PWM nfor the entire period. If PH1D is greater than or equal to (PER + 1), the first phase is 100% ofthe period and the P1OUT output level is sent for the duration of the period.
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2.3 Functional Operation
2.3.1 One-Shot Mode Operation
Write
PWM START PWM START
Write
P1D
PER+1
PWM output
Interrupt
2.3.1.1 Event-Triggered One-Shot Mode Operation
Peripheral Architecture
The PWM module can operate in either one-shot or continuous mode. In both modes, the PWM peripheralhas a first-phase duration register (PH1D) and a period register (PER) to specify, respectively, thefirst-phase duration and period of the waveform. The first-phase output level can be configured to beeither high or low in the P1OUT bit of the PWM configuration register (CFG) and the second phase outputis automatically the opposite polarity of the first-phase level. The inactive state before and after the PWMoperation can also be configured to be either a 0 or a 1 in the INACTOUT bit of CFG. For one-shot modeoperation, see Section 2.3.1 ; for continuous mode operation, see Section 2.3.2 .
In one-shot mode operation, the PWM produces a series of periods but does not run continuously. Thenumber of periods in the series is controlled by the repeat count contained in the PWM repeat countregister (RPT). To select one-shot mode, configure the MODE bit in the PWM configuration register (CFG)to 1h.
For one-shot mode operation, the PWM should first be configured for mode, period, and first-phaseduration, along with other configuration options. The PWM uses the last programmed set of parametersonce it is started by writing a 1 to the START bit in the PWM start register (START).
Once started, the PWM asserts/deasserts the output as configured, driving to the first-phase output levelduring the first phase and the opposite level during the second phase. When the prescribed number ofRPT + 1 periods of pulses expire, the peripheral sends an interrupt to the system (if the interrupt isenabled in CFG). The PWM then becomes inactive until the START bit is written a 1 again.
The PWM is stopped during one-shot mode operation by changing the MODE bit to 0 (disable). When thePWM is disabled, the output is immediately driven to the configured inactive state.
Figure 2 shows the one-shot mode operation. The waveform generation is started by writing to the STARTbit (assuming event triggering is disabled). After RPT + 1 number of periods, the waveform stops and aninterrupt is generated. The polarity is configured as inactive low, first phase high-then-low.
Figure 2. PWM One-Shot Mode Operation (P1OUT = 1, INACTOUT = 0, EVTRIG = 0, PWM_RPT = 2)
In one-shot mode, the PWM senses a rising or falling transition on an event-trigger input signal to start theoperation. This event trigger input is synchronized to the PWM clock inside the module and is driven bythe video processing subsystem CCDC_VD output signal. This capability is provided to allow the PWM tobe used as a CCD timer.
The trigger event can be detected on the rising edge or the falling edge of CCDC_VD. After eventtriggering is enabled as part of the configuration process, a write to the PWM START register (START)starts the sensing circuitry in the PWM and after the first event, the PWM starts the period counting.
Figure 3 shows the event-triggered one-shot mode operation. Note that each subsequent event does notrestart period counting. It takes another write to the START bit to sense the event signal again. Also note,that events received within the PWM period are ignored as well.
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Write
PWM START
Configure
PWM
Trigger event
PWM output
Interrupt
Write
PWM START
P1D
PER+1
Ignored events
2.3.2 Continuous Operation
Peripheral Architecture
The PWM is stopped from the event-triggered one-shot mode operation by changing the MODE bit to 0(disable). When the PWM is disabled, the output is immediately driven to the configured inactive state.
Figure 3. PWM Event-Triggered One-Shot Mode Operation (P1OUT = 1, INACTOUT = 0, EVTRIG = 1,PWM_RPT = 1)
In continuous mode operation, the PWM produces the repeating output waveforms continuously withoutstopping. For continuous mode operation, the PWM should first be configured for mode, period, andfirst-phase duration, along with other configuration options. The PWM uses the last programmed set ofparameters once it is started by writing a 1 to the START bit in the PWM start register (START). Unlike theone-shot mode, the repeat count does not affect the continuous operation. To select continuous mode,configure the MODE bit in the PWM configuration register (CFG) to 2h.
Once started, the PWM asserts/deasserts the output as configured, driving to first-phase output levelduring the first phase and the opposite level during the second phase. Once a period expires, the nextperiod starts. When a period starts, the PWM copies the period and first-phase duration registers into aset of internal shadow registers and maintains the counts there. An interrupt is also generated (if enabled)after the registers are copied. This buffering scheme and interrupt timing allows the CPU or EDMA toprogram the durations for the next period while the current period is running.
The PWM is stopped during the continuous mode operation by either disabling it or by reconfiguring it toone-shot mode using the MODE bit. Whenever the PWM is disabled, the output is immediately driven tothe configured inactive state. To allow the PWM to stop gracefully from continuous operation, upon aninterrupt, configure the PWM to one-shot mode operation. The PWM then operates for RPT + 1 periodsand stops by itself (sending an interrupt, if enabled). Note that unlike normal one-shot mode operation,another write to the START bit is not required for the one-shot mode operation to start.
While operating in continuous mode, the minimum period for the PWM is 8 cycles.
Figure 4 shows programming of period/first-phase-duration, and the resulting output waveform, andinterrupt signal for continuous operation.
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START
PERa
P1Da
PERb
P1Db Configure to
one−shot
P1Da P1Db P1Db
PERa+1 PERb+1 PERb+1
Period/P1D not
changed, previous
values applied
PWM output
Interrupt
2.4 Reset Considerations
2.4.1 Software Reset Considerations
2.4.2 Hardware Reset Considerations
2.5 Initialization
2.6 Interrupt Support
Peripheral Architecture
Figure 4. PWM Continuous Mode Operation (P1OUT = 1, INACTOUT = 0, EVTRIG = 1, PWM_RPT = 0)
A software reset (such as a reset generated by the emulator) causes the PWM peripheral registers toreturn to their default state after reset.
A hardware reset of the processor causes the PWM peripheral registers to return to their default valuesafter reset.
To initialize and start the PWM:1. Write the desired period duration to the PWM period register (PER)2. Write the desired first-phase duration to the PWM first-phase duration register (PH1D)3. If one-shot mode will be used, write the desired repeat value to the PWM repeat count register (RPT).4. Configure the operating mode, inactive output level, first-phase output level, and event trigger behaviorin the CFG register.5. If interrupts will be used, enable interrupts in the PWM configuration register (CFG).6. Configure how the PWM responds to emulation suspend events in the PWM peripheral control register(PCR). See Section 2.9 for more information.7. Start the PWM by writing a 1 to the START bit in the PWM start register (START).
There is a single interrupt from the CPU interrupt controller for each PWM instance.
When the PWM is configured in one-shot mode and the interrupt bit (INTEN) in the PWM CFG register isenabled, the peripheral generates an interrupt when RPT+1 number of periods have been completed.
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2.6.1 Interrupt Multiplexing
2.7 EDMA Event Support
2.8 Power Management
2.9 Emulation Considerations
Peripheral Architecture
When the PWM is configured in continuous mode and the interrupt bit (INTEN) in the PWM configurationregister (CFG) is enabled, the PWM peripheral generates an interrupt every period after the first-phaseduration register and period register values have been copied to the associated shadow registers. Thisevent indicates it is safe to program the duration values for the next period.
The interrupts from the PWM peripheral instances are not multiplexed with any other interrupt sources onthe DM35x DMSoC.
The PWM provides EDMA synchronization events to allow the EDMA to update the values for thefirst-phase duration and period registers. The EDMA events occur at the same times as the interruptspreviously described. For detailed information on EDMA synchronization events, see the device-specificdata manual.
The PWM peripheral can be placed in reduced-power modes to conserve power during periods of lowactivity. The power management of the PWM peripheral is controlled by the processor Power and SleepController (PSC). The PSC acts as a master controller for power management for all of the peripherals onthe device. For detailed information on power management procedures using the PSC, see theTMS320DM35x DMSoC ARM Subsystem Reference Guide (SPRUEE8).
When the PWM peripheral exits the power-down state, it will resume normal function (no register valuesare altered), but a write to the START bit is required to restart operation. If the PWM was configured to beevent-triggered before power-down, a trigger event will also be required to restart the PWM after it exitsthe power-down state.
The PWM implements a FREE bit in the PWM peripheral control register (PCR) to determine operationduring an emulation stop. If FREE is set to 1, the PWM continues to run during an emulation stop; if FREEis cleared to 0 (default), then the following occurs:•Suspend operation immediately.•Freeze PWM output at its current state.•Suspend internal counters.•Suspend interrupt generation.•Keep the event capture circuitry functional. If the PWM is configured for event-triggered operation andis waiting for an event, an event coming in during suspend is registered and the PWM period starts assoon as the emulation suspend is deasserted.
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3 Registers
3.1 Pulse Width Modulator (PWM) Peripheral Identification Register (PID)
3.2 Pulse Width Modulator (PWM) Peripheral Control Register (PCR)
Registers
Table 1 lists the memory-mapped registers for the pulse-width modulator (PWM) controller. See thedevice-specific data manual for the memory addresses of these registers.
Table 1. Pulse Width Modulator (PWM) Registers
Offset Acronym Register Description Section
00h PID PWM Peripheral Identification Register Section 3.104h PCR PWM Peripheral Control Register Section 3.208h CFG PWM Configuration Register Section 3.30Ch START PWM Start Register Section 3.410h RPT PWM Repeat Count Register Section 3.514h PER PWM Period Register Section 3.618h PH1D PWM First-Phase Duration Register Section 3.7
The pulse-width modulator (PWM) peripheral identification register (PID) contains identification data (type,class, and revision) for the peripheral. PID is shown in Figure 5 and described in Table 2 .
Figure 5. Pulse Width Modulator (PWM) Peripheral Identification Register (PID)
31 24 23 16Reserved TIDR-0 R-02h
15 8 7 0CID REVR-07h R-0LEGEND: R = Read only; - n= value after reset
Table 2. Pulse Width Modulator (PWM) Peripheral Identification Register (PID) Field Descriptions
Bit Field Value Description
31-24 Reserved 0 Reserved23-16 TID 0-FFh Identifies type of peripheral.2h15-8 CID 0-FFh Identifies class of peripheral.7h7-0 REV 0-FFh Identifies revision of peripheral.0 Current revision of peripheral.
The pulse-width modulator (PWM) peripheral control register (PCR) is shown in Figure 6 and described inTable 3 .
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3.3 Pulse Width Modulator (PWM) Configuration Register (CFG)
Registers
Figure 6. Pulse Width Modulator (PWM) Peripheral Control Register (PCR)
31 16Reserved
R-0
15 1 0Reserved FREER-0 R/W-0LEGEND: R/W = Read/Write; R = Read only; - n= value after reset
Table 3. Pulse Width Modulator (PWM) Peripheral Control Register (PCR) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reserved0 FREE Free-running enable mode bit. This bit determines the behavior of the PWM when an emulationsuspend event occurs (halt or breakpoint).0 The PWM stops immediately.1 Free-running mode is enabled; the PWM continues to run free.
The pulse-width modulator (PWM) configuration register (CFG) is shown in Figure 7 and described inTable 4 .
Figure 7. Pulse Width Modulator (PWM) Configuration Register (CFG)31 18 17 16Reserved OPST CURLEVR-0 R-0 R-0
15 7 6 5 4 3 2 1 0Reserved INTEN INACTOUT P1OUT EVTRIG MODER-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0LEGEND: R/W = Read/Write; R = Read; - n= value at reset
Table 4. Pulse Width Modulator (PWM) Configuration Register (CFG) Field Descriptions
Bit Field Value Description
31-18 Reserved 0 Reserved17 OPST PWM operation status.0 Idle mode1 Running mode16 CURLEV PWM output status.0 Low1 High15-7 Reserved 0 Reserved6 INTEN Interrupt enable.0 Disable interrupt1 Enable interrupt5 INACTOUT Inactive output level.0 Low1 High
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3.4 Pulse Width Modulator (PWM) Start Register (START)
3.5 Pulse Width Modulator (PWM) Repeat Count Register (RPT)
Registers
Table 4. Pulse Width Modulator (PWM) Configuration Register (CFG) Field Descriptions (continued)
Bit Field Value Description
4 P1OUT First-phase output level.0 Low1 High3-2 EVTRIG 0-3h Event trigger.0 Disable1h Positive edge triggered2h Negative edge triggered3h Reserved1-0 MODE 0-3h Operating mode.0 Disable1h One shot mode2h Continuous mode3h Reserved
The pulse-width modulator (PWM) start register (START) is shown in Figure 8 and described in Table 5 .
Figure 8. Pulse Width Modulator (PWM) Start Register (START)
31 16Reserved
R-0
15 1 0Reserved STARTR-0 W-0LEGEND: R/W = Read/Write; W= Write only; - n= value after reset
Table 5. Pulse Width Modulator (PWM) Start Register (START) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reserved0 START PWM start bit. Writing a 1 to this bit starts the PWM.0 No effect1 Start PWM.
The pulse-width modulator (PWM) repeat count register (RPT) is shown in Figure 9 and described inTable 6 .
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3.6 Pulse Width Modulator (PWM) Period Register (PER)
3.7 Pulse Width Modulator (PWM) First-Phase Duration Register (PH1D)
Registers
Figure 9. Pulse Width Modulator (PWM) Repeat Count Register (RPT)
31 16Reserved
R-0
15 8 7 0Reserved RPTR-0 R/W-0LEGEND: R/W = Read/Write; R = Read only; - n= value after reset
Table 6. Pulse Width Modulator (PWM) Repeat Count Register (RPT) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved7-0 RPT 0-FFh One-shot mode repeat count is RPT + 1.
The pulse-width modulator (PWM) period register (PER) is shown in Figure 10 and described in Table 7 .
Figure 10. Pulse Width Modulator (PWM) Period Register (PER)
31 16PER
R/W-0
15 0PER
R/W-0LEGEND: R/W = Read/Write; - n= value after reset
Table 7. Pulse Width Modulator (PWM) Period Register (PER) Field Descriptions
Bit Field Value Description
31-0 PER 0-FFFF FFFFh Output period is PER + 1 clock cycles.
The pulse-width modulator (PWM) first-phase duration register (PH1D) is shown in Figure 11 anddescribed in Table 8 .
Figure 11. Pulse Width Modulator (PWM) First-Phase Duration Register (PH1D)
31 16PH1D
R/W-0
15 0PH1D
R/W-0LEGEND: R/W = Read/Write; - n= value after reset
SPRUEE7A – May 2006 – Revised September 2007 Pulse-Width Modulator (PWM) Peripheral 17Submit Documentation Feedback

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Registers
Table 8. Pulse Width Modulator (PWM) First-Phase Duration Register (PH1D) Field Descriptions
Bit Field Value Description
31-0 PH1D 0-FFFF FFFFh First-phase duration is PH1D clock cycles.
18 Pulse-Width Modulator (PWM) Peripheral SPRUEE7A – May 2006 – Revised September 2007Submit Documentation Feedback

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