Texas Instruments MSP430FG4616IPZ User manual

MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
1
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
DLow Supply-Voltage Range: 1.8 V to 3.6 V
DUltralow-Power Consumption:
− Active Mode: 400 μAat 1 MHz, 2.2 V
− Standby Mode: 1.3 μA
− Off Mode (RAM Retention): 0.22 μA
DFive Power-Saving Modes
DWake-Up From Standby Mode in Less
Than 6 μs
D16-Bit RISC Architecture, Extended
Memory, 125-ns Instruction Cycle Time
DThree Channel Internal DMA
D12-Bit A/D Converter With Internal
Reference, Sample-and-Hold, and Autoscan
Feature
DThree Configurable Operational Amplifiers
DDual 12-Bit Digital-to-Analog (D/A)
Converters With Synchronization
D16-Bit Timer_A With Three
Capture/Compare Registers
D16-Bit Timer_B With Seven
Capture/Compare-With-Shadow Registers
DOn-Chip Comparator
DSupply Voltage Supervisor/Monitor With
Programmable Level Detection
DSerial Communication Interface (USART1),
Select Asynchronous UART or
Synchronous SPI by Software
DUniversal Serial Communication Interface
− Enhanced UART Supporting
Auto-Baudrate Detection
− IrDA Encoder and Decoder
− Synchronous SPI
− I2CTM
DSerial Onboard Programming,
Programmable Code Protection by Security
Fuse
DBrownout Detector
DBasic Timer With Real Time Clock Feature
DIntegrated LCD Driver up to 160 Segments
With Regulated Charge Pump
DFamily Members Include:
− MSP430xG4616:
92KB+256B Flash or ROM Memory
4KB RAM
− MSP430xG4617:
92KB+256B Flash or ROM Memory,
8KB RAM
− MSP430xG4618:
116KB+256B Flash or ROM Memory,
8KB RAM
− MSP430xG4619:
120KB+256B Flash or ROM Memory,
4KB RAM
DFor Complete Module Descriptions, See the
MSP430x4xx Family User’s Guide
(
literature number SLAU056
)
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency.The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6 μs.
The MSP430xG461x series are microcontroller configurations with two 16-bit timers, a high-performance 12-bit
A/D converter, dual 12-bit D/A converters, three configurable operational amplifiers, one universal serial
communication interface (USCI), one universal synchronous/asynchronous communication interface
(USART), DMA, 80 I/O pins, and a liquid crystal display (LCD) driver with regulated charge pump.
Typical applications for this device include portable medical applications and e-meter applications.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright ©2011, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
2POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
AVAILABLE OPTIONS{
PACKAGED DEVICES}
TAPLASTIC 100-PIN TQFP
(PZ) PLASTIC 113-BALL BGA (ZQW)
MSP430FG4616IPZ MSP430FG4616IZQW
MSP430FG4617IPZ MSP430FG4617IZQW
MSP430FG4618IPZ MSP430FG4618IZQW
40°Cto85°C
MSP430FG4619IPZ MSP430FG4619IZQW
−40°C to 85°CMSP430CG4616IPZ MSP430CG4616IZQW
MSP430CG4617IPZ MSP430CG4617IZQW
MSP430CG4618IPZ MSP430CG4618IZQW
MSP430CG4619IPZ MSP430CG4619IZQW
†For the most current package and ordering information, see the Package Option
Addendum at the end of this document, or see the TI
web site at www.ti.com.
‡Package drawings, thermal data, and symbolization are available at
www.ti.com/packaging.
DEVELOPMENT TOOL SUPPORT
All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging
and programming through easy-to-use development tools. Recommended hardware options include:
DDebugging and Programming Interface
− MSP-FET430UIF (USB)
− MSP-FET430PIF (Parallel Port)
DDebugging and Programming Interface with Target Board
− MSP-FET430U100 (for PZ package)
DStandalone Target Board
− MSP-TS430PZ100 (for PZ package)
DProduction Programmer
− MSP-GANG430

MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
3
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
pin designation, MSP430xG461xIPZ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50 49 48 47 46 45 44 43 42 41 40
39
38
37 36 35 34 33 32 31 30 29 28 27 26
P1.7/CA1 P6.1/A1/OA0O P6.0/A0/OA0I0 RST/NMI XT2IN XT2OUT P1.3/TBOUTH/SVSOUT P1.4/TBCLK/SMCLK P1.5/TACLK/ACLK P1.6/CA0 P2.3/TB2
P9,2/S15 P9.1/S16 P9.0/S17 P8.5/S20 P8.0/S25 P7.7/S26 P7.6/S27 P7.5/S28 P7.4/S29
P7.2/UCA0SOMI/S31
P4.7/UCA0RXD/S34
P7.3/UCA0CLK/S30
P1.0/TA0
TDI/TCLK
TDO/TDI
P8.4/S21
SS1
DV P6.2/A2/OA0I1
P1.2/TA1
P8.1/S24
P4.6/UCA0TXD/S35
DVCC1
P6.3/A3/OA1O
P6.4/A4/OA1I0
P6.5/A5/OA2O
P6.6/A6/DAC0/OA2I0
P6.7/A7/DAC1/SVSIN
VREF+
XIN
XOUT
VeREF+/DAC0
VREF−/VeREF−
P5.1/S0/A12/DAC1
P5.0/S1/A13/OA1I1
P10.7/S2/A14/OA2I1
P10.6/S3/A15
P10.5/S4
P10.4/S5
P10.3/S6
P10.2/S7
P10.1/S8
P10.0/S9
P9.7/S10
P9.6/S11
P9.5/S12
P9.4/S13
P2.4/UCA0TXD
P2.5/UCA0RXD
P2.6/CAOUT
P2.7/ADC12CLK/DMAE0
P3.0/UCB0STE
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK
P3.4/TB3
P3.5/TB4
P3.6/TB5
P3.7/TB6
P4.0/UTXD1
P4.1/URXD1
DVSS2
DVCC2
LCDCAP/R33
P5.7/R23
P5.6/LCDREF/R13
P5.5/R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/STE1/S39
P8.6/S19 P8.3/S22 P8.2/S23
P7.0/UCA0STE/S33
P7.1/UCA0SIMO/S32
P4.5/UCLK1/S36
P4.4/SOMI1/S37 P4.3/SIMO1/S38
CC
AV
SS
AV
TCK TMS
P1.1/TA0/MCLK
P2.0/TA2 P2.1/TB0 P2.2/TB1
MSP430xG4616IPZ
MSP430xG4617IPZ
MSP430xG4618IPZ
MSP430xG4619IPZ
P9.3/S14 P8.7/S18

MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
4POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
pin designation, MSP430xG461xIZQW (top view)
A
B
C
D
E
F
G
H
J
K
L
M
123456789101112
NOTE: For terminal assignments, see the MSP430xG461x Terminal Functions table.

MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
5
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
functional block diagram
Oscillators
FLL+
RAM
4kB
8kB
8kB
4kB
Brownout
Protection
SVS/SVM
RST/NMI
DVCC1/2 DVSS1/2
MCLK
Watchdog
WDT+
15/16−Bit
Timer_A3
3CC
Registers
8MHz
CPUX
incl.16
Registers
XOUT/
XT2OUT
OA0, OA1,
OA2
3 Op Amps
Basic Timer
&
Real−Time
Clock
JTAG
Interface
LCD_A
160
Segments
1,2,3,4 Mux
Ports P1/P2
2x8 I/O
Interrupt
capability
USCI_A0:
UART,
IrDA, SPI
USCI_B0:
SPI,I2C
Comparator
_A
Flash(FG)
ROM(CG)
120kB
116kB
92kB
92kB
Hardware
Multiplier
MPY,
MPYS,
MAC,
MACS
Timer_B7
7CC
Registers,
Shadow
Reg
ADC12
12−Bit
12
Channels
DAC12
12−Bit
2Channels
Voltage out
USART1
UART,SPI
DMA
Controller
3 Channels
Ports
P3/P4
P5/P6
4x8 I/O
Ports
P7/P8
P9/P10
4x8/2x16 I/O
AVCC AVSS P1.x/P2.x
2x8
P3.x/P4.x
P5.x/P6.x
4x8
P7.x/P8.x
P9.x/P10.x
4x8/2x16
XIN/
XT2IN 22
SMCLK
ACLK
MDB
MAB
Enhanced
Emulation
(FG only)

MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
6POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
PZ NO. ZQW I/O DESCRIPTION
DVCC1 1 A1 Digital supply voltage, positive terminal
P6.3/A3/OA1O 2 B1 I/O General-purpose digital I/O / analog input a3—12-bit ADC / OA1 output
P6.4/A4/OA1I0 3 B2 I/O General-purpose digital I/O / analog input a4—12-bit ADC / OA1 input multiplexer
on +terminal and −terminal
P6.5/A5/OA2O 4 C2 I/O General-purpose digital I/O / analog input a5—12-bit ADC / OA2 output
P6.6/A6/DAC0/OA2I0 5 C1 I/O General-purpose digital I/O / analog input a6—12-bit ADC / DAC12.0 output / OA2
input multiplexer on +terminal and −terminal
P6.7/A7/DAC1/SVSIN 6 C3 I/O General-purpose digital I/O / analog input a7—12-bit ADC / DAC12.1 output /
analog input to brownout, supply voltage supervisor
VREF+ 7 D2 O Output of positive terminal of the reference voltage in the ADC
XIN 8 D1 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 9 E1 O Output terminal of crystal oscillator XT1
VeREF+/DAC0 10 E2 I/O Input for an external reference voltage to the ADC / DAC12.0 output
VREF−/VeREF− 11 E4 I Negative terminal for the ADC reference voltage for both sources, the internal
reference voltage, or an external applied reference voltage
P5.1/S0/A12/DAC1 (see Note 1) 12 F1 I/O General-purpose digital I/O / LCD segment output 0 / analog input a12 − 12−bit
ADC / DAC12.1 output
P5.0/S1/A13/OA1I1 (see Note 1) 13 F2 I/O General-purpose digital I/O / LCD segment output 1 / analog input a13 − 12−bit
ADC/OA1 input multiplexer on +terminal and −terminal
P10.7/S2/A14/OA2I1 (see Note 1) 14 E5 I/O General-purpose digital I/O / LCD segment output 2 / analog input a14 − 12−bit
ADC/OA2 input multiplexer on +terminal and −terminal
P10.6/S3/A15 (see Note 1) 15 G1 I/O General-purpose digital I/O / LCD segment output 3 / analog input a15 − 12−bit
ADC
P10.5/S4 16 G2 I/O General-purpose digital I/O / LCD segment output 4
P10.4/S5 17 F4 I/O General-purpose digital I/O / LCD segment output 5
P10.3/S6 18 H1 I/O General-purpose digital I/O / LCD segment output 6
P10.2/S7 19 H2 I/O General-purpose digital I/O / LCD segment output 7
P10.1/S8 20 F5 I/O General-purpose digital I/O / LCD segment output 8
P10.0/S9 21 J1 I/O General-purpose digital I/O / LCD segment output 9
P9.7/S10 22 J2 I/O General-purpose digital I/O / LCD segment output 10
P9.6/S11 23 G4 I/O General-purpose digital I/O / LCD segment output 11
P9.5/S12 24 K1 I/O General-purpose digital I/O / LCD segment output 12
P9.4/S13 25 L1 I/O General-purpose digital I/O / LCD segment output 13
P9.3/S14 26 M2 I/O General-purpose digital I/O / LCD segment output 14
P9.2/S15 27 K2 I/O General-purpose digital I/O / LCD segment output 15
P9.1/S16 28 L3 I/O General-purpose digital I/O / LCD segment output 16
P9.0/S17 29 M3 I/O General-purpose digital I/O / LCD segment output 17
P8.7/S18 30 H4 I/O General-purpose digital I/O / LCD segment output 18
P8.6/S19 31 L4 I/O General-purpose digital I/O / LCD segment output 19
P8.5/S20 32 M4 I/O General-purpose digital I/O / LCD segment output 20
P8.4/S21 33 G5 I/O General-purpose digital I/O / LCD segment output 21
P8.3/S22 34 L5 I/O General-purpose digital I/O / LCD segment output 22
NOTES: 1. Segments S0 through S3 are disabled when the LCD charge pump feature is enabled (LCDCPEN = 1) and cannot be used together
with the LCD charge pump. In addition, when using segments S0 through S3 with an external LCD voltage supply, VLCD ≤AVCC.

MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
7
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME NO.
PZ NO. ZQW I/O DESCRIPTION
P8.2/S23 35 M5 I/O General-purpose digital I/O / LCD segment output 23
P8.1/S24 36 H5 I/O General-purpose digital I/O / LCD segment output 24
P8.0/S25 37 J5 I/O General-purpose digital I/O / LCD segment output 25
P7.7/S26 38 M6 I/O General-purpose digital I/O / LCD segment output 26
P7.6/S27 39 L6 I/O General-purpose digital I/O / LCD segment output 27
P7.5/S28 40 J6 I/O General-purpose digital I/O / LCD segment output 28
P7.4/S29 41 M7 I/O General-purpose digital I/O / LCD segment output 29
P7.3/UCA0CLK/S30 42 H6 I/O General-purpose digital I/O / external clock input − USCI_A0/UART or SPI mode, clock
output − USCI_A0/SPI mode / LCD segment 30
P7.2/UCA0SOMI/S31 43 L7 I/O General-purpose digital I/O / slave out/master in of USCI_A0/SPI mode / LCD segment
output 31
P7.1/UCA0SIMO/S32 44 M8 I/O General-purpose digital I/O / slave in/master out of USCI_A0/SPI mode / LCD segment
output 32
P7.0/UCA0STE/S33 45 L8 I/O General-purpose digital I/O / slave transmit enable—USCI_A0/SPI mode / LCD segment
output 33
P4.7/UCA0RXD/S34 46 J7 I/O General-purpose digital I/O / receive data in − USCI_A0/UART or IrDA mode / LCD
segment output 34
P4.6/UCA0TXD/S35 47 M9 I/O General-purpose digital I/O / transmit data out − USCI_A0/UART or IrDA mode / LCD
segment output 35
P4.5/UCLK1/S36 48 L9 I/O General-purpose digital I/O / external clock input − USART1/UART or SPI mode,
clock output − USART1/SPI MODE / LCD segment output 36
P4.4/SOMI1/S37 49 H7 I/O General-purpose digital I/O / slave out/master in of USART1/SPI mode / LCD segment
output 37
P4.3/SIMO1/S38 50 M10 I/O General-purpose digital I/O / slave in/master out of USART1/SPI mode / LCD segment
output 38
P4.2/STE1/S39 51 M11 I/O General-purpose digital I/O / slave transmit enable—USART1/SPI mode / LCD segment
output 39
COM0 52 L10 O COM0−3 are used for LCD backplanes.
P5.2/COM1 53 L12 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.3/COM2 54 J8 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.4/COM3 55 K12 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.5/R03 56 K11 I/O General-purpose digital I/O / Input port of lowest analog LCD level (V5)
P5.6/LCDREF/R13 57 J12 I/O General-purpose digital I/O / External reference voltage input for regulated LCD voltage
/ Input port of third most positive analog LCD level (V4 or V3)
P5.7/R23 58 J11 I/O General-purpose digital I/O / Input port of second most positive analog LCD level (V2)
LCDCAP/R33 59 H11 I LCD capacitor connection / Input/output port of most positive analog LCD level (V1)
DVCC2 60 H12 Digital supply voltage, positive terminal
DVSS2 61 G12 Digital supply voltage, negative terminal
P4.1/URXD1 62 G11 I/O General-purpose digital I/O / receive data in—USART1/UART mode
P4.0/UTXD1 63 H9 I/O General-purpose digital I/O / transmit data out—USART1/UART mode
P3.7/TB6 64 F12 I/O General-purpose digital I/O / Timer_B7 CCR6. Capture: CCI6A/CCI6B input, compare:
Out6 output
P3.6/TB5 65 F11 I/O General-purpose digital I/O / Timer_B7 CCR5. Capture: CCI5A/CCI5B input, compare:
Out5 output
P3.5/TB4 66 G9 I/O General-purpose digital I/O / Timer_B7 CCR4. Capture: CCI4A/CCI4B input, compare:
Out4 output

MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
8POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME NO.
PZ NO. ZQW I/O DESCRIPTION
P3.4/TB3 67 E12 I/O General-purpose digital I/O / Timer_B7 CCR3. Capture: CCI3A/CCI3B input, compare: Out3
output
P3.3/UCB0CLK 68 E11 I/O General-purpose digital I/O / external clock input—USCI_B0/UART or SPI mode, clock
output—USCI_B0/SPI mode
P3.2/UCB0SOMI/
UCB0SCL 69 F9 I/O General-purpose digital I/O / slave out/master in of USCI_B0/SPI mode /I2C clock—USCI_B0/I2C mode
P3.1/UCB0SIMO/
UCB0SDA 70 D12 I/O General-purpose digital I/O / slave in/master out of USCI_B0/SPI mode, I2C data—USCI_B0/I2C mode
P3.0/UCB0STE 71 D11 I/O General-purpose digital I/O / slave transmit enable—USCI_B0/SPI mode
P2.7/ADC12CLK/
DMAE0 72 E9 I/O General-purpose digital I/O / conversion clock—12-bit ADC / DMA Channel 0 external trigger
P2.6/CAOUT 73 C12 I/O General-purpose digital I/O / Comparator_A output
P2.5/UCA0RXD 74 C11 I/O General-purpose digital I/O / receive data in—USCI_A0/UART or IrDA mode
P2.4/UCA0TXD 75 B12 I/O General-purpose digital I/O / transmit data out—USCI_A0/UART or IrDA mode
P2.3/TB2 76 A11 I/O General-purpose digital I/O / Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2
output
P2.2/TB1 77 E8 I/O General-purpose digital I/O / Timer_B7 CCR1. Capture: CCI1A/CCI1B input, compare: Out1
output
P2.1/TB0 78 D8 I/O General-purpose digital I/O / Timer_B7 CCR0. Capture: CCI0A/CCI0B input, compare: Out0
output
P2.0/TA2 79 A10 I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output
P1.7/CA1 80 B10 I/O General-purpose digital I/O / Comparator_A input
P1.6/CA0 81 A9 I/O General-purpose digital I/O / Comparator_A input
P1.5/TACLK/ACLK 82 B9 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by
1, 2, 4, or 8)
P1.4/TBCLK/SMCLK 83 B8 I/O General-purpose digital I/O / input clock TBCLK—Timer_B7 / submain system clock SMCLK
output
P1.3/TBOUTH/SVSOUT 84 A8 I/O General-purpose digital I/O / switch all PWM digital output ports to high
impedance—Timer_B7 TB0 to TB6 / SVS: output of SVS comparator
P1.2/TA1 85 D7 I/O General-purpose digital I/O / Timer_A, Capture: CCI1A input, compare: Out1 output
P1.1/TA0/MCLK 86 E7 I/O General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive
P1.0/TA0 87 A7 I/O General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL
transmit
XT2OUT 88 B7 O Output terminal of crystal oscillator XT2
XT2IN 89 B6 I Input port for crystal oscillator XT2. Only standard crystals can be connected.
TDO/TDI 90 A6 I/O Test data output port. TDO/TDI data output or programming data input terminal
TDI/TCLK 91 D6 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TMS 92 E6 I Test mode select. TMS is used as an input port for device programming and test.
TCK 93 A5 I Test clock. TCK is the clock input port for device programming and test.
RST/NMI 94 B5 I Reset input or nonmaskable interrupt input port
P6.0/A0/OA0I0 95 A4 I/O General-purpose digital I/O / analog input a0—12-bit ADC / OA0 input multiplexer on
+ terminal and − terminal
P6.1/A1/OA0O 96 D5 I/O General-purpose digital I/O / analog input a1—12-bit ADC / OA0 output
P6.2/A2/OA0I1 97 B4 I/O General-purpose digital I/O / analog input a2—12-bit ADC / OA0 input multiplexer on
+ terminal and − terminal

MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
9
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME NO.
PZ NO. ZQW I/O DESCRIPTION
AVSS 98 A3 Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_A,
port 1
DVSS1 (see Note 1) 99 B3 Digital supply voltage, negative terminal
AVCC 100 A2 Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_A,
port 1; must not power up prior to DVCC1/DVCC2.
NOTE 1: All unassigned ball locations on the ZQW package should be electrically tied to the ground supply. The shortest ground return path to
the device should be established via ball location B3.

General-Purpose Register
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R12
R13
General-Purpose Register
General-Purpose Register
R6
R7
General-Purpose Register
General-Purpose Register
R8
R9
General-Purpose Register
General-Purpose Register
R10
R11
General-Purpose Register
General-Purpose Register
R14
R15
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
10 POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
The MSP430xG461x device family utilizes the
MSP430X CPU and is completely backwards
compatible with the MSP430 CPU. For a complete
description of the MSP430X CPU, see the
MSP430x4xx Family User’s Guide (SLAU056).
instruction set
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the
expanded address range. Each instruction can
operate on word and byte data. Table 1 shows
examples of the three types of instruction formats;
Table 2 shows the address modes.

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Table 1. Instruction Word Formats
Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 −−−> R5
Single operands, destination only e.g., CALL R8 PC −−>(TOS), R8−−> PC
Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register FFMOV Rs,Rd MOV R10,R11 R10 —> R11
Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)—> M(6+R6)
Symbolic (PC relative) F F MOV EDE,TONI M(EDE) —> M(TONI)
Absolute F F MOV & MEM, & TCDAT M(MEM) —> M(TCDAT)
Indirect FMOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) —> M(Tab+R6)
Indirect
autoincrement FMOV @Rn+,Rm MOV @R10+,R11 M(R10) —> R11 R10 + 2—> R10
Immediate FMOV #X,TONI MOV #45,TONI #45 —> M(TONI)
NOTE: S = source D = destination

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operating modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
DActive mode (AM)
− All clocks are active
DLow-power mode 0 (LPM0)
− CPU is disabled
− ACLK and SMCLK remain active. MCLK is disabled
− FLL+ loop control remains active
DLow-power mode 1 (LPM1)
− CPU is disabled
− FLL+ loop control is disabled
− ACLK and SMCLK remain active, MCLK is disabled
DLow-power mode 2 (LPM2)
− CPU is disabled
− MCLK, FLL+ loop control and DCOCLK are disabled
− DCO’s dc-generator remains enabled
− ACLK remains active
DLow-power mode 3 (LPM3)
− CPU is disabled
− MCLK, FLL+ loop control, and DCOCLK are disabled
− DCO’s dc-generator is disabled
− ACLK remains active
DLow-power mode 4 (LPM4)
− CPU is disabled
− ACLK is disabled
− MCLK, FLL+ loop control, and DCOCLK are disabled
− DCO’s dc-generator is disabled
− Crystal oscillator is stopped

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interrupt vector addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FFC0h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 3. Interrupt Sources, Flags, and Vectors of MSP430xG461x Configurations
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD
ADDRESS PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
WDTIFG
KEYV
(see Note 1 and 5)
Reset 0FFFEh 31, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1, 2, and 5)
(Non)maskable
(Non)maskable
(Non)maskable 0FFFCh 30
Timer_B7 TBCCR0 CCIFG0 (see Note 2) Maskable 0FFFAh 29
Timer_B7 TBCCR1 CCIFG1 ... TBCCR6 CCIFG6,
TBIFG (see Notes 1 and 2) Maskable 0FFF8h 28
Comparator_A CAIFG Maskable 0FFF6h 27
Watchdog Timer+ WDTIFG Maskable 0FFF4h 26
USCI_A0/USCI_B0 Receive UCA0RXIFG, UCB0RXIFG (see Note 1) Maskable 0FFF2h 25
USCI_A0/USCI_B0 Transmit UCA0TXIFG, UCB0TXIFG (see Note 1) Maskable 0FFF0h 24
ADC12 ADC12IFG (see Notes 1 and 2) Maskable 0FFEEh 23
Timer_A3 TACCR0 CCIFG0 (see Note 2) Maskable 0FFECh 22
Timer_A3 TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (see Notes 1 and 2) Maskable 0FFEAh 21
I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0FFE8h 20
USART1 Receive URXIFG1 Maskable 0FFE6h 19
USART1 Transmit UTXIFG1 Maskable 0FFE4h 18
I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0FFE2h 17
Basic Timer1/RTC BTIFG Maskable 0FFE0h 16
DMA DMA0IFG, DMA1IFG, DMA2IFG
(see Notes 1 and 2) Maskable 0FFDEh 15
DAC12 DAC12.0IFG, DAC12.1IFG (see Notes 1 and 2) Maskable 0FFDCh 14
0FFDAh 13
Reserved Reserved (see Note 4) ... ...
Reserved
Reserved
(see
Note
4)
0FFC0h 0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh).
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
4. The interrupt vectors at addresses 0FFDAh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
5. Access and key violations, KEYV and ACCVIFG, only applicable to F devices.

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special function registers (SFRs)
The MSP430 SFRs are located in the lowest address space and are organized as byte mode registers. SFRs
should be accessed with byte instructions.
interrupt enable 1 and 2
7654 0
OFIE WDTIE
321
rw–0 rw–0 rw–0
Address
0h ACCVIE NMIIE
rw–0
WDTIE Watchdog-timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as a general-purpose timer.
OFIE Oscillator-fault-interrupt enable
NMIIE Nonmaskable-interrupt enable
ACCVIE Flash access violation interrupt enable
7654 0321
Address
01h
rw–0
BTIE UTXIE1 URXIE1
rw–0 rw–0
UCA0TXIE UCA0RXIE
rw–0 rw–0
UCB0TXIE UCB0RXIE
rw–0 rw–0
UCA0RXIE USCI_A0 receive-interrupt enable
UCA0TXIE USCI_A0 transmit-interrupt enable
UCB0RXIE USCI_B0 receive-interrupt enable
UCB0TXIE USCI_B0 transmit-interrupt enable
URXIE1 USART1 UART and SPI receive-interrupt enable
UTXIE1 USART1 UART and SPI transmit-interrupt enable
BTIE Basic timer interrupt enable

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interrupt flag register 1 and 2
7654 0
OFIFG WDTIFG
321
rw–0 rw–1 rw–(0)
Address
02h NMIIFG
WDTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode
OFIFG: Flag set on oscillator fault
NMIIFG: Set via RST/NMI pin
7654 0321
Address
03h BTIFG
rw–0
UTXIFG1 URXIFG1
rw–1 rw–0
UCA0TXIFG UCA0RXIFG
rw–0 rw–0
UCB0TXIFG UCB0RXIFG
rw–0 rw–0
UCA0RXIFG USCI_A0 receive-interrupt flag
UCA0TXIFG USCI_A0 transmit-interrupt flag
UCB0RXIFG USCI_B0 receive-interrupt flag
UCB0TXIFG USCI_B0 transmit-interrupt flag
URXIFG0: USART1: UART and SPI receive flag
UTXIFG0: USART1: UART and SPI transmit flag
BTIFG: Basic timer flag
module enable registers 1 and 2
7654 0321
Address
04h
7654 0
UTXE1 321
rw–0 rw–0
Address
05h URXE1
USPIE1
URXE1: USART1: UART mode receive enable
UTXE1: USART1: UART mode transmit enable
USPIE1: USART1: SPI mode transmit and receive enable
Legend rw:
rw-0,1: Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
rw-(0,1): SFR bit is not present in device

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memory organization
MSP430FG4616 MSP430FG4617 MSP430FG4618 MSP430FG4619
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
92KB
0FFFFh − 0FFC0h
018FFFh − 002100h
92KB
0FFFFh − 0FFC0h
019FFFh − 003100h
116KB
0FFFFh − 0FFC0h
01FFFFh − 003100h
120KB
0FFFFh − 0FFC0h
01FFFFh − 002100h
RAM (Total) Size 4KB
020FFh − 01100h 8KB 030FFh − 01100h 8KB 030FFh − 01100h 4KB 020FFh − 01100h
Extended Size 2KB
020FFh − 01900h 6KB 030FFh − 01900h 6KB 030FFh − 01900h 2KB 020FFh − 01900h
Mirrored Size 2KB
018FFh − 01100h 2KB 018FFh − 01100h 2KB 018FFh − 01100h 2KB 018FFh − 01100h
Information memory Size
Flash 256 Byte 010FFh − 01000h 256 Byte 010FFh − 01000h 256 Byte 010FFh − 01000h 256 Byte 010FFh − 01000h
Boot memory Size
ROM 1KB 0FFFh − 0C00h 1KB 0FFFh − 0C00h 1KB 0FFFh − 0C00h 1KB 0FFFh − 0C00h
RAM
(mirrored at
018FFh − 01100h)
Size 2KB
09FFh − 0200h 2KB 09FFh − 0200h 2KB 09FFh − 0200h 2KB 09FFh − 0200h
Peripherals 16 bit
8 bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
MSP430CG4616 MSP430CG4617 MSP430CG4618 MSP430CG4619
Memory
Main: interrupt vector
Main: code memory
Size
ROM
ROM
92KB
0FFFFh − 0FFC0h
018FFFh − 002100h
92KB
0FFFFh − 0FFC0h
019FFFh − 003100h
116KB
0FFFFh − 0FFC0h
01FFFFh − 003100h
120KB
0FFFFh − 0FFC0h
01FFFFh − 002100h
RAM (Total) Size 4KB
020FFh − 01100h 8KB 030FFh − 01100h 8KB 030FFh − 01100h 4KB 020FFh − 01100h
Extended Size 2KB
020FFh − 01900h 6KB 030FFh − 01900h 6KB 030FFh − 01900h 2KB 020FFh − 01900h
Mirrored Size 2KB
018FFh − 01100h 2KB 018FFh − 01100h 2KB 018FFh − 01100h 2KB 018FFh − 01100h
Information memory Size
ROM 256 Byte 010FFh − 01000h 256 Byte 010FFh − 01000h 256 Byte 010FFh − 01000h 256 Byte 010FFh − 01000h
Boot memory
(Optional on CG) Size ROM 1KB 0FFFh − 0C00h 1KB 0FFFh − 0C00h 1KB 0FFFh − 0C00h 1KB 0FFFh − 0C00h
RAM
(mirrored at
018FFh − 01100h)
Size 2KB
09FFh − 0200h 2KB 09FFh − 0200h 2KB 09FFh − 0200h 2KB 09FFh − 0200h
Peripherals 16 bit
8 bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h

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bootstrap loader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access
to the MSP430 memory via the BSL is protected by user-defined password. A bootstrap loader security key is
provided at address 0FFBEh to disable the BSL completely or to disable the erasure of the flash if an invalid
password is supplied. The BSL is optional for ROM-based devices. For complete description of the features of
the BSL and its implementation, see the application report Features of the MSP430 Bootstrap Loader, literature
number SLAA089.
BSLKEY DESCRIPTION
00000h Erasure of flash disabled if an invalid password is supplied
0AA55h BSL disabled
any other value BSL enabled
BSL FUNCTION PZ/ZQW PACKAGE PINS
Data Transmit 87/A7 − P1.0
Data Receive 86/E7 − P1.1
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
DFlash memory has n segments of main memory and two segments of information memory (A and B) of
128 bytes each. Each segment in main memory is 512 bytes in size.
DSegments 0 to n may be erased in one step, or each segment may be individually erased.
DSegments A and B can be erased individually, or as a group with segments 0 to n.
Segments A and B are also called information memory.
DNew devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.

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peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide (SLAU056).
DMA controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to
or from a peripheral.
oscillator and system clock
The clock system in the MSP430xG461x family of devices is supported by the FLL+ module, which includes
support for a 32768-Hz watch crystal oscillator, an internal digitally controlled oscillator (DCO), and a
high-frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low
system cost and low power consumption. The FLL+ features digital frequency locked loop (FLL) hardware that,
in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch
crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The
FLL+ module provides the following clock signals:
DAuxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal
DMain clock (MCLK), the system clock used by the CPU
DSub-Main clock (SMCLK), the subsystem clock used by the peripheral modules
DACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on
and power-off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must insure the default FLL+ settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are ten 8-bit I/O ports implemented—ports P1 through P10:
DAll individual I/O bits are independently programmable.
DAny combination of input, output, and interrupt conditions is possible.
DEdge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
DRead/write access to port-control registers is supported by all instructions.
DPorts P7/P8 and P9/P10 can be accessed word-wise as ports PA and PB respectively.
Basic Timer1 and Real-Time Clock
The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. Basic Timer1 is extended to provide an integrated real-time clock
(RTC). An internal calendar compensates for months with less than 31 days and includes leap-year correction.

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LCD_A drive with regulated charge pump
The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump.
Furthermore it is possible to control the level of the LCD voltage and, thus, contrast by software.
watchdog timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
universal serial communication interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols like UART,
enhanced UART with automatic baudrate detection, and IrDA.
The USCI_A0 module provides support for SPI (3 or 4 pin), UART, enhanced UART and IrDA.
The USCI_B0 module provides support for SPI (3 or 4 pin) and I2C.
USART1
The hardware universal synchronous/asynchronous receive transmit (USART) peripheral module is used for
serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART
communication protocols, using double-buffered transmit and receive channels.
hardware multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16 16,
16 8, 8 16, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplication,
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.

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Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number Device Input Module Input Module Module Output Output Pin Number
PZ/ZQW
Device
Input
Signal
Module
Input
Name
Module
Block
Module
Output
Signal PZ/ZQW
82/B9 - P1.5 TACLK TACLK
ACLK ACLK
Timer
NA
SMCLK SMCLK Timer NA
82/B9 - P1.5 TACLK INCLK
87/A7 - P1.0 TA0 CCI0A 87/A7 - P1.0
86/E7 - P1.1 TA0 CCI0B
CCR0
TA0
DVSS GND CCR0 TA0
DVCC VCC
85/D7 - P1.2 TA1 CCI1A 85/D7 - P1.2
CAOUT (internal) CCI1B
CCR1
TA1
ADC12 (internal)
DVSS GND CCR1 TA1
DVCC VCC
79/A10 - P2.0 TA2 CCI2A 79/A10 - P2.0
ACLK (internal) CCI2B
CCR2
TA2
DVSS GND CCR2 TA2
DVCC VCC