Texas Instruments TPS6594-Q1 Series User manual

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User's Guide for Powering DRA829V and TDA4VM with the TPS6594-Q1
PMICs
User's Guide
SLVUBR0–December 2019
User's Guide for Powering DRA829V and TDA4VM with the
TPS6594-Q1 PMICs
This User’s Guide can be used as a guide for integrating the TPS6594-Q1 power management integrated
circuit (PMIC) into a system powering the DRA829V or TDA4VM device. This document provides the
default non-volatile memory (NVM) settings, state transitions, and power sequencing for the system
solution.
Contents
1 Introduction ................................................................................................................... 3
2 Device Versions.............................................................................................................. 3
3 Processor Connection....................................................................................................... 3
4 Supporting Functional Safety Systems ................................................................................... 7
5 Static NVM Settings ......................................................................................................... 9
6 Pre-Configurable Finite State Machine (PFSM) Settings ............................................................. 25
7 Additional Resources ...................................................................................................... 42
List of Figures
1 Power Connections with TPS659413-Q1 and TPS659411-Q1........................................................ 4
2 Digital Connections with TPS659413-Q1 and TPS659411-Q1........................................................ 6
3 Dual TPS6594-Q1 PFSM States and Transitions...................................................................... 25
4 TO_SAFE_SEVERE Sequence.......................................................................................... 28
5 TO_SAFE_MODERATE and TO_STANDBY Sequence.............................................................. 30
6 WARM_RESET Sequence................................................................................................ 32
7 MCU_WARM_RESET Sequence........................................................................................ 34
8 TO_MCU Sequence with I2C_7=0....................................................................................... 36
9 TO_MCU Sequence with I2C_7=1....................................................................................... 37
10 TO_ACTIVE Sequence.................................................................................................... 39
11 TO_S2R Sequence ........................................................................................................ 41
List of Tables
1 Dual TPS6594-Q1 NVM Settings and Orderable Part Numbers...................................................... 3
2 Power Connections by System Feature .................................................................................. 5
3 Digital Connections by System Feature .................................................................................. 7
4 Application Use Case Settings............................................................................................. 9
5 Device Identification NVM Settings ...................................................................................... 10
6 BUCK NVM Settings....................................................................................................... 10
7 LDO NVM Settings......................................................................................................... 12
8 VCCA NVM Settings....................................................................................................... 13
9 GPIO NVM Settings........................................................................................................ 14
10 FSM NVM Settings......................................................................................................... 16
11 Interrupt NVM Settings .................................................................................................... 17
12 POWERGOOD NVM Settings............................................................................................ 21
13 Miscellaneous NVM Settings ............................................................................................. 22

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14 Interface NVM Settings.................................................................................................... 23
15 Multi-Device NVM Settings ............................................................................................... 24
16 Watchdog NVM Settings .................................................................................................. 24
17 State Transition Triggers.................................................................................................. 26
18 Additional Documents ..................................................................................................... 42
Trademarks
All trademarks are the property of their respective owners.

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1 Introduction
This user’s guide can be used as a guide to understand the power distribution network (PDN) between the
two TPS6594-Q1 devices and the DRA829V or TDA4VM processor. This guide describes the platform
power resource connections, digital control connections, and the PMIC sequencing settings to support the
different state transitions of the processor. The default NVM contents are also included in this guide. This
user's guide does not provide information about the electrical characteristics, external components,
package, or the functionality of the PMIC or processor devices. For such information and the full register
map, refer to the datasheet for each device. In the event of any inconsistency between the official
specification and any user's guide, application report, or other referenced material, the data sheet
specification will be the definitive source.
2 Device Versions
There are different versions of the TPS6594-Q1 device available with unique NVM settings to support
different use cases for the processor. The unique NVM settings for each PMIC device are optimized per
PDN design to support different processors, processing loads, SDRAM types, system functional safety
levels, and end product features - such as low power modes, processor interface levels, SD Card, and so
forth. The NVM settings can be distinguished using the NVM_ID register. In this user guide, each PMIC
device is distinguished by the part number, NVM_ID, and NVM_REV values listed in Table 1.
(1) TI recommends having 15% margin between the maximum expected load current and the maximum current allowed per each
PMIC output rail.
Table 1. Dual TPS6594-Q1 NVM Settings and Orderable Part Numbers
PDN USE CASE ORDERABLE PART NUMBER DEVICE MODE NVM_ID NVM_REV
1
• Up to 12 A(1) on the CORE rail
• Up to 6 A(1) on the CPU rails
• Up to 3.4 A(1) on the SDRAM, with support for
LPDDR4
• Supports Functional Safety up to ASIL-D level
• Supports low power modes, including MCU-
only and suspend-to-RAM states
• Supports I/O level of 3.3 V or 1.8 V
• Supports use of SD card
PTPS659413F0RWERQ1 Master 0xF0 0x7
PTPS659411F0RWERQ1 Slave 0xF0 0x7
3 Processor Connection
This section details how the dual TPS6594-Q1 power resources and GPIO signals are connected to the
SoC processor and other peripheral components in order to support the PDN use case.
Figure 1 shows the detailed power mapping between the processor and the TPS659413-Q1 and
TPS659411-Q1 PMICs. In this configuration, both TPS6594-Q1 devices use a 3.3 V input voltage. For
Functional Safety applications, there is a protection FET before VCCA that connects to the OVPGDRV pin
of the master PMIC, allowing voltage monitoring of the input supply to the PMICs.
The VCCA voltage must be the first voltage applied to the PMIC devices, so VIO_IN of the PMICs must be
supplied after VCCA. In this configuration, VIO_IN is supplied by the load switch that also supplies the
VDDSHVx_MCU voltage domain of the processor to allow the digital components of the PMIC devices
(such as GPIOs) to remain supplied in MCU-only mode. Additionally, by controlling VIO_IN of both PMICs
through this load switch, the system can also reduce power consumption in suspend-to-RAM mode, since
the load switch is disabled.
For SD card dual-voltage I/O support (3.3 V and 1.8 V), LDO1 of the TPS659411-Q1 device can be used,
with a control signal from the processor, to switch the LDO1 voltage between 3.3 V and 1.8 V. This allows
control of the LDO1 voltage without the need for the MCU of the processor to establish I2C
communication with the PMICs during boot from SD card operations.

TPS659413-Q1
BUCK1 + BUCK2
(7A max)
BUCK3
(3.5A max)
BUCK4
(4A max)
BUCK5
(2A max)
LDO1
(500mA max)
LDO2
(500mA max)
LDO3
(500mA max)
LDO4
(300mA max)
TPS659411-Q1
BUCK1 + BUCK2 +
BUCK3 + BUCK4
(14A max)
LDO1
(500mA max)
LDO2
(500mA max)
LDO3
(500mA max)
LDO4
(300mA max)
BUCK5
(2A max)
MASTER PMICSLAVE PMIC
Processor Supplies
MAIN PROCESSOR
VDD_CORE
VDDAR_CPU
VDDAR_CORE
VDDS_DDR_x
1.1V
0.8V
0.85V
MAIN ANALOG
VDDA_1P8_PHYs
VDDA_0P8_PHYs
VDDA_0P8_PLLs/DLLs
VDDA_1P8_PLLs
0.8V
VDDA_3P3_USB
MAIN DIGITAL
VDDSHV5
VDDSHVx
VDDS_MMC0
3.3V
1.8V
1.8V
MCU SAFETY ISLAND
VDD_MCU
VDDAR_MCU
VDDA_x
VDDSHVx_MCU (1.8V)
System
1.8V
3.3V
1.8V
TPS22965-Q1
(load switch, 4A max)
3.3V
VPP_x (EFUSE)
3.3V / 1.8V
0.85V
1.8V
VDDSHVx_MCU (3.3V)
1.8V
TPS22965-Q1
(load switch, 4A max)
3.3V
0.8V (AVS)
1.8V
LPDDR4
1.8V
1.1V
3.3V
VDD_CPU (AVS)
VCCA
OVPGDRV
VCCA
OVPGDRV
VIO_IN
VIO_IN
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Figure 1. Power Connections with TPS659413-Q1 and TPS659411-Q1

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The power connections shown in Figure 1 allow the support for features including MCU-only mode,
suspend-to-RAM mode, SD-card integration, and USB interface integration. Please use Table 2 as a guide
to understand which power resources are required to support different system features. If the system
feature listed is not required, the power connection can be removed and the SoC voltage domains will
need to be grouped into alternative power rails.
Table 2. Power Connections by System Feature
Device PMIC Resource System Features
Active SoC MCU-only Mode Suspend-to-
RAM Mode SD Card USB Interface
TPS659413-Q1
BUCK12 Required
BUCK3 Required Required
BUCK4 Required Required
BUCK5 Required
LDO1 Required Required
LDO2 Required Required
LDO3 Required
LDO4 Required Required
TPS659411-Q1
BUCK1234 Required
BUCK5 Required
LDO1 Required
LDO2 Required
LDO3 Required
LDO4 Required
TPS22965-Q1
(MCU I/O) Load Switch Required Required
TPS22965-Q1
(MAIN I/O) Load Switch Required
Figure 2 shows the digital control signal mapping between the processor and the TPS659413-Q1 and
TPS659411-Q1 PMICs. For the two TPS6594-Q1 devices to work together, master PMIC and slave PMIC
must establish an SPMI communication channel in order to synchronize both internal Pre-Configurable
State Machines (PFSM) so that they operate as one PFSM across all power and digital resources. The
GPIO_5 and GPIO_6 pins on each PMIC are assigned for this functionality. In addition, the master PMIC's
LDOVINT pin must be connected to the slave PMIC's ENABLE input to correctly initiate the PFSM.
Other digital connections from the TPS6594-Q1 devices to the processor allow support for error
monitoring, processor reset, processor wake up, and system low-power modes. Specific GPIO pins have
been assigned to key signals in order to ensure proper operation during low power modes when only a
few GPIO pins will remain operational.

TPS659413-Q1
ENABLE
INTn
nRSTOUT
GPIO_1 (SCL_I2C2)
TPS659411-Q1
MASTER PMIC
Processor
SoC MAIN CONTROLS
MMC1 IO
DDR_RET
RESETSTATz
SAFETY MCU CONTROLS
Safety MCU GPIO
WKUP_I2C0_SCL/SDA
MCU_PORz
Board
TPS22965-Q1
MCU_SAFETY_ERRORn
TPS22965-Q1
Reset to Board
Warm Reset
ON REQUEST
SCL_I2C1
SDA_I2C1
GPIO_2 (SDA_I2C2)
GPIO_3 (GPO)
GPIO_4 (GPI)
GPIO_5 (SCLK_SPMI)
GPIO_6 (SDATA_SPMI)
GPIO_7 (nERR_MCU)
GPIO_8 (DISABLE_WDOG)
GPIO_9 (nSLEEP)
GPIO_10 (WKUP1)
GPIO_11 (nRSTOUT_SoC)
ENABLE
INTn
nRSTOUT
GPIO_1 (GPI)
SLAVE PMIC
SCL_I2C1
SDA_I2C1
GPIO_2 (GPI)
GPIO_3 (GPO)
GPIO_4 (GPO)
GPIO_5 (SCLK_SPMI)
GPIO_6 (SDATA_SPMI)
GPIO_7 (GPO)
GPIO_8 (GPO)
GPIO_9 (GPO)
GPIO_10 (GPO)
GPIO_11 (GPO)
LDOVINT LDOVINT
GND
MCU_I2C0_SCL/SDA
ENABLE MCU I/O
PMIC_POWER_EN1
PORz
ENABLE MAIN I/O
ENABLE 0.6V LPDDR4x (optional)
PMIC VOLTAGE DOMAINS
VRTC t1.8V
VINT t1.8V
VIO t1.8V or 3.3V
PORz_OUT
CONTROL SD VOLTAGE
Disable Watchdog
CAN Wakeup
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Figure 2. Digital Connections with TPS659413-Q1 and TPS659411-Q1

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The digital connections shown in Figure 2 allow system features including MCU-only mode, suspend-to-
RAM mode, functional safety up to ASIL-D, compliant dual voltage SD card operation, and LPDDR4x
integration. Please use Table 3 as a guide to understand GPIO assignments required for these features. If
the feature listed is not required, the digital connection can be removed. For details on how functional
safety related connections help achieve functional safety system-level goals, see Section 4.
Table 3. Digital Connections by System Feature
Device PMIC Digital
Signal
System Features
Active SoC Functional Safety MCU-only
Mode Suspend-to- RAM Mode SD Card LPDDR4x
TPS659413-
Q1
nPWRON/E
NABLE Required
INT Required
nRSTOUT Required
SCL_I2C1 Required
SDA_I2C1 Required
GPIO_1 Required
GPIO_2 Required
GPIO_3 Required
GPIO_4 Required
GPIO_5 Required
GPIO_6 Required
GPIO_7 Required
GPIO_8
GPIO_9
GPIO_10
GPIO_11 Required
TPS659411-
Q1
nPWRON/E
NABLE Required
INT Required
nRSTOUT
SCL_I2C1 Required
SDA_I2C1 Required
GPIO_1
GPIO_2 Required
GPIO_3 Required
GPIO_4 Required
GPIO_5 Required
GPIO_6 Required
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11 Required Required
4 Supporting Functional Safety Systems
By utilizing the dual TPS6594-Q1 solution to power the DRA829V or TDA4VM processor, the system can
utilize the following PMIC functional safety features:
• Independent Power Control of MCU and Main Rails
• Independent Monitoring and Reset for MCU and Main Rails
• Input Supply Monitoring

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• Output Voltage and Current Monitoring
• Question/Answer Watchdog
• Fault Reporting Interrupts
• Enable Drive Pin that provides an independent path to disable system actuators
• Error Pin Monitoring
• Internal Diagnostics including voltage monitoring, temperature monitoring, and Built-In Self-Test
Please refer to the Safety Manual of the TPS6594-Q1 device for full descriptions and analysis of the PMIC
functional safety features. These functional safety features can assist in achieving up to ASIL-D rating for
a system. Additionally, these features help in achieving the functional safety assumptions utilized by the
processor to achieve up to ASIL-D rating. See the DRA829/TDA4VM Safety Manual for JacintoTM 7
Processors for a complete list of functional safety system assumptions.
4.1 Achieving ASIL-B System Requirements
To achieve a functional safety level of ASIL-B for the dual TPS6594-Q1 and SoC system, the following
features are available within the PDN:
• PMIC over voltage and under voltage monitoring on the output power rails
• PMIC over-voltage monitoring and protection on the input to the PMIC (VCCA)
• Watchdog
• MCU error monitoring
• MCU reset
• I2C communication
• Error indicator for driving external circuitry (Optional)
There is the option for using an external power FET to shut off the PMICs when an over-voltage event is
detected on the input to protect the system from being damaged as shown in Figure 1. Note that any
power rail connected after the FET can be protected from an over voltage event. Any power connected
upstream from the FET is not protected from over voltage events. In Figure 1 the load switches to power
the MCU I/O and the Main I/O are connected after the FET to protect the their pins from observing greater
than 6 V in the event of a short of the previous power stage.
The PMIC internal over voltage and under voltage monitoring and their respective monitoring threshold
levels are enabled by default and can be updated through I2C after startup. PMIC power rails connected
directly to the processor are monitored by default, however, the rails supplied through the load switches
are not monitored. To monitor the load switch voltage that supplies the MCU I/O of the processor, it is
recommended to use the processor's POK monitor built into the VDDSHV0_MCU voltage domain. For
monitoring the load switch voltage that supplies the Main I/O, an unused feedback pin of the TPS659411-
Q1 (FB_B3 or FB_B4) can be configured through I2C and connected to the output of the load switch to
enable monitoring.
The PMIC's Internal Q&A Watchdog is enabled by default on the TPS659413-Q1 device. Once the device
is in ACTIVE state, the trigger or Q&A watchdog settings can be configured through the secondary I2C in
the device. The steps for configuring the watchdog settings can be found in the TPS6594-Q1 datasheet.
GPIO_7 of the TPS659413-Q1 PMIC is configured as the MCU error signal monitoring, but will need to be
enabled though the ESM_MCU_EN register bit. MCU reset is supported through the connection between
the master PMIC nRSTOUT pin and the MCU_PORz of the processor. Lastly, there are 2 I2C ports
between the TPS659413-Q1 and the processor which allows the watchdog monitoring to be on an
independent communication channel.
There is an option to use EN_DRV of the TPS659413-Q1 PMIC to indicate an error has been detected
and the system is entering SAFE state. This signal can be utilized if the system has some additional
external circuitry that needs to be driven by an error event. In this PDN, the EN_DRV is not utilized, but
available if needed.
4.2 Achieving up to ASIL-D System Requirements
For ASIL-C or ASIL-D systems, there are additional features to the ones described in Section 4.1 that can
be utilized. These features include:

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• PMIC current monitoring on all output power rails
• Isolation of the MCU and Main power domains of the processor
• SoC error monitoring
• SoC reset
The current monitoring is enabled by default for all BUCKs and LDOs for the TPS659413-Q1 and
TPS659411-Q1 devices. Additionally, Figure 1 shows that the MCU domain of the processor is powered
by different power resources of the PMICs than the main power domain of the processor. SoC error signal
monitoring can be utilized if GPIO_3 of TPS659411-Q1 is available to be reconfigured as nERR_SoC.
This feature would need to be enabled through I2C using the ESM_SOC_EN register bit. The SoC reset
functionality is supported through the connection of GPIO_11 on TPS659413-Q1, configured as
nRSTOUT_SoC, to the PORz pin of the processor.
5 Static NVM Settings
The TPS6594x-Q1 devices consist of fixed registers and configurable registers that are loaded from NVM.
For all NVM registers, the initial NVM settings that load into the registers are provided in this section. Note
that these initial NVM settings can be changed during state transitions, such as moving from STANDBY to
ACTIVE mode. The full register map, including default values of fixed registers, is located in the
TPS6594x-Q1 datasheet.
5.1 Application-Based Configuration Settings
In the TPS6594-Q1 datasheet, there are 7 application-based configurations for each BUCK to operate
within. The following list includes the different configurations available:
• 2.2 MHz Single Phase for DDR Termination
• 4.4 MHz Multi-phase Configuration
• 4.4 MHz Single Phase Low Output Voltage
• 4.4 MHz Single Phase High Output Voltage
• 2.2 MHz Multi-phase with Full Range VIN
• 2.2 MHz Single Phase with 5.0 V VIN
• 2.2 MHz Single Phase with Full Range VIN
The seven configurations also have optimal output inductance values that optimize the performance of
each buck under these various conditions. Table 4 shows the default configurations for the BUCKs. These
settings cannot be changed after device startup.
Table 4. Application Use Case Settings
Device BUCK Rail Default Application Use Case Recommended Inductor Value
BUCK1 2.2 MHz Multi-phase with Full Range VIN 470 nH
BUCK2 470 nH
BUCK3 2.2 MHz Multi-phase with Full Range VIN 470 nH
BUCK4 2.2 MHz Multi-phase with Full Range VIN 470 nH
BUCK5 2.2 MHz Multi-phase with Full Range VIN 470 nH
BUCK1
2.2 MHz Multi-phase with Full Range VIN
470 nH
BUCK2 470 nH
BUCK3 470 nH
BUCK4 470 nH
BUCK5 2.2 MHz Multi-phase with Full Range VIN 470 nH
5.2 Device Identification Settings
These settings are used to distinguish which device is detected in a system. These settings cannot be
changed after device startup.

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Table 5. Device Identification NVM Settings
Register Name Field Name PTPS659413F0 PTPS659411F0
Value Description Value Description
DEV_REV SILICON_VERSION 000b 000b
DEVICE_ID 001b 001b
NVM_CODE_1 NVM_ID 11110000b 0xF0 11110000b 0xF0
NVM_CODE_2 NVM_REV 000111b 000111b
PHASE_CONFIG MP_CONFIG 010b 2+1+1+1 000b 4+1
5.3 BUCK Settings
These settings detail the default voltages, configurations, and monitoring of the BUCK rails. All these
settings can be changed though I2C after startup.
(1) Note that this NVM default value can change when the device transitions to ACTIVE mode.
Table 6. BUCK NVM Settings
Register Name Field Name PTPS659413F0 PTPS659411F0
Value Description Value Description
BUCK1_CTRL BUCK1_EN(1) 0b BUCK regulator is
disabled 0b BUCK regulator is disabled
BUCK1_FPWM 1b Forced to PWM
operation. 1b Forced to PWM operation.
BUCK1_FPWM_MP 0b Automatic phase
adding and shedding. 0b Automatic phase adding and shedding.
BUCK1_VMON_EN 0b OV and UV
comparators are
disabled
0b OV and UV
comparators are
disabled
BUCK1_VSEL 0b BUCK1_VOUT_1 0b BUCK1_VOUT_1
BUCK1_PLDN 1b Enabled 1b Enabled
BUCK1_RV_SEL 1b Enabled 1b Enabled
BUCK1_CONF BUCK1_SLEW_RATE 100b 2.5 mV/µs 100b 2.5 mV/µs
BUCK1_ILIM 101b 5.5 A 101b 5.5 A
BUCK2_CTRL BUCK2_EN(1) 0b BUCK regulator is
disabled 0b BUCK regulator is disabled
BUCK2_FPWM 1b Forced to PWM
operation. 1b Forced to PWM operation.
BUCK2_VMON_EN 0b OV and UV
comparators are
disabled
0b OV and UV
comparators are
disabled
BUCK2_VSEL 0b BUCK2_VOUT_1 0b BUCK2_VOUT_1
BUCK2_PLDN 1b Enabled 1b Enabled
BUCK2_RV_SEL 1b Enabled 1b Enabled
BUCK2_CONF BUCK2_SLEW_RATE 111b 0.31 mV/µs 111b 0.31 mV/µs
BUCK2_ILIM 101b 5.5 A 101b 5.5 A

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Table 6. BUCK NVM Settings (continued)
Register Name Field Name PTPS659413F0 PTPS659411F0
Value Description Value Description
BUCK3_CTRL BUCK3_EN(1) 0b BUCK regulator is
disabled 0b BUCK regulator is disabled
BUCK3_FPWM 1b Forced to PWM
operation. 1b Forced to PWM operation.
BUCK3_FPWM_MP 0b Automatic phase
adding and shedding. 0b Automatic phase adding and shedding.
BUCK3_VMON_EN 0b OV and UV
comparators are
disabled
0b OV and UV
comparators are
disabled
BUCK3_VSEL 0b BUCK3_VOUT_1 0b BUCK3_VOUT_1
BUCK3_PLDN 1b Pull-down resistor
enabled 1b Pull-down resistor enabled
BUCK3_RV_SEL 1b Enabled 1b Enabled
BUCK3_CONF BUCK3_SLEW_RATE 100b 2.5 mV/µs 111b 0.31 mV/µs
BUCK3_ILIM 101b 5.5 A 101b 5.5 A
BUCK4_CTRL BUCK4_EN(1) 0b BUCK regulator is
disabled 0b BUCK regulator is disabled
BUCK4_FPWM 1b Forced to PWM
operation. 1b Forced to PWM operation.
BUCK4_VMON_EN 0b OV and UV
comparators are
disabled
0b OV and UV
comparators are
disabled
BUCK4_VSEL 0b BUCK4_VOUT_1 0b BUCK4_VOUT_1
BUCK4_PLDN 1b Pull-down resistor
enabled 1b Pull-down resistor enabled
BUCK4_RV_SEL 1b Enabled 1b Enabled
BUCK4_CONF BUCK4_SLEW_RATE 100b 2.5 mV/µs 111b 0.31 mV/µs
BUCK4_ILIM 101b 5.5 A 101b 5.5 A
BUCK5_CTRL BUCK5_EN(1) 0b BUCK regulator is
disabled 0b BUCK regulator is disabled
BUCK5_FPWM 1b Forced to PWM
operation. 1b Forced to PWM operation.
BUCK5_VMON_EN 0b OV and UV
comparators are
disabled
0b OV and UV
comparators are
disabled
BUCK5_VSEL 0b BUCK5_VOUT_1 0b BUCK5_VOUT_1
BUCK5_PLDN 1b Pull-down resistor
enabled 1b Pull-down resistor enabled
BUCK5_RV_SEL 1b Enabled 1b Enabled
BUCK5_CONF BUCK5_SLEW_RATE 011b 5.0 mV/µs 100b 2.5 mV/µs
BUCK5_ILIM 011b 3.5 A 011b 3.5 A
BUCK1_VOUT_1 BUCK1_VSET1 00110111b 0.8 V 00110111b 0.8 V
BUCK1_VOUT_2 BUCK1_VSET2 00000000b 0.3 V 00000000b 0.3 V
BUCK2_VOUT_1 BUCK2_VSET1 00110111b 0.8 V 00110111b 0.8 V
BUCK2_VOUT_2 BUCK2_VSET2 00000000b 0.3 V 00000000b 0.3 V
BUCK3_VOUT_1 BUCK3_VSET1 01000001b 0.85 V 00110111b 0.8 V
BUCK3_VOUT_2 BUCK3_VSET2 00000000b 0.3 V 00000000b 0.3 V
BUCK4_VOUT_1 BUCK4_VSET1 01110011b 1.1 V 00110111b 0.8 V
BUCK4_VOUT_2 BUCK4_VSET2 00000000b 0.3 V 00000000b 0.3 V
BUCK5_VOUT_1 BUCK5_VSET1 10110010b 1.8 V 01000001b 0.85 V
BUCK5_VOUT_2 BUCK5_VSET2 00000000b 0.3 V 00000000b 0.3 V

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Table 6. BUCK NVM Settings (continued)
Register Name Field Name PTPS659413F0 PTPS659411F0
Value Description Value Description
BUCK1_PG_WINDOW BUCK1_OV_THR 010b +4% / +40 mV 010b +4% / +40 mV
BUCK1_UV_THR 010b -4% / -40 mV 010b -4% / -40 mV
BUCK2_PG_WINDOW BUCK2_OV_THR 010b +4% / +40 mV 010b +4% / +40 mV
BUCK2_UV_THR 010b -4% / -40 mV 010b -4% / -40 mV
BUCK3_PG_WINDOW BUCK3_OV_THR 010b +4% / +40 mV 010b +4% / +40 mV
BUCK3_UV_THR 010b -4% / -40 mV 010b -4% / -40 mV
BUCK4_PG_WINDOW BUCK4_OV_THR 010b +4% / +40 mV 010b +4% / +40 mV
BUCK4_UV_THR 010b -4% / -40 mV 010b -4% / -40 mV
BUCK5_PG_WINDOW BUCK5_OV_THR 010b +4% / +40 mV 010b +4% / +40 mV
BUCK5_UV_THR 010b -4% / -40 mV 010b -4% / -40 mV
5.4 LDO Settings
These settings detail the default voltages, configurations, and monitoring of the LDO rails. All these
settings can be changed though I2C after startup.
(1) Note that this NVM default value can change when the device transitions to ACTIVE mode.
Table 7. LDO NVM Settings
Register Name Field Name PTPS659413F0 PTPS659411F0
Value Description Value Description
LDO1_CTRL LDO1_EN(1) 0b LDO1 regulator is
disabled 0b LDO1 regulator is disabled
LDO1_PLDN 01b 125 Ohm 01b 125 Ohm
LDO1_VMON_EN 0b OV and UV
comparators are
disabled
0b OV and UV
comparators are
disabled
LDO1_RV_SEL 1b Enabled 1b Enabled
LDO2_CTRL LDO2_EN(1) 0b LDO2 regulator is
disabled 0b LDO2 regulator is disabled
LDO2_PLDN 01b 125 Ohm 01b 125 Ohm
LDO2_VMON_EN 0b OV and UV
comparators are
disabled
0b OV and UV
comparators are
disabled
LDO2_RV_SEL 1b Enabled 1b Enabled
LDO3_CTRL LDO3_EN(1) 0b LDO3 regulator is
disabled 0b LDO3 regulator is disabled
LDO3_PLDN 11b 500 Ohm 01b 125 Ohm
LDO3_VMON_EN 0b OV and UV
comparators are
disabled
0b OV and UV
comparators are
disabled
LDO3_RV_SEL 1b Enabled 1b Enabled
LDO4_CTRL LDO4_EN(1) 0b LDO4 regulator is
disabled 0b LDO4 regulator is disabled
LDO4_PLDN 01b 125 Ohm 01b 125 Ohm
LDO4_VMON_EN 0b OV and UV
comparators are
disabled
0b OV and UV
comparators are
disabled
LDO4_RV_SEL 1b Enabled 1b Enabled
LDOINT_CTRL LDOINT_VMON_EN 1b OV and UV
comparators are
enabled.
1b OV and UV
comparators are
enabled.

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Table 7. LDO NVM Settings (continued)
Register Name Field Name PTPS659413F0 PTPS659411F0
Value Description Value Description
LDORTC_CTRL LDORTC_VMON_EN 1b UVLO comparator is
enabled. 1b UVLO comparator is enabled.
LDO1_VOUT LDO1_VSET 011100b 1.8 V 111010b 3.3 V
LDO1_BYPASS 0b LDO is set to linear
regulator mode. 1b LDO is set to bypass mode.
LDO2_VOUT LDO2_VSET 011100b 1.8 V 111010b 3.3 V
LDO2_BYPASS 0b LDO is set to linear
regulator mode. 1b LDO is set to bypass mode.
LDO3_VOUT LDO3_VSET 001000b 0.8 V 011100b 1.8 V
LDO3_BYPASS 0b LDO is set to linear
regulator mode. 0b LDO is set to linear regulator mode.
LDO4_VOUT LDO4_VSET 0111000b 1.8 V 0111000b 1.8 V
LDO1_PG_WINDOW LDO1_OV_THR 010b +4% / +40 mV 010b +4% / +40 mV
LDO1_UV_THR 010b -4% / -40 mV 010b -4% / -40 mV
LDO2_PG_WINDOW LDO2_OV_THR 010b +4% / +40 mV 010b +4% / +40 mV
LDO2_UV_THR 010b -4% / -40 mV 010b -4% / -40 mV
LDO3_PG_WINDOW LDO3_OV_THR 010b +4% / +40 mV 010b +4% / +40 mV
LDO3_UV_THR 010b -4% / -40 mV 010b -4% / -40 mV
LDO4_PG_WINDOW LDO4_OV_THR 010b +4% / +40 mV 010b +4% / +40 mV
LDO4_UV_THR 010b -4% / -40 mV 010b -4% / -40 mV
5.5 VCCA Settings
These settings detail the default monitoring enabled on VCCA. All these settings can be changed though
I2C after startup.
Table 8. VCCA NVM Settings
Register Name Field Name PTPS659413F0 PTPS659411F0
Value Description Value Description
VCCA_VMON_CTRL VCCA_VMON_EN 1b OV and UV
comparators are
enabled.
0b OV and UV
comparators are
disabled
VCCA_PG_WINDOW VCCA_OV_THR 111b +10% 111b +10%
VCCA_UV_THR 111b -10% 111b -10%
VCCA_PG_SET 0b 3.3 V 0b 3.3 V
5.6 GPIO Settings
These settings detail the default configurations of the GPIO rails. All these settings can be changed
though I2C after startup. Note that the contents of the GPIOx_SEL field determine which other fields in the
GPIOx_CONF and GPIO_OUT_x registers are applicable. To understand which NVM fields apply to each
GPIOx_SEL option, see the "Digital Signal Descriptions" section in the TPS6594x-Q1 datasheet.

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Table 9. GPIO NVM Settings
Register Name Field Name PTPS659413F0 PTPS659411F0
Value Description Value Description
GPIO1_CONF GPIO1_OD 1b Open-drain output 0b Push-pull output
GPIO1_DIR 0b Input 0b Input
GPIO1_SEL 001b SCL_I2C2/CS_SPI 000b GPIO1
GPIO1_PU_SEL 0b Pull-down resistor
selected 0b Pull-down resistor selected
GPIO1_PU_PD_EN 0b Pull-up/pull-down
resistor disabled 0b Pull-up/pull-down resistor disabled
GPIO1_DEGLITCH_EN 0b No deglitch, only
synchronization. 0b No deglitch, only synchronization.
GPIO2_CONF GPIO2_OD 1b Open-drain output 0b Push-pull output
GPIO2_DIR 0b Input 0b Input
GPIO2_SEL 010b SDA_I2C2/SDO_SPI 000b GPIO2
GPIO2_PU_SEL 0b Pull-down resistor
selected 1b Pull-up resistor selected
GPIO2_PU_PD_EN 0b Pull-up/pull-down
resistor disabled 1b Pull-up/pull-down resistor enabled
GPIO2_DEGLITCH_EN 0b No deglitch, only
synchronization. 0b No deglitch, only synchronization.
GPIO3_CONF GPIO3_OD 0b Push-pull output 0b Push-pull output
GPIO3_DIR 1b Output 1b Output
GPIO3_SEL 000b GPIO3 000b GPIO3
GPIO3_PU_SEL 0b Pull-down resistor
selected 0b Pull-down resistor selected
GPIO3_PU_PD_EN 0b Pull-up/pull-down
resistor disabled 0b Pull-up/pull-down resistor disabled
GPIO3_DEGLITCH_EN 0b No deglitch, only
synchronization. 0b No deglitch, only synchronization.
GPIO4_CONF GPIO4_OD 1b Open-drain output 1b Open-drain output
GPIO4_DIR 0b Input 1b Output
GPIO4_SEL 000b GPIO4 000b GPIO4
GPIO4_PU_SEL 0b Pull-down resistor
selected 0b Pull-down resistor selected
GPIO4_PU_PD_EN 1b Pull-up/pull-down
resistor enabled 0b Pull-up/pull-down resistor disabled
GPIO4_DEGLITCH_EN 0b No deglitch, only
synchronization. 0b No deglitch, only synchronization.
GPIO5_CONF GPIO5_OD 0b Push-pull output 0b Push-pull output
GPIO5_DIR 1b Output 0b Input
GPIO5_SEL 001b SCLK_SPMI 001b SCLK_SPMI
GPIO5_PU_SEL 0b Pull-down resistor
selected 0b Pull-down resistor selected
GPIO5_PU_PD_EN 0b Pull-up/pull-down
resistor disabled 0b Pull-up/pull-down resistor disabled
GPIO5_DEGLITCH_EN 0b No deglitch, only
synchronization. 0b No deglitch, only synchronization.

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Table 9. GPIO NVM Settings (continued)
Register Name Field Name PTPS659413F0 PTPS659411F0
Value Description Value Description
GPIO6_CONF GPIO6_OD 0b Push-pull output 0b Push-pull output
GPIO6_DIR 1b Output 0b Input
GPIO6_SEL 001b SDATA_SPMI 001b SDATA_SPMI
GPIO6_PU_SEL 0b Pull-down resistor
selected 0b Pull-down resistor selected
GPIO6_PU_PD_EN 0b Pull-up/pull-down
resistor disabled 0b Pull-up/pull-down resistor disabled
GPIO6_DEGLITCH_EN 0b No deglitch, only
synchronization. 0b No deglitch, only synchronization.
GPIO7_CONF GPIO7_OD 1b Open-drain output 0b Push-pull output
GPIO7_DIR 0b Input 1b Output
GPIO7_SEL 001b NERR_MCU 000b GPIO7
GPIO7_PU_SEL 0b Pull-down resistor
selected 0b Pull-down resistor selected
GPIO7_PU_PD_EN 1b Pull-up/pull-down
resistor enabled 0b Pull-up/pull-down resistor disabled
GPIO7_DEGLITCH_EN 1b 10 us deglitch time. 0b No deglitch, only
synchronization.
GPIO8_CONF GPIO8_OD 1b Open-drain output 0b Push-pull output
GPIO8_DIR 0b Input 1b Output
GPIO8_SEL 011b DISABLE_WDOG 000b GPIO8
GPIO8_PU_SEL 0b Pull-down resistor
selected 0b Pull-down resistor selected
GPIO8_PU_PD_EN 1b Pull-up/pull-down
resistor enabled 0b Pull-up/pull-down resistor disabled
GPIO8_DEGLITCH_EN 1b 10 us deglitch time. 0b No deglitch, only
synchronization.
GPIO9_CONF GPIO9_OD 1b Open-drain output 0b Push-pull output
GPIO9_DIR 0b Input 1b Output
GPIO9_SEL 100b NSLEEP1 000b GPIO9
GPIO9_PU_SEL 0b Pull-down resistor
selected 0b Pull-down resistor selected
GPIO9_PU_PD_EN 0b Pull-up/pull-down
resistor disabled 0b Pull-up/pull-down resistor disabled
GPIO9_DEGLITCH_EN 0b No deglitch, only
synchronization. 0b No deglitch, only synchronization.
GPIO10_CONF GPIO10_OD 1b Open-drain output 0b Push-pull output
GPIO10_DIR 0b Input 0b Input
GPIO10_SEL 110b WKUP1 000b GPIO10
GPIO10_PU_SEL 0b Pull-down resistor
selected 0b Pull-down resistor selected
GPIO10_PU_PD_EN 1b Pull-up/pull-down
resistor enabled 1b Pull-up/pull-down resistor enabled
GPIO10_DEGLITCH_EN 0b No deglitch, only
synchronization. 0b No deglitch, only synchronization.

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Table 9. GPIO NVM Settings (continued)
Register Name Field Name PTPS659413F0 PTPS659411F0
Value Description Value Description
(1) Note that this NVM default value can change when the device transitions to ACTIVE mode.
GPIO11_CONF GPIO11_OD 1b Open-drain output 0b Push-pull output
GPIO11_DIR 1b Output 1b Output
GPIO11_SEL 010b NRSTOUT_SOC 000b GPIO11
GPIO11_PU_SEL 0b Pull-down resistor
selected 0b Pull-down resistor selected
GPIO11_PU_PD_EN 0b Pull-up/pull-down
resistor disabled 0b Pull-up/pull-down resistor disabled
GPIO11_DEGLITCH_EN 0b No deglitch, only
synchronization. 0b No deglitch, only synchronization.
NPWRON_CONF NPWRON_SEL 00b ENABLE 00b ENABLE
ENABLE_PU_SEL 0b Pull-down resistor
selected 0b Pull-down resistor selected
ENABLE_PU_PD_EN 1b Pull-up/pull-down
resistor enabled 0b Pull-up/pull-down resistor disabled
ENABLE_DEGLITCH_EN 1b 10 us deglitch time
when ENABLE, 50 ms
deglitch time when
NPWRON.
1b 10 us deglitch time
when ENABLE, 50 ms
deglitch time when
NPWRON.
ENABLE_POL 0b Active high 0b Active high
NRSTOUT_OD 1b Open-drain output 0b Push-pull output
GPIO_OUT_1 GPIO1_OUT(1) 0b Low 0b Low
GPIO2_OUT(1) 0b Low 0b Low
GPIO3_OUT(1) 0b Low 0b Low
GPIO4_OUT(1) 0b Low 0b Low
GPIO5_OUT(1) 0b Low 0b Low
GPIO6_OUT(1) 0b Low 0b Low
GPIO7_OUT(1) 0b Low 0b Low
GPIO8_OUT(1) 0b Low 0b Low
GPIO_OUT_2 GPIO9_OUT(1) 0b Low 0b Low
GPIO10_OUT(1) 0b Low 0b Low
GPIO11_OUT(1) 0b Low 0b Low
5.7 Finite State Machine (FSM) Settings
These settings describe how the PMIC output rails are assigned to various system-level states. Also, the
default trigger for each system-level state is described. All these settings can be changed though I2C after
startup.
Table 10. FSM NVM Settings
Register Name Field Name PTPS659413F0 PTPS659411F0
Value Description Value Description
RAIL_SEL_1 BUCK1_GRP_SEL 10b SOC rail group 10b SOC rail group
BUCK2_GRP_SEL 10b SOC rail group 10b SOC rail group
BUCK3_GRP_SEL 01b MCU rail group 10b SOC rail group
BUCK4_GRP_SEL 01b MCU rail group 10b SOC rail group

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Table 10. FSM NVM Settings (continued)
Register Name Field Name PTPS659413F0 PTPS659411F0
Value Description Value Description
RAIL_SEL_2 BUCK5_GRP_SEL 10b SOC rail group 10b SOC rail group
LDO1_GRP_SEL 01b MCU rail group 10b SOC rail group
LDO2_GRP_SEL 01b MCU rail group 10b SOC rail group
LDO3_GRP_SEL 10b SOC rail group 10b SOC rail group
RAIL_SEL_3 LDO4_GRP_SEL 01b MCU rail group 10b SOC rail group
VCCA_GRP_SEL 01b MCU rail group 01b MCU rail group
FSM_TRIG_SEL_1 MCU_RAIL_TRIG 10b MCU power error 10b MCU power error
SOC_RAIL_TRIG 11b SOC power error 11b SOC power error
OTHER_RAIL_TRIG 11b SOC power error 11b SOC power error
SEVERE_ERR_TRIG 00b Immediate shutdown 00b Immediate shutdown
FSM_TRIG_SEL_2 MODERATE_ERR_TRIG 01b Orderly shutdown 01b Orderly shutdown
5.8 Interrupt Settings
These settings detail the default configurations for what is monitored by nINT pin. All these settings can be
changed though I2C after startup.
Table 11. Interrupt NVM Settings
Register Name Field Name PTPS659413F0 PTPS659411F0
Value Description Value Description
FSM_TRIG_MASK_1 GPIO1_FSM_MASK 1b Masked 1b Masked
GPIO1_FSM_MASK_POL 0b Masking sets signal
value to '0' 0b Masking sets signal value to '0'
GPIO2_FSM_MASK 1b Masked 0b Not masked
GPIO2_FSM_MASK_POL 0b Masking sets signal
value to '0' 0b Masking sets signal value to '0'
GPIO3_FSM_MASK 1b Masked 1b Masked
GPIO3_FSM_MASK_POL 0b Masking sets signal
value to '0' 0b Masking sets signal value to '0'
GPIO4_FSM_MASK 0b Not masked 1b Masked
GPIO4_FSM_MASK_POL 0b Masking sets signal
value to '0' 0b Masking sets signal value to '0'
FSM_TRIG_MASK_2 GPIO5_FSM_MASK 1b Masked 1b Masked
GPIO5_FSM_MASK_POL 0b Masking sets signal
value to '0' 0b Masking sets signal value to '0'
GPIO6_FSM_MASK 1b Masked 1b Masked
GPIO6_FSM_MASK_POL 0b Masking sets signal
value to '0' 0b Masking sets signal value to '0'
GPIO7_FSM_MASK 1b Masked 1b Masked
GPIO7_FSM_MASK_POL 1b Masking sets signal
value to '1' 0b Masking sets signal value to '0'
GPIO8_FSM_MASK 1b Masked 1b Masked
GPIO8_FSM_MASK_POL 0b Masking sets signal
value to '0' 0b Masking sets signal value to '0'

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Table 11. Interrupt NVM Settings (continued)
Register Name Field Name PTPS659413F0 PTPS659411F0
Value Description Value Description
FSM_TRIG_MASK_3 GPIO9_FSM_MASK 1b Masked 1b Masked
GPIO9_FSM_MASK_POL 0b Masking sets signal
value to '0' 0b Masking sets signal value to '0'
GPIO10_FSM_MASK 1b Masked 1b Masked
GPIO10_FSM_MASK_POL 0b Masking sets signal
value to '0' 0b Masking sets signal value to '0'
GPIO11_FSM_MASK 1b Masked 1b Masked
GPIO11_FSM_MASK_POL 0b Masking sets signal
value to '0' 0b Masking sets signal value to '0'
MASK_BUCK1_2 BUCK1_ILIM_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
BUCK1_OV_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
BUCK1_UV_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
BUCK2_ILIM_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
BUCK2_OV_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
BUCK2_UV_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
MASK_BUCK3_4 BUCK3_ILIM_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
BUCK3_OV_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
BUCK3_UV_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
BUCK4_OV_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
BUCK4_UV_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
BUCK4_ILIM_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
MASK_BUCK5 BUCK5_ILIM_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
BUCK5_OV_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
BUCK5_UV_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
MASK_LDO1_2 LDO1_OV_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
LDO1_UV_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
LDO2_OV_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
LDO2_UV_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
LDO1_ILIM_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
LDO2_ILIM_MASK 1b Interrupt not
generated. 1b Interrupt not generated.

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Table 11. Interrupt NVM Settings (continued)
Register Name Field Name PTPS659413F0 PTPS659411F0
Value Description Value Description
MASK_LDO3_4 LDO3_OV_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
LDO3_UV_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
LDO4_OV_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
LDO4_UV_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
LDO3_ILIM_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
LDO4_ILIM_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
MASK_VMON VCCA_OV_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
VCCA_UV_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
MASK_GPIO1_8_FALL GPIO1_FALL_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
GPIO2_FALL_MASK 1b Interrupt not
generated. 0b Interrupt generated
GPIO3_FALL_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
GPIO4_FALL_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
GPIO5_FALL_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
GPIO6_FALL_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
GPIO7_FALL_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
GPIO8_FALL_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
MASK_GPIO1_8_RISE GPIO1_RISE_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
GPIO2_RISE_MASK 1b Interrupt not
generated. 0b Interrupt generated
GPIO3_RISE_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
GPIO4_RISE_MASK 0b Interrupt generated 1b Interrupt not
generated.
GPIO5_RISE_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
GPIO6_RISE_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
GPIO7_RISE_MASK 0b Interrupt generated 1b Interrupt not
generated.
GPIO8_RISE_MASK 0b Interrupt generated 1b Interrupt not
generated.

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Table 11. Interrupt NVM Settings (continued)
Register Name Field Name PTPS659413F0 PTPS659411F0
Value Description Value Description
MASK_GPIO9_11 GPIO9_FALL_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
GPIO9_RISE_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
GPIO10_FALL_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
GPIO11_FALL_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
GPIO10_RISE_MASK 0b Interrupt generated 1b Interrupt not
generated.
GPIO11_RISE_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
MASK_STARTUP NPWRON_START_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
ENABLE_MASK 0b Interrupt generated 0b Interrupt generated
FSD_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
MASK_MISC TWARN_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
BIST_PASS_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
EXT_CLK_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
MASK_MODERATE_E
RR BIST_FAIL_MASK 1b Interrupt not generated. 1b Interrupt not generated.
REG_CRC_ERR_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
SPMI_ERR_MASK 0b Interrupt generated 0b Interrupt generated
NPWRON_LONG_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
PFSM_ERR_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
MASK_FSM_ERR IMM_SHUTDOWN_MASK 0b Interrupt generated 0b Interrupt generated
MCU_PWR_ERR_MASK 0b Interrupt generated 0b Interrupt generated
SOC_PWR_ERR_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
ORD_SHUTDOWN_MASK 0b Interrupt generated 0b Interrupt generated
MASK_COMM_ERR COMM_FRM_ERR_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
COMM_CRC_ERR_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
COMM_ADR_ERR_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
I2C2_CRC_ERR_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
I2C2_ADR_ERR_MASK 1b Interrupt not
generated. 1b Interrupt not generated.
MASK_READBACK_ER
REN_DRV_READBACK_ MASK 0b Interrupt generated 1b Interrupt not generated.
NINT_READBACK_MASK 0b Interrupt generated 0b Interrupt generated
NRSTOUT_READBACK_
MASK 0b Interrupt generated 1b Interrupt not generated.
NRSTOUT_SOC_
READBACK_MASK 0b Interrupt generated 1b Interrupt not generated.