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Introduction
3
SLVUBR0–December 2019
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User's Guide for Powering DRA829V and TDA4VM with the TPS6594-Q1
PMICs
1 Introduction
This user’s guide can be used as a guide to understand the power distribution network (PDN) between the
two TPS6594-Q1 devices and the DRA829V or TDA4VM processor. This guide describes the platform
power resource connections, digital control connections, and the PMIC sequencing settings to support the
different state transitions of the processor. The default NVM contents are also included in this guide. This
user's guide does not provide information about the electrical characteristics, external components,
package, or the functionality of the PMIC or processor devices. For such information and the full register
map, refer to the datasheet for each device. In the event of any inconsistency between the official
specification and any user's guide, application report, or other referenced material, the data sheet
specification will be the definitive source.
2 Device Versions
There are different versions of the TPS6594-Q1 device available with unique NVM settings to support
different use cases for the processor. The unique NVM settings for each PMIC device are optimized per
PDN design to support different processors, processing loads, SDRAM types, system functional safety
levels, and end product features - such as low power modes, processor interface levels, SD Card, and so
forth. The NVM settings can be distinguished using the NVM_ID register. In this user guide, each PMIC
device is distinguished by the part number, NVM_ID, and NVM_REV values listed in Table 1.
(1) TI recommends having 15% margin between the maximum expected load current and the maximum current allowed per each
PMIC output rail.
Table 1. Dual TPS6594-Q1 NVM Settings and Orderable Part Numbers
PDN USE CASE ORDERABLE PART NUMBER DEVICE MODE NVM_ID NVM_REV
1
• Up to 12 A(1) on the CORE rail
• Up to 6 A(1) on the CPU rails
• Up to 3.4 A(1) on the SDRAM, with support for
LPDDR4
• Supports Functional Safety up to ASIL-D level
• Supports low power modes, including MCU-
only and suspend-to-RAM states
• Supports I/O level of 3.3 V or 1.8 V
• Supports use of SD card
PTPS659413F0RWERQ1 Master 0xF0 0x7
PTPS659411F0RWERQ1 Slave 0xF0 0x7
3 Processor Connection
This section details how the dual TPS6594-Q1 power resources and GPIO signals are connected to the
SoC processor and other peripheral components in order to support the PDN use case.
Figure 1 shows the detailed power mapping between the processor and the TPS659413-Q1 and
TPS659411-Q1 PMICs. In this configuration, both TPS6594-Q1 devices use a 3.3 V input voltage. For
Functional Safety applications, there is a protection FET before VCCA that connects to the OVPGDRV pin
of the master PMIC, allowing voltage monitoring of the input supply to the PMICs.
The VCCA voltage must be the first voltage applied to the PMIC devices, so VIO_IN of the PMICs must be
supplied after VCCA. In this configuration, VIO_IN is supplied by the load switch that also supplies the
VDDSHVx_MCU voltage domain of the processor to allow the digital components of the PMIC devices
(such as GPIOs) to remain supplied in MCU-only mode. Additionally, by controlling VIO_IN of both PMICs
through this load switch, the system can also reduce power consumption in suspend-to-RAM mode, since
the load switch is disabled.
For SD card dual-voltage I/O support (3.3 V and 1.8 V), LDO1 of the TPS659411-Q1 device can be used,
with a control signal from the processor, to switch the LDO1 voltage between 3.3 V and 1.8 V. This allows
control of the LDO1 voltage without the need for the MCU of the processor to establish I2C
communication with the PMICs during boot from SD card operations.
