Texas Instruments CC1070 User manual

CC1070
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CC1070
Single Chip Low Power RF Transmitter for Narrowband Systems
Applications
•Narrowband low power UHF wireless
data transmitters
•402 / 424 / 426 / 429 / 433 / 447 / 449 /
469 / 868 and 915 MHz ISM/SRD
band systems
•TPMS – Tire Pressure Monitoring
Systems
•AMR – Automatic Meter Reading
•Wireless alarm and security systems
•Home automation
•Low power telemetry
Product Description
CC1070
is a true single-chip UHF
transmitter designed for very low power
and very low voltage wireless applications.
The circuit is mainly intended for the ISM
(Industrial, Scientific and Medical) and
SRD (Short Range Device) frequency
bands at 402, 424, 426, 429, 433, 447,
449, 469, 868 and 915 MHz, but can
easily be programmed for multi-channel
operation at other frequencies in the 402 -
470 and 804 - 940 MHz range.
The
CC1070
is especially suited for narrow-
band systems with channel spacings of
12.5 or 25 kHz complying with ARIB STD
T-67 and EN 300 220.
The
CC1070
main operating parameters
can be programmed via a serial bus, thus
making
CC1070
a very flexible and easy to
use transmitter. In a typical application
CC1070
will be used together with a
microcontroller and a few external passive
components.
Features
•True single chip UHF RF transmitter
•Frequency range 402 - 470 MHz and
804 - 940 MHz
•Programmable output power
•Low supply voltage (2.3 to 3.6 V)
•Very few external components required
•Small size (QFN 20 package)
•Pb-free package
•Data rate up to 153.6 kBaud
•OOK, FSK and GFSK data modulation
•Fully on-chip VCO
•Programmable frequency makes
crystal temperature drift compensation
possible without TCXO
•Suitable for frequency hopping systems
•Suited for systems targeting
compliance with EN 300 220, FCC
CFR47 part 15 and ARIB STD T-67
•Development kit available
•Easy-to-use software for generating the
CC1070
configuration data

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Table of Contents
1Abbreviations................................................................................................................ 4
2Absolute Maximum Ratings ........................................................................................ 5
3Operating Conditions................................................................................................... 5
4Electrical Specifications .............................................................................................. 5
4.1 RF Transmit Section ............................................................................................ 6
4.2 Crystal Oscillator Section..................................................................................... 8
4.3 Frequency Synthesizer Section........................................................................... 9
4.4 Digital Inputs / Outputs ...................................................................................... 10
4.5 Current Consumption......................................................................................... 11
5Pin Assignment........................................................................................................... 12
6Circuit Description...................................................................................................... 13
7Application Circuit...................................................................................................... 13
8Configuration Overview ............................................................................................. 16
8.1 Configuration Software ...................................................................................... 16
9Microcontroller Interface ........................................................................................... 17
9.1 4-wire Serial Configuration Interface ................................................................. 18
9.2 Signal Interface .................................................................................................. 20
10 Data Rate Programming............................................................................................. 22
11 Frequency Programming ........................................................................................... 23
11.1 Dithering ......................................................................................................... 24
12 Transmitter .................................................................................................................. 24
12.1 FSK Modulation Formats ............................................................................... 24
12.2 OOK Modulation............................................................................................. 24
12.3 Output Power Programming........................................................................... 25
12.4 TX Data Latency............................................................................................. 26
12.5 Reducing Spurious Emission and Modulation Bandwidth ............................. 26
13 Output Matching and Filtering .................................................................................. 26
14 Frequency Synthesizer .............................................................................................. 29
14.1 VCO, Charge Pump and PLL Loop Filter....................................................... 29
14.2 VCO and PLL Self-Calibration ....................................................................... 30
14.3 PLL Turn-on Time versus Loop Filter Bandwidth .......................................... 31
14.4 PLL Lock Time versus Loop Filter Bandwidth ............................................... 32
15 VCO Current Control .................................................................................................. 32
16 Power Management.................................................................................................... 33
17 Crystal Oscillator ........................................................................................................ 34
18 Built-in Test Pattern Generator ................................................................................. 36

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19 Interrupt upon PLL Lock............................................................................................ 36
20 PA_EN Digital Output Pin .......................................................................................... 36
20.1 Interfacing an External PA ............................................................................. 36
20.2 General Purpose Output Control Pins ........................................................... 36
20.3 PA_EN Pin Drive ............................................................................................ 37
21 System Considerations and Guidelines................................................................... 37
22 PCB Layout Recommendations ................................................................................ 39
23 Antenna Considerations ............................................................................................ 39
24 Configuration Registers............................................................................................. 40
24.1 CC1070 Register Overview............................................................................ 41
25 Package Marking ........................................................................................................ 52
25.1 Soldering Information ..................................................................................... 52
25.2 Tray Specification........................................................................................... 52
25.3 Carrier Tape and Reel Specification .............................................................. 52
26 Ordering Information.................................................................................................. 53
27 General Information.................................................................................................... 54

CC1070
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1 Abbreviations
ACP Adjacent Channel Power
AMR Automatic Meter Reading
ASK Amplitude Shift Keying
BOM Bill Of Materials
bps bits per second
BT Bandwidth-Time product (for GFSK)
CW Continuous Wave
DNM Do Not Mount
ESR Equivalent Series Resistance
FHSS Frequency Hopping Spread Spectrum
FM Frequency Modulation
FS Frequency Synthesizer
FSK Frequency Shift Keying
GFSK Gaussian Frequency Shift Keying
IC Integrated Circuit
ISM Industrial Scientific Medical
kbps kilo bits per second
MCU Micro Controller Unit
NA Not Applicable
NRZ Non Return to Zero
OOK On-Off Keying
PA Power Amplifier
PD Phase Detector / Power Down
PCB Printed Circuit Board
PN9 Pseudo-random Bit Sequence (9-bit)
PLL Phase Locked Loop
PSEL Program Select
RF Radio Frequency
SPI Serial Peripheral Interface
SRD Short Range Device
TBD To Be Decided/Defined
TX Transmit (mode)
UHF Ultra High Frequency
VCO Voltage Controlled Oscillator
XOSC Crystal oscillator
XTAL Crystal

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2 Absolute Maximum Ratings
The absolute maximum ratings given Table 1 should under no circumstances be violated.
Stress exceeding one or more of the limiting values may cause permanent damage to the
device.
Parameter Min Max Unit Condition
Supply voltage, VDD -0.3 5.0 V All supply pins must have the
same voltage
Voltage on any pin -0.3 VDD+0.3, max 5.0 V
Storage temperature range -50 150 °C
Package body temperature 260 °C Norm: IPC/JEDEC J-STD-020C 1
Humidity non-condensing 5 85 %
ESD 500 V CDM model
Table 1. Absolute maximum ratings
1The reflow peak soldering temperature (body temperature) is specified according to
IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid
State Surface Mount Devices”.
Caution! ESD sensitive device.
Precaution should be used when handling
the device in order to prevent permanent
damage.
3 Operating Conditions
The operating conditions for
CC1070
are listed in Table 2.
Parameter
Min Typ Max Unit Condition / Note
RF Frequency Range 402
804
470
940
MHz
MHz
Programmable in <300 Hz steps
Programmable in <600 Hz steps
Operating ambient temperature range
-40 105
°C
Supply voltage
2.3 3.0 3.6 V
The same supply voltage should
be used for digital (DVDD) and
analog (AVDD) power.
A 3.0 ±0.1 V supply is
recommended to meet the ARIB
STD T-67 output power tolerance
requirement.
Table 2. Operating conditions
4 Electrical Specifications
Table 3 to Table 7 gives the
CC1070
electrical specifications. All measurements were
performed using the 2 layer PCB CC1070EM reference design. This is the same test circuit
as shown in Figure 3. Temperature = 25°C, supply voltage = AVDD = DVDD = 3.0 V if
nothing else stated. Crystal frequency = 14.7456 MHz.
The electrical specifications given for 868 MHz are also applicable for the 902 – 928 MHz
frequency range.

CC1070
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4.1 RF Transmit Section
Parameter
Min. Typ. Max. Unit Condition / Note
Transmit data rate
0.45
153.6 kBaud The data rate is programmable.
See section 10 on page 22 for
details.
NRZ or Manchester encoding can
be used. 153.6 kBaud equals
153.6 kbps using NRZ coding
and 76.8 kbps using Manchester
coding. See section 9.2 on page
20 for details.
Binary FSK frequency separation
0
0
108
216
kHz
kHz
in 402 - 470 MHz range
in 804 - 940 MHz range
108/216 kHz is the maximum
separation at 1.84 MHz reference
frequency. Larger separations
can be achieved at higher
reference frequencies.
Output power
433 MHz
868 MHz
-20 to +10
-20 to +8
dBm
dBm
Delivered to 50 Ωsingle-ended
load. The output power is
programmable and should not be
programmed to exceed +10/+8
dBm at 433/868 MHz under any
operating conditions. See section
13 on page 26 for details.
Output power tolerance
-4
+3
dB
dB
At maximum output power
At 2.3 V, +105oC
At 3.6 V, -40oC
Harmonics, radiated CW
2nd harmonic, 433 MHz, +10 dBm
3rd harmonic, 433 MHz, +10 dBm
2nd harmonic, 868 MHz, +8 dBm
3rd harmonic, 868 MHz, +8 dBm
-50
-60
-50
-57
dBc
dBc
dBc
dBc
Harmonics are measured as
EIRP values according to EN 300
220. The antenna (SMAFF-433
and SMAFF-868 from R.W.
Badland) plays a part in
attenuating the harmonics.
Adjacent channel power (GFSK)
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
-47
-50
dBc
dBc
For 12.5 kHz channel spacing
ACP is measured in a ±4.25 kHz
bandwidth at ±12.5 kHz offset.
Modulation: 2.4 kBaud NRZ PN9
sequence, ±2.025 kHz frequency
deviation.
For 25 kHz channel spacing ACP
is measured in a ±8.5 kHz
bandwidth at ±25 kHz offset.
Modulation: 4.8 kBaud NRZ PN9
sequence, ±2.475 kHz frequency
deviation.
Occupied bandwidth (99.5%,GFSK)
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
7
10
kHz
kHz
Bandwidth for 99.5% of total
average power.
Modulation for 12.5 channel
spacing: 2.4 kBaud NRZ PN9
sequence, ±2.025 kHz frequency
deviation.
Modulation for 25 kHz channel
spacing: 4.8 kBaud NRZ PN9
sequence, ±2.475 kHz frequency
deviation.

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Parameter
Min. Typ. Max. Unit Condition / Note
Modulation bandwidth, 868 MHz
19.2 kBaud, ±9.9 kHz frequency
deviation
38.4 kBaud, ±19.8 kHz frequency
deviation
48
106
kHz
kHz
Bandwidth where the power
envelope of modulation equals
–36 dBm. Spectrum analyzer
RBW = 1 kHz.
Spurious emission, radiated CW
47-74, 87.5-118,
174-230, 470-862 MHz
9 kHz – 1 GHz
1 – 4 GHz
-54
-36
-30
dBm
dBm
dBm
At maximum output power,
+10/+8 dBm at 433/868 MHz.
To comply with EN 300 220,
FCC CFR47 part 15 and ARIB
STD T-67 an external (antenna)
filter, as implemented in the
application circuit in Figure 14,
must be used and tailored to
each individual design to reduce
out-of-band spurious emission
levels.
Spurious emissions can be
measured as EIRP values
according to EN 300 220. The
antenna (SMAFF-433 and
SMAFF-868 from R.W. Badland)
plays a part in attenuating the
spurious emissions.
If the output power is increased
using an external PA, a filter must
be used to attenuate spurs below
862 MHz when operating in the
868 MHz frequency band in
Europe. Application Note AN036
CC1020/1021 Spurious Emission
presents and discusses a solution
that reduces the TX mode
spurious emission close to 862
MHz by increasing the REF_DIV
from 1 to 7.
Optimum load impedance
433 MHz
868 MHz
915 MHz
91 + j16
34 + j25
28 + j21
Ω
Ω
Ω
Transmit mode. For matching
details see section 13 on page
26.
Table 3. RF transmit parameters

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4.2 Crystal Oscillator Section
Parameter
Min. Typ. Max. Unit Condition / Note
Crystal Oscillator Frequency
4.9152 14.7456 19.6608 MHz
Crystal operation
Parallel
C4 and C5 are loading
capacitors. See section 17 on
page 34 for details.
Crystal load capacitance
12
12
12
22
16
16
30
30
16
pF
pF
pF
4-6 MHz, 22 pF recommended
6-8 MHz, 16 pF recommended
8-20 MHz, 16 pF recommended
Crystal oscillator start-up time 1.55
0.90
0.95
0.63
ms
ms
ms
ms
4.9152 MHz, 12 pF load
9.8304 MHz, 12 pF load
14.7456 MHz, 16 pF load
19.6608 MHz, 12 pF load
External clock signal drive,
sine wave
300
mVpp
The external clock signal must be
connected to XOSC_Q1 using a
DC block (10 nF). Set
XOSC_BYPASS = 0 in the
INTERFACE register when using
an external clock signal with low
amplitude or a crystal.
External clock signal drive,
full-swing digital external clock
0 - VDD
V
The external clock signal must be
connected to XOSC_Q1. No DC
block shall be used. Set
XOSC_BYPASS = 1 in the
INTERFACE register when using
a full-swing digital external clock
Reference frequency accuracy
requirement
+/- 5.7
+/- 2.8
+/- 4
+/- 7
ppm
ppm
ppm
ppm
433 MHz (EN 300 220)
868 MHz (EN 300 220)
Must be less than ±5.7 / ±2.8
ppm to comply with EN 300 220
25 kHz channel spacing at
433/868 MHz.
Must be less than ±4 ppm to
comply with Japanese 12.5 kHz
channel spacing regulations
(ARIB STD T-67). NOTE: This
imposes special requirements on
the receiver of the signal.
Must be less than ±7 ppm to
comply with Korean 12.5 kHz
channel spacing regulations.
NOTE: This imposes special
requirements on the receiver of
the signal.
NOTE:
The reference frequency
accuracy (initial tolerance) and
drift (aging and temperature
dependency) will determine the
frequency accuracy of the
transmitted signal.
Crystal oscillator temperature
compensation can be done using
the fine frequency
programmability.
Table 4. Crystal oscillator parameters

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4.3 Frequency Synthesizer Section
Parameter
Min. Typ. Max. Unit Condition / Note
Phase noise, 402 – 470 MHz
12.5 kHz channel spacing
−87
−95
−100
−105
−114
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Unmodulated carrier
At 12.5 kHz offset from carrier
At 25 kHz offset from carrier
At 50 kHz offset from carrier
At 100 kHz offset from carrier
At 1 MHz offset from carrier
Measured using loop filter
components given in Table 10.
The phase noise will be higher for
larger PLL loop filter bandwidth.
Phase noise, 804 - 940 MHz
25 kHz channel spacing
−81
−89
−96
−103
−122
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Unmodulated carrier
At 12.5 kHz offset from carrier
At 25 kHz offset from carrier
At 50 kHz offset from carrier
At 100 kHz offset from carrier
At 1 MHz offset from carrier
Measured using loop filter
components given in Table 10.
The phase noise will be higher for
larger PLL loop filter bandwidth.
PLL loop bandwidth
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
5
7
kHz
kHz
After PLL and VCO calibration.
The PLL loop bandwidth is
programmable
PLL lock time (TX_1 / TX_2 turn
time)
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
500 kHz channel spacing
180
270
14
us
us
us
One channel frequency step to
RF frequency within ±10% of
channel spacing. Depends on
loop filter component values and
PLL_BW register setting. See
Table 20 on page 32 for more
details.
PLL turn-on time. From power
down mode with crystal oscillator
running.
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
500 kHz channel spacing
3.2
2.5
700
ms
ms
us
Time from writing to registers to
RF frequency within ±10% of
channel spacing. Depends on
loop filter component values and
PLL_BW register setting. See
Table 19 on page 32 for more
details.
Table 5. Frequency synthesizer parameters

CC1070
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4.4 Digital Inputs / Outputs
Parameter
Min Typ Max Unit Condition / Note
Logic "0" input voltage
0 0.3*
VDD
V
Logic "1" input voltage
0.7*
VDD
VDD V
Logic "0" output voltage 0
0.4 V Output current −2.0 mA,
3.0 V supply voltage
Logic "1" output voltage 2.5
VDD V Output current 2.0 mA,
3.0 V supply voltage
Logic "0" input current
NA −1 µA Input signal equals GND.
PSEL has an internal pull-up
resistor and during configuration
the current will be -350 µA.
Logic "1" input current
NA 1 µA Input signal equals VDD
DIO setup time 20 ns TX mode, minimum time DIO
must be ready before the positive
edge of DCLK. Data should be
set up on the negative edge of
DCLK.
DIO hold time
10 ns TX mode, minimum time DIO
must be held after the positive
edge of DCLK. Data should be
set up on the negative edge of
DCLK.
Serial interface (PCLK, PDI, PDO
and PSEL) timing specification
See Table 11 on page 20 for
more details
PA_EN pin drive
0.90
0.87
0.81
0.69
0.93
0.92
0.89
0.79
mA
mA
mA
mA
mA
mA
mA
mA
Source current
0 V on PA_EN pin
0.5 V on PA_EN pin
1.0 V on PA_EN pin
1.5 V on PA_EN pin
Sink current
3.0 V on PA_EN pin
2.5 V on PA_EN pin
2.0 V on PA_EN pin
1.5 V on PA_EN pin
Table 6. Digital inputs / outputs parameters

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4.5 Current Consumption
Parameter
Min. Typ. Max. Unit Condition / Note
Power Down mode
0.2 1
µA Oscillator core off
Current consumption,
433/868 MHz:
P = −20 dBm
P = −5 dBm
P = 0 dBm
P = +5 dBm
P = +8 dBm
P = +10 dBm
12.3/13.9
14.7/16.8
17.5/20.5
21.5/25.3
25.5/33.1
31/NA
mA
mA
mA
mA
mA
mA
The output power is delivered to a
50 Ωsingle-ended load.
See section 12.3 on page 25 for
more details.
Current consumption, crystal
oscillator
Current consumption, crystal
oscillator and bias
Current consumption, crystal
oscillator, bias and synthesizer
65
500
7.5
µA
µA
mA
14.7456 MHz, 16 pF load crystal
14.7456 MHz, 16 pF load crystal
14.7456 MHz, 16 pF load crystal
Table 7. Current consumption

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5 Pin Assignment
Table 8 provides an overview of the
CC1070
pinout.
The
CC1070
comes in a QFN20 type
package.
PCLK 1AVDD15
PA_EN
14
AVDD
13
RF_OUT
12
R_BIAS
11
AVDD10
XOSC_Q2
9
XOSC_Q1
8
LOCK
7
DCLK
6
DVDD 5
PDO 4
PDI 3
DI 2
20PSEL
19DVDD
18CHP_OUT
17AVDD
16VC
AGND
Exposed die
attached pad
Figure 1.
CC1070
package (top view)
Pin no. Pin name Pin type Description
- AGND Ground (analog) Exposed die attached pad. Must be soldered to a solid ground
plane as this is the ground connection for all analog modules See
page 39 for more details.
1 PCLK Digital input Programming clock for SPI configuration interface
2 DI Digital input Data input in transmit mode
3 PDI Digital input Programming data input for SPI configuration interface
4 PDO Digital output Programming data output for SPI configuration interface
5 DVDD Power (digital) Power supply (3 V typical) for digital modules and digital I/O
6 DCLK Digital output Clock for transmit data
7 LOCK Digital output PLL Lock indicator, active low. Output is asserted (low) when PLL
is in lock. The pin can also be used as a general digital output.
8 XOSC_Q1 Analog input Crystal oscillator or external clock input
9 XOSC_Q2 Analog output Crystal oscillator
10 AVDD Power (analog) Power supply (3 V typical) for crystal oscillator and bias generator
(double bonded).
11 R_BIAS Analog output
Connection for external precision bias resistor (82 kΩ, ±1%)
12 RF_OUT RF output RF signal output to antenna
13 AVDD Power (analog) Power supply (3 V typical) for LO buffers, prescaler and PA first
stage
14 PA_EN Digital output General digital output. Can be used for controlling an external PA,
if higher output power is needed.
15 AVDD Power (analog) Power supply (3 V typical) for VCO
16 VC Analog input VCO control voltage input from external loop filter
17 AVDD Power (analog) Power supply (3 V typical) for charge pump and phase detector
18 CHP_OUT Analog output PLL charge pump output to external loop filter
19 DVDD Power (digital) Power supply connection (3 V typical) for digital modules
20 PSEL Digital input Programming chip select, active low, for configuration interface.
Internal pull-up resistor.
Table 8. Pin assignment overview
Note:
DCLK, DI and LOCK are high-impedance
(3-state) in power down (BIAS_PD = 1 in
the MAIN register).
The exposed die attached pad must be
soldered to solid ground plane as this is
the main ground connection for the chip.

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6 Circuit Description
BIAS
DI
LOCK
PDO
DCLK
FREQ
SYNTH
DIGITAL
MODULATOR
- Modulation
- Data shaping
- Power Control
Power
Control
DIGITAL
INTERFACE
TO µC
CONTROL
LOGIC
RF_OUT
R_BIAS XOSC_Q1 XOSC_Q2
XOSC
VC CHP_OUT
:2:2
Multiplexer PCLK
PDI
PSEL
Figure 2.
CC1070
simplified block diagram
A simplified block diagram of
CC1070
is
shown in Figure 2. Only signal pins are
shown.
During transmit operation, the synthesized
RF frequency is fed directly to the power
amplifier (PA). The RF output is frequency
shift keyed (FSK) by the digital bit stream
that is fed to the DI pin. Optionally, the
internal Gaussian filter can be enabled for
Gaussian FSK (GFSK).
The frequency synthesizer includes a
completely on-chip LC VCO. The VCO
operates in the frequency range 1.608-
1.880 GHz. The CHP_OUT pin is the
charge pump output and VC is the control
node of the on-chip VCO. The external
loop filter is placed between these pins. A
crystal is to be connected between
XOSC_Q1 and XOSC_Q2. A lock signal is
available from the PLL.
The 4-wire SPI serial interface is used for
configuration.
7 Application Circuit
Very few external components are
required for the operation of
CC1070
. A
typical application circuit is shown in
Figure 3. The external components are
described in Table 9 and values are given
in Table 10.
Output matching
L2, C2 and C3 are used to match the
transmitter to 50 Ω. See section 13 on
page 26 for details. Component values for
the matching network are easily calculated
using the SmartRF®Studio software.
Bias resistor
The precision bias resistor R1 is used to
set an accurate bias current.
PLL loop filter
The loop filter consists of two resistors (R2
and R3) and three capacitors (C6-C8). C7
and C8 may be omitted in applications
where high loop bandwidth is desired. The
values shown in Table 10 can be used for
data rates up to 4.8 kBaud. Component
values for higher data rates are easily
found using the SmartRF®Studio
software.
Crystal
An external crystal with two loading
capacitors (C4 and C5) is used for the
crystal oscillator. See section 17 on page
34 for details.
Additional filtering
Additional external components (e.g. RF
LC or SAW filter) may be used in order to
improve the performance in specific
applications. See section 13 on page 26
for further information.
Power supply decoupling and filtering
Power supply decoupling and filtering
must be used (not shown in the
application circuit). The placement and
size of the decoupling capacitors and the
power supply filtering are very important to

CC1070
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achieve the optimum performance for
narrowband applications. TI provides a
reference design that should be followed
very closely.
PCLK
DI
PDI
PDO
DVDD
DCLK
LOCK
XOSC_Q1
XOSC_Q2
AVDD
R_BIAS
RF_OUT
AVDD
PA_EN
AVDD
PSEL
DVDD
CHP_OUT
AVDD
VC
DVDD=3V
1
2
3
4
6
AVDD=3V
LC filter
Monopole antenna
(50 Ohm)
AVDD=3V
DVDD=3V AVDD=3V
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
XTAL
R1
R3
L2
C5 C4
C7 C8C6
C3
Microcontroller configuration interface and signal interface
AVDD=3V
R2
C60
R6
C2
Figure 3. Typical application and test circuit (power supply decoupling not shown)
Ref Description
C2 PA match, see page 26
C3 PA output match and dc block, see page 26
C4 Crystal load capacitor, see page 34
C5 Crystal load capacitor, see page 34
C6 PLL loop filter capacitor
C7 PLL loop filter capacitor (may be omitted for highest loop bandwidth)
C8 PLL loop filter capacitor (may be omitted for highest loop bandwidth)
C60 Decoupling capacitor
L2 PA match and DC bias (supply voltage), see page 26
R1 Precision resistor for current reference generator
R2 PLL loop filter resistor
R3 PLL loop filter resistor
R6 PA output match, see page 26
XTAL Crystal, see page 34
Table 9. Overview of external components (excluding supply decoupling capacitors)

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Item 433 MHz 868 MHz 915 MHz
C2 2.2 pF, 5%, NP0, 0402 1.5 pF, 5%, NP0, 0402 1.5 pF, 5%, NP0, 0402
C3 5.6 pF, 5%, NP0, 0402 10 pF, 5%, NP0, 0402 10 pF, 5%, NP0, 0402
C4 22 pF, 5%, NP0, 0402 22 pF, 5%, NP0, 0402 22 pF, 5%, NP0, 0402
C5 12 pF, 5%, NP0, 0402 12 pF, 5%, NP0, 0402 12 pF, 5%, NP0, 0402
C6 220 nF, 10%, X7R, 0603 100 nF, 10%, X7R, 0603 100 nF, 10%, X7R, 0603
C7 8.2 nF, 10%, X7R, 0402 3.9 nF, 10%, X7R, 0402 3.9 nF, 10%, X7R, 0402
C8 2.2 nF, 10%, X7R, 0402 1.0 nF, 10%, X7R, 0402 1.0 nF, 10%, X7R, 0402
C60 220 pF, 5%, NP0, 0402 220 pF, 5%, NP0, 0402 220 pF, 5%, NP0, 0402
L2 22 nH, 5%, 0402 6.8 nH, 5%, 0402 6.8 nH, 5%, 0402
R1 82 kΩ, 1%, 0402 82 kΩ, 1%, 0402 82 kΩ, 1%, 0402
R2 1.5 kΩ, 5%, 0402 2.2 kΩ, 5%, 0402 2.2 kΩ, 5%, 0402
R3 4.7 kΩ, 5%, 0402 6.8 kΩ, 5%, 0402 6.8 kΩ, 5%, 0402
R6 82 Ω, 5%, 0402 82 Ω, 5%, 0402 82 Ω, 5%, 0402
XTAL 14.7456 MHz crystal,
16 pF load
14.7456 MHz crystal,
16 pF load
14.7456 MHz crystal,
16 pF load
Note: Items shaded vary for different frequencies. For 433 MHz, 12.5 kHz channel, a loop filter with
lower bandwidth is used to improve adjacent and alternate channel rejection.
Table 10. Bill of materials for the application circuit in Figure 3
Note:
The PLL loop filter component values in
Table 10 (R2, R3, C6-C8) can be used for
data rates up to 4.8 kBaud. The SmartRF®
Studio software provides component
values for other data rates using the
equations on page 29.
In the CC1070EM reference design
LQG15HS series inductors from Murata
have been used.

CC1070
SWRS043A Page 16 of 54
8 Configuration Overview
CC1070
can be configured to achieve
optimum performance for different
applications. Through the programmable
configuration registers the following key
parameters can be programmed:
•RF output power
•Frequency synthesizer key
parameters: RF output frequency, FSK
frequency separation, crystal oscillator
reference frequency
•Power-down / power-up mode
•Crystal oscillator power-up / power
down
•Data rate and data format (NRZ,
Manchester coded or UART interface)
•Synthesizer lock indicator mode
•FSK / GFSK / OOK modulation
8.1 Configuration Software
TI provides users of
CC1070
with a
software program, SmartRF®Studio
(Windows interface) that generates all
necessary
CC1070
configuration data
based on the user's selections of various
parameters. These hexadecimal numbers
will then be the necessary input to the
microcontroller for the configuration of
CC1070
. In addition, the program will
provide the user with the component
values needed for the output matching
circuit, the PLL loop filter and the LC filter.
Figure 4 shows the user interface of the
CC1070
configuration software.
Figure 4. SmartRF®Studio user interface

CC1070
SWRS043A Page 17 of 54
9 Microcontroller Interface
Used in a typical system,
CC1070
will
interface to a microcontroller. This
microcontroller must be able to:
•Program
CC1070
into different modes
via the 4-wire serial configuration
interface (PDI, PDO, PCLK and PSEL)
•Interface to the synchronous data
signal interface (DI and DCLK)
•Optionally, the microcontroller can do
data encoding
•Optionally, the microcontroller can
monitor the LOCK pin for frequency
lock status or other status information.
Configuration interface
The microcontroller interface is shown in
Figure 5. The microcontroller uses 3 or 4
I/O pins for the configuration interface
(PDI, PDO, PCLK and PSEL). PDO
should be connected to a microcontroller
input. PDI, PCLK and PSEL must be
microcontroller outputs. One I/O pin can
be saved if PDI and PDO are connected
together and a bi-directional pin is used at
the microcontroller.
The microcontroller pins connected to PDI,
PDO and PCLK can be used for other
purposes when the configuration interface
is not used. PDI, PDO and PCLK are high
impedance inputs as long as PSEL is not
activated (active low).
PSEL has an internal pull-up resistor and
should be left open (tri-stated by the
microcontroller) or set to a high level
during power down mode in order to
prevent a trickle current flowing in the pull-
up.
Signal interface
The DI pin is used for data to be
transmitted. DCLK providing the data
timing should be connected to a
microcontroller input.
PLL lock signal
Optionally, one microcontroller pin can be
used to monitor the LOCK signal. This
signal is at low logic level when the PLL is
in lock. It can also be used to monitor
other internal test signals.
CC1070
PDI
PCLK
PSEL
DI
LOCK
Micro-
controller
DCLK
(Optional)
PDO (Optional)
CC1070
PDI
PCLK
PSEL
DI
LOCK
Micro-
controller
DCLK
(Optional)
PDO (Optional)
Figure 5. Microcontroller interface

CC1070
SWRS043A Page 18 of 54
9.1 4-wire Serial Configuration Interface
CC1070
is configured via a simple 4-wire
SPI-compatible interface (PDI, PDO,
PCLK and PSEL) where
CC1070
is the
slave. There are 22 8-bit configuration
registers and 6 8-bit test-only registers,
each addressed by a 7-bit address. A
Read/Write bit initiates a read or write
operation. A full configuration of
CC1070
requires sending 22 data frames of 16 bits
each (7 address bits, R/W bit and 8 data
bits). The time needed for a full
configuration depends on the PCLK
frequency. With a PCLK frequency of 10
MHz the full configuration is done in less
than 36 µs. Setting the device in power
down mode requires sending one frame
only and will in this case take less than 2
µs. All registers are also readable.
In each write-cycle, 16 bits are sent on the
PDI-line. The seven most significant bits of
each data frame (A6:0) are the address-
bits. A6 is the MSB (Most Significant Bit)
of the address and is sent as the first bit.
The next bit is the R/W bit (high for write,
low for read). The 8 data-bits are then
transferred (D7:0). During address and
data transfer the PSEL (Program SELect)
must be kept low. See Figure 6.
The timing for the programming is also
shown in Figure 6 with reference to Table
11. The clocking of the data on PDI is
done on the positive edge of PCLK. Data
should be set up on the negative edge of
PCLK by the microcontroller. When the
last bit, D0, of the 8 data-bits has been
loaded, the data word is loaded in the
internal configuration register.
The configuration data will be retained
during a programmed power-down mode,
but not when the power-supply is turned
off. The registers can be programmed in
any order.
The configuration registers can also be
read by the microcontroller via the same
configuration interface. The seven address
bits are sent first, then the R/W bit set low
to initiate the data read-back.
CC1070
then
returns the data from the addressed
register. PDO is used as the data output
and must be configured as an input by the
microcontroller. The PDO is set at the
negative edge of PCLK and should be
sampled at the positive edge. The read
operation is illustrated in Figure 7.
PSEL must be set high between each
read/write operation.
There are also 5 read-only status
registers.

CC1070
SWRS043A Page 19 of 54
PCLK
PDI
PSEL
Address Write mode
6543210 76543210
Data byte
THD
TSS
TCL,min TCH,min
THS
W
TSD
PDO
Figure 6. Configuration registers write operation
PCLK
PDI
PSEL
A
ddress
Read mode
6
5
4
3210
T
SS
T
CL,min T
CH,min
T
HS
R
PDO
765432
1
0
Data byte
T
SH
Figure 7. Configuration registers read operation

CC1070
SWRS043A Page 20 of 54
Parameter Symbol
Min Max Unit Conditions
PCLK, clock
frequency
FPCLK
10 MHz
PCLK low
pulse
duration
TCL,min 50 ns The minimum time PCLK must be low.
PCLK high
pulse
duration
TCH,min 50 ns The minimum time PCLK must be high.
PSEL setup
time
TSS
25 ns The minimum time PSEL must be low before
positive edge of PCLK.
PSEL hold
time
THS 25 ns The minimum time PSEL must be held low after
the negative edge of PCLK.
PSEL high
time
TSH 50 ns The minimum time PSEL must be high.
PDI setup
time
TSD
25 ns The minimum time data on PDI must be ready
before the positive edge of PCLK.
PDI hold time
THD 25 ns The minimum time data must be held at PDI, after
the positive edge of PCLK.
Rise time Trise 100 ns The maximum rise time for PCLK and PSEL
Fall time Tfall 100 ns The maximum fall time for PCLK and PSEL
Note: The setup and hold times refer to 50% of VDD. The rise and fall times refer to 10% /
90% of VDD. The maximum load that this table is valid for is 20 pF.
Table 11. Serial interface, timing specification
9.2 Signal Interface
The
CC1070
can be used with NRZ (Non-
Return-to-Zero) data or Manchester (also
known as bi-phase-level) encoded data.
The data format is controlled by the
DATA_FORMAT[1:0] bits in the MODEM
register.
CC1070
can be configured for three
different data formats:
Synchronous NRZ mode
During transmit operation, the
CC1070
provides the data clock at DCLK and DI is
used as data input. Data is clocked into
CC1070
at the rising edge of DCLK. The
data is modulated at RF without encoding.
See Figure 8.
Synchronous Manchester encoded
mode
During transmit operation, the
CC1070
provides the data clock at DCLK and DI is
used as data input. Data is clocked into
CC1070
at the rising edge of DCLK and
should be in NRZ format. The data is
modulated at RF with Manchester code.
The encoding is done by
CC1070
. In this
mode the effective bit rate is half the baud
rate due to the coding. As an example,
19.2 kBaud Manchester encoded data
corresponds to a 9.6 kbps. See Figure 9.
Transparent Asynchronous UART
mode
During transmit operation, DI is used as
data input. The data is modulated at RF
without synchronization or encoding. In
this mode, the DCLK pin is not active and
can be set to a high or low level by
DATA_FORMAT[0]. See Figure 10.
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2
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