Texas Instruments CC1070 User manual

CC1070
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CC1070 Single Chip Low Power RF Transmitter for Narrowband Systems
Applications
•Narrowband low power UHF wireless
data transmitters
•402 / 424 / 426 / 429 / 433 / 447 / 449 /
469 / 868 and 915 MHz ISM/SRD
band systems
•TPMS – Tire Pressure Monitoring
Systems
•AMR – Automatic Meter Reading
•Wireless alarm and security systems
•Home automation
•Low power telemetry
Product Description
CC1070 is a true single-chip UHF
transmitter designed for very low power
and very low voltage wireless applications.
The circuit is mainly intended for the ISM
(Industrial, Scientific and Medical) and
SRD (Short Range Device) frequency
bands at 402, 424, 426, 429, 433, 447,
449, 469, 868 and 915 MHz, but can
easily be programmed for multi-channel
operation at other frequencies in the 402 -
470 and 804 - 940 MHz range.
The
CC1070 is especially suited for narrow-
band systems with channel spacings of
12.5 or 25 kHz complying with ARIB STD
T-67 and EN 300 220.
The
CC1070 main operating parameters
can be programmed via a serial bus, thus
making
CC1070 a very flexible and easy to
use transmitter. In a typical application
CC1070 will be used together with a
microcontroller and a few external passive
components.
Features
•True single chip UHF RF transmitter
•Frequency range 402 - 470 MHz and
804 - 940 MHz
•Programmable output power
•Low supply voltage (2.3 to 3.6 V)
•Very few external components required
•Small size (QFN 20 package)
•Pb-free package
•Data rate up to 153.6 kBaud
•OOK, FSK and GFSK data modulation
•Fully on-chip VCO
•Programmable frequency makes
crystal temperature drift compensation
possible without TCXO
•Suitable for frequency hopping systems
•Suited for systems targeting
compliance with EN 300 220, FCC
CFR47 part 15 and ARIB STD T-67
•Development kit available
•Easy-to-use software for generating the
CC1070 configuration data

CC1070
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Table of Contents
1Abbreviations................................................................................................................ 4
2Absolute Maximum Ratings ........................................................................................ 5
3Operating Conditions................................................................................................... 5
4Electrical Specifications .............................................................................................. 5
4.1 RF Transmit Section ............................................................................................ 6
4.2 Crystal Oscillator Section..................................................................................... 8
4.3 Frequency Synthesizer Section........................................................................... 9
4.4 Digital Inputs / Outputs ...................................................................................... 10
4.5 Current Consumption......................................................................................... 11
5Pin Assignment........................................................................................................... 12
6Circuit Description...................................................................................................... 13
7Application Circuit...................................................................................................... 13
8Configuration Overview ............................................................................................. 16
8.1 Configuration Software ...................................................................................... 16
9Microcontroller Interface ........................................................................................... 17
9.1 4-wire Serial Configuration Interface ................................................................. 18
9.2 Signal Interface .................................................................................................. 20
10 Data Rate Programming............................................................................................. 22
11 Frequency Programming ........................................................................................... 23
11.1 Dithering ......................................................................................................... 24
12 Transmitter .................................................................................................................. 24
12.1 FSK Modulation Formats ............................................................................... 24
12.2 OOK Modulation............................................................................................. 24
12.3 Output Power Programming........................................................................... 25
12.4 TX Data Latency............................................................................................. 26
12.5 Reducing Spurious Emission and Modulation Bandwidth ............................. 26
13 Output Matching and Filtering .................................................................................. 26
14 Frequency Synthesizer .............................................................................................. 29
14.1 VCO, Charge Pump and PLL Loop Filter....................................................... 29
14.2 VCO and PLL Self-Calibration ....................................................................... 30
14.3 PLL Turn-on Time versus Loop Filter Bandwidth .......................................... 31
14.4 PLL Lock Time versus Loop Filter Bandwidth ............................................... 32
15 VCO Current Control .................................................................................................. 32
16 Power Management.................................................................................................... 33
17 Crystal Oscillator ........................................................................................................ 34
18 Built-in Test Pattern Generator ................................................................................. 36

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19 Interrupt upon PLL Lock............................................................................................ 36
20 PA_EN Digital Output Pin .......................................................................................... 36
20.1 Interfacing an External PA ............................................................................. 36
20.2 General Purpose Output Control Pins ........................................................... 36
20.3 PA_EN Pin Drive ............................................................................................ 37
21 System Considerations and Guidelines................................................................... 37
22 PCB Layout Recommendations ................................................................................ 39
23 Antenna Considerations ............................................................................................ 39
24 Configuration Registers............................................................................................. 40
24.1 CC1070 Register Overview............................................................................ 41
25 Package Marking ........................................................................................................ 52
25.1 Soldering Information ..................................................................................... 52
25.2 Tray Specification........................................................................................... 52
25.3 Carrier Tape and Reel Specification .............................................................. 52
26 Ordering Information.................................................................................................. 53
27 General Information.................................................................................................... 54

CC1070
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1 Abbreviations
ACP Adjacent Channel Power
AMR Automatic Meter Reading
ASK Amplitude Shift Keying
BOM Bill Of Materials
bps bits per second
BT Bandwidth-Time product (for GFSK)
CW Continuous Wave
DNM Do Not Mount
ESR Equivalent Series Resistance
FHSS Frequency Hopping Spread Spectrum
FM Frequency Modulation
FS Frequency Synthesizer
FSK Frequency Shift Keying
GFSK Gaussian Frequency Shift Keying
IC Integrated Circuit
ISM Industrial Scientific Medical
kbps kilo bits per second
MCU Micro Controller Unit
NA Not Applicable
NRZ Non Return to Zero
OOK On-Off Keying
PA Power Amplifier
PD Phase Detector / Power Down
PCB Printed Circuit Board
PN9 Pseudo-random Bit Sequence (9-bit)
PLL Phase Locked Loop
PSEL Program Select
RF Radio Frequency
SPI Serial Peripheral Interface
SRD Short Range Device
TBD To Be Decided/Defined
TX Transmit (mode)
UHF Ultra High Frequency
VCO Voltage Controlled Oscillator
XOSC Crystal oscillator
XTAL Crystal

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2 Absolute Maximum Ratings
The absolute maximum ratings given Table 1 should under no circumstances be violated.
Stress exceeding one or more of the limiting values may cause permanent damage to the
device.
Parameter Min Max Unit Condition
Supply voltage, VDD -0.3 5.0 V All supply pins must have the
same voltage
Voltage on any pin -0.3 VDD+0.3, max 5.0 V
Storage temperature range -50 150 °C
Package body temperature 260 °C Norm: IPC/JEDEC J-STD-020C 1
Humidity non-condensing 5 85 %
ESD 500 V CDM model
Table 1. Absolute maximum ratings
1The reflow peak soldering temperature (body temperature) is specified according to
IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid
State Surface Mount Devices”.
Caution! ESD sensitive device.
Precaution should be used when handling
the device in order to prevent permanent
damage.
3 Operating Conditions
The operating conditions for
CC1070 are listed in Table 2.
Parameter Min Typ Max Unit Condition / Note
RF Frequency Range 402
804
470
940
MHz
MHz
Programmable in <300 Hz steps
Programmable in <600 Hz steps
Operating ambient temperature range -40 105
°C
Supply voltage 2.3 3.0 3.6 V The same supply voltage should
be used for digital (DVDD) and
analog (AVDD) power.
A 3.0 ±0.1 V supply is
recommended to meet the ARIB
STD T-67 output power tolerance
requirement.
Table 2. Operating conditions
4 Electrical Specifications
Table 3 to Table 7 gives the
CC1070 electrical specifications. All measurements were
performed using the 2 layer PCB CC1070EM reference design. This is the same test circuit
as shown in Figure 3. Temperature = 25°C, supply voltage = AVDD = DVDD = 3.0 V if
nothing else stated. Crystal frequency = 14.7456 MHz.
The electrical specifications given for 868 MHz are also applicable for the 902 – 928 MHz
frequency range.

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4.1 RF Transmit Section
Parameter Min. Typ. Max. Unit Condition / Note
Transmit data rate 0.45 153.6 kBaud The data rate is programmable.
See section 10 on page 22 for
details.
NRZ or Manchester encoding can
be used. 153.6 kBaud equals
153.6 kbps using NRZ coding
and 76.8 kbps using Manchester
coding. See section 9.2 on page
20 for details.
Binary FSK frequency separation
0
0
108
216
kHz
kHz
in 402 - 470 MHz range
in 804 - 940 MHz range
108/216 kHz is the maximum
separation at 1.84 MHz reference
frequency. Larger separations
can be achieved at higher
reference frequencies.
Output power
433 MHz
868 MHz
-20 to +10
-20 to +8
dBm
dBm
Delivered to 50 Ωsingle-ended
load. The output power is
programmable and should not be
programmed to exceed +10/+8
dBm at 433/868 MHz under any
operating conditions. See section
13 on page 26 for details.
Output power tolerance
-4
+3
dB
dB
At maximum output power
At 2.3 V, +105oC
At 3.6 V, -40oC
Harmonics, radiated CW
2nd harmonic, 433 MHz, +10 dBm
3rd harmonic, 433 MHz, +10 dBm
2nd harmonic, 868 MHz, +8 dBm
3rd harmonic, 868 MHz, +8 dBm
-50
-60
-50
-57
dBc
dBc
dBc
dBc
Harmonics are measured as
EIRP values according to EN 300
220. The antenna (SMAFF-433
and SMAFF-868 from R.W.
Badland) plays a part in
attenuating the harmonics.
Adjacent channel power (GFSK)
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
-47
-50
dBc
dBc
For 12.5 kHz channel spacing
ACP is measured in a ±4.25 kHz
bandwidth at ±12.5 kHz offset.
Modulation: 2.4 kBaud NRZ PN9
sequence, ±2.025 kHz frequency
deviation.
For 25 kHz channel spacing ACP
is measured in a ±8.5 kHz
bandwidth at ±25 kHz offset.
Modulation: 4.8 kBaud NRZ PN9
sequence, ±2.475 kHz frequency
deviation.
Occupied bandwidth (99.5%,GFSK)
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
7
10
kHz
kHz
Bandwidth for 99.5% of total
average power.
Modulation for 12.5 channel
spacing: 2.4 kBaud NRZ PN9
sequence, ±2.025 kHz frequency
deviation.
Modulation for 25 kHz channel
spacing: 4.8 kBaud NRZ PN9
sequence, ±2.475 kHz frequency
deviation.

CC1070
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Parameter Min. Typ. Max. Unit Condition / Note
Modulation bandwidth, 868 MHz
19.2 kBaud, ±9.9 kHz frequency
deviation
38.4 kBaud, ±19.8 kHz frequency
deviation
48
106
kHz
kHz
Bandwidth where the power
envelope of modulation equals
–36 dBm. Spectrum analyzer
RBW = 1 kHz.
Spurious emission, radiated CW
47-74, 87.5-118,
174-230, 470-862 MHz
9 kHz – 1 GHz
1 – 4 GHz
-54
-36
-30
dBm
dBm
dBm
At maximum output power,
+10/+8 dBm at 433/868 MHz.
To comply with EN 300 220,
FCC CFR47 part 15 and ARIB
STD T-67 an external (antenna)
filter, as implemented in the
application circuit in Figure 14,
must be used and tailored to
each individual design to reduce
out-of-band spurious emission
levels.
Spurious emissions can be
measured as EIRP values
according to EN 300 220. The
antenna (SMAFF-433 and
SMAFF-868 from R.W. Badland)
plays a part in attenuating the
spurious emissions.
If the output power is increased
using an external PA, a filter must
be used to attenuate spurs below
862 MHz when operating in the
868 MHz frequency band in
Europe. Application Note AN036
CC1020/1021 Spurious Emission
presents and discusses a solution
that reduces the TX mode
spurious emission close to 862
MHz by increasing the REF_DIV
from 1 to 7.
Optimum load impedance
433 MHz
868 MHz
915 MHz
91 + j16
34 + j25
28 + j21
Ω
Ω
Ω
Transmit mode. For matching
details see section 13 on page
26.
Table 3. RF transmit parameters

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4.2 Crystal Oscillator Section
Parameter Min. Typ. Max. Unit Condition / Note
Crystal Oscillator Frequency 4.9152 14.7456 19.6608 MHz
Crystal operation Parallel C4 and C5 are loading
capacitors. See section 17 on
page 34 for details.
Crystal load capacitance
12
12
12
22
16
16
30
30
16
pF
pF
pF
4-6 MHz, 22 pF recommended
6-8 MHz, 16 pF recommended
8-20 MHz, 16 pF recommended
Crystal oscillator start-up time 1.55
0.90
0.95
0.63
ms
ms
ms
ms
4.9152 MHz, 12 pF load
9.8304 MHz, 12 pF load
14.7456 MHz, 16 pF load
19.6608 MHz, 12 pF load
External clock signal drive,
sine wave 300 mVpp
The external clock signal must be
connected to XOSC_Q1 using a
DC block (10 nF). Set
XOSC_BYPASS = 0 in the
INTERFACE register when using
an external clock signal with low
amplitude or a crystal.
External clock signal drive,
full-swing digital external clock 0 - VDD V
The external clock signal must be
connected to XOSC_Q1. No DC
block shall be used. Set
XOSC_BYPASS = 1 in the
INTERFACE register when using
a full-swing digital external clock
Reference frequency accuracy
requirement
+/- 5.7
+/- 2.8
+/- 4
+/- 7
ppm
ppm
ppm
ppm
433 MHz (EN 300 220)
868 MHz (EN 300 220)
Must be less than ±5.7 / ±2.8
ppm to comply with EN 300 220
25 kHz channel spacing at
433/868 MHz.
Must be less than ±4 ppm to
comply with Japanese 12.5 kHz
channel spacing regulations
(ARIB STD T-67). NOTE: This
imposes special requirements on
the receiver of the signal.
Must be less than ±7 ppm to
comply with Korean 12.5 kHz
channel spacing regulations.
NOTE: This imposes special
requirements on the receiver of
the signal.
NOTE:
The reference frequency
accuracy (initial tolerance) and
drift (aging and temperature
dependency) will determine the
frequency accuracy of the
transmitted signal.
Crystal oscillator temperature
compensation can be done using
the fine frequency
programmability.
Table 4. Crystal oscillator parameters

CC1070
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4.3 Frequency Synthesizer Section
Parameter Min. Typ. Max. Unit Condition / Note
Phase noise, 402 – 470 MHz
12.5 kHz channel spacing
−87
−95
−100
−105
−114
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Unmodulated carrier
At 12.5 kHz offset from carrier
At 25 kHz offset from carrier
At 50 kHz offset from carrier
At 100 kHz offset from carrier
At 1 MHz offset from carrier
Measured using loop filter
components given in Table 10.
The phase noise will be higher for
larger PLL loop filter bandwidth.
Phase noise, 804 - 940 MHz
25 kHz channel spacing
−81
−89
−96
−103
−122
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Unmodulated carrier
At 12.5 kHz offset from carrier
At 25 kHz offset from carrier
At 50 kHz offset from carrier
At 100 kHz offset from carrier
At 1 MHz offset from carrier
Measured using loop filter
components given in Table 10.
The phase noise will be higher for
larger PLL loop filter bandwidth.
PLL loop bandwidth
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
5
7
kHz
kHz
After PLL and VCO calibration.
The PLL loop bandwidth is
programmable
PLL lock time (TX_1 / TX_2 turn
time)
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
500 kHz channel spacing
180
270
14
us
us
us
One channel frequency step to
RF frequency within ±10% of
channel spacing. Depends on
loop filter component values and
PLL_BW register setting. See
Table 20 on page 32 for more
details.
PLL turn-on time. From power
down mode with crystal oscillator
running.
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
500 kHz channel spacing
3.2
2.5
700
ms
ms
us
Time from writing to registers to
RF frequency within ±10% of
channel spacing. Depends on
loop filter component values and
PLL_BW register setting. See
Table 19 on page 32 for more
details.
Table 5. Frequency synthesizer parameters

CC1070
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4.4 Digital Inputs / Outputs
Parameter Min Typ Max Unit Condition / Note
Logic "0" input voltage 0 0.3*
VDD
V
Logic "1" input voltage 0.7*
VDD
VDD V
Logic "0" output voltage 0 0.4 V Output current −2.0 mA,
3.0 V supply voltage
Logic "1" output voltage 2.5 VDD V Output current 2.0 mA,
3.0 V supply voltage
Logic "0" input current NA −1 µA Input signal equals GND.
PSEL has an internal pull-up
resistor and during configuration
the current will be -350 µA.
Logic "1" input current NA 1 µA Input signal equals VDD
DIO setup time 20 ns TX mode, minimum time DIO
must be ready before the positive
edge of DCLK. Data should be
set up on the negative edge of
DCLK.
DIO hold time 10 ns TX mode, minimum time DIO
must be held after the positive
edge of DCLK. Data should be
set up on the negative edge of
DCLK.
Serial interface (PCLK, PDI, PDO
and PSEL) timing specification
See Table 11 on page 20 for
more details
PA_EN pin drive
0.90
0.87
0.81
0.69
0.93
0.92
0.89
0.79
mA
mA
mA
mA
mA
mA
mA
mA
Source current
0 V on PA_EN pin
0.5 V on PA_EN pin
1.0 V on PA_EN pin
1.5 V on PA_EN pin
Sink current
3.0 V on PA_EN pin
2.5 V on PA_EN pin
2.0 V on PA_EN pin
1.5 V on PA_EN pin
Table 6. Digital inputs / outputs parameters