Texas Instruments CC112 Series User manual

CC112X/CC1175
SWRU295C Page 1 of 108
CC112X/CC1175 Low-Power High Performance
Sub-1 GHz RF Transceivers/Transmitter
User’s Guide

CC112X/CC1175
SWRU295C Page 2 of 108
Abbreviations
Abbreviations used in this data sheet are described below.
2-FSK
Binary Frequency Shift Keying
LSB
Least Significant Bit
4-FSK
Quaternary Frequency Shift Keying
LQI
Link Quality Indicator
ACP
Adjacent Channel Power
MCU
Microcontroller Unit
ADC
Analog to Digital Converter
MSB
Most Significant Bit
AFC
Automatic Frequency Compensation
MSK
Minimum Shift Keying
AGC
Automatic Gain Control
OOK
On-Off Keying
ASK
Amplitude Shift Keying
PA
Power Amplifier
BT
Bandwidth-Time Product
PD
Power Down
CCA
Clear Channel Assessment
PER
Packet Error Rate
CRC
Cyclic Redundancy Check
PLL
Phase Locked Loop
CS
Carrier Sense
POR
Power-On Reset
DC
Direct Current
PQT
Preamble Quality Threshold
ESR
Equivalent Series Resistance
QPSK
Quadrature Phase Shift Keying
FCC
Federal Communications Commission
RC
Resistor-Capacitor
FIFO
First-In-First-Out
RF
Radio Frequency
FHSS
Frequency Hopping Spread Spectrum
RSSI
Received Signal Strength Indicator
FS
Frequency Synthesizer
RX
Receive, Receive Mode
GFSK
Gaussian shaped Frequency Shift Keying
SPI
Serial Peripheral Interface
IF
Intermediate Frequency
SRD
Short Range Devices
I/Q
In-Phase/Quadrature
TX
Transmit, Transmit Mode
ISM
Industrial, Scientific, Medical
VCO
Voltage Controlled Oscillator
kbps
kilo bit per second
eWOR
Enhanced Wake on Radio
ksps
kilo symbol per second
XOSC
Crystal Oscillator
LNA
Low Noise Amplifier
XTAL
Crystal
LO
Local Oscillator

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Table of Contents
ABBREVIATIONS...............................................................................................................................................2
TABLE OF CONTENTS.....................................................................................................................................3
1OVERVIEW..............................................................................................................................................5
2CONFIGURATION SOFTWARE..........................................................................................................6
3MICROCONTROLLER INTERFACE .................................................................................................7
3.1 CONFIGURATION .........................................................................................................................................7
3.2 SPI ACCESS TYPES....................................................................................................................................10
3.3 OPTIONAL PIN CTRL RADIO CONTROL FEATURE ....................................................................................18
3.4 GENERAL PURPOSE INPUT/OUTPUT CONTROL PINS ..................................................................................18
4COMMON RECEIVE AND TRANSMIT CONFIGURATIONS......................................................24
4.1 MODULATION FORMATS............................................................................................................................24
4.2 DATA RATE PROGRAMMING......................................................................................................................29
5RECEIVE CONFIGURATION ............................................................................................................30
5.1 RX FILTER BANDWIDTH............................................................................................................................30
5.2 DC OFFSET REMOVAL...............................................................................................................................31
5.3 AUTOMATIC GAIN CONTROL.....................................................................................................................31
5.4 IMAGE COMPENSATION .............................................................................................................................32
5.5 BIT SYNCHRONIZATION.............................................................................................................................33
5.6 BYTE SYNCHRONIZATION,SYNC WORD DETECTION.................................................................................33
5.7 PREAMBLE DETECTION .............................................................................................................................34
5.8 RSSI..........................................................................................................................................................34
5.9 COLLISION DETECTOR...............................................................................................................................38
5.10 CLEAR CHANNEL ASSESSMENT (CCA) .....................................................................................................39
5.11 LISTEN BEFORE TALK (LBT) ....................................................................................................................40
5.12 LINK QUALITY INDICATOR (LQI)..............................................................................................................40
6TRANSMIT CONFIGURATION.........................................................................................................41
6.1 PA OUTPUT POWER PROGRAMMING .........................................................................................................41
6.2 OOK/ASK BIT SHAPING...........................................................................................................................41
7PACKET HANDLING HARDWARE SUPPORT..............................................................................42
7.1 STANDARD PACKET FORMAT ....................................................................................................................42
7.2 PACKET FILTERING IN RECEIVE MODE......................................................................................................48
7.3 PACKET HANDLING IN TRANSMIT MODE...................................................................................................49
7.4 PACKET HANDLING IN RECEIVE MODE .....................................................................................................49
7.5 PACKET HANDLING IN FIRMWARE.............................................................................................................49
7.6 TX FIFO AND RX FIFO............................................................................................................................50
7.7 TRANSPARENT AND SYNCHRONOUS SERIAL OPERATION ..........................................................................51
8RADIO CONTROL................................................................................................................................53
8.1 POWER-ON START-UP SEQUENCE.............................................................................................................53
8.2 CRYSTAL CONTROL...................................................................................................................................53
8.3 VOLTAGE REGULATOR CONTROL..............................................................................................................53
8.4 ACTIVE MODES .........................................................................................................................................54
8.5 RX TERMINATION .....................................................................................................................................55
8.6 ENHANCED WAKE ON RADIO (EWOR)......................................................................................................58
8.7 RX SNIFF MODE........................................................................................................................................61
8.8 RC OSCILLATOR CALIBRATION.................................................................................................................63
8.9 ANTENNA DIVERSITY AND MULTIPLE PATH TRANSMISSION....................................................................63
8.10 RANDOM NUMBER GENERATOR................................................................................................................64
8.11 FREQUENCY SYNTHESIZER CONFIGURATION.............................................................................................64
8.12 RF PROGRAMMING....................................................................................................................................64
8.13 IF PROGRAMMING .....................................................................................................................................65
8.14 FS CALIBRATION.......................................................................................................................................65
8.15 FS OUT OF LOCK DETECTION....................................................................................................................66
9SYSTEM CONSIDERATIONS AND GUIDELINES.........................................................................67
9.1 VOLTAGE REGULATORS ............................................................................................................................67
9.2 SRD REGULATIONS...................................................................................................................................67
9.3 FREQUENCY HOPPING AND MULTI-CHANNEL SYSTEMS............................................................................67

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9.4 CONTINUOUS TRANSMISSIONS ..................................................................................................................67
9.5 BATTERY OPERATED SYSTEMS .................................................................................................................67
10 REGISTER DESCRIPTION.................................................................................................................68
11 SOLDERING INFORMATION..........................................................................................................106
12 DEVELOPMENT KIT ORDERING INFORMATION ...................................................................106
13 REFERENCES .....................................................................................................................................107
14 GENERAL INFORMATION..............................................................................................................108
14.1 DOCUMENT HISTORY ..............................................................................................................................108

CC112X/CC1175
SWRU295C Page 5 of 108
1Overview
CC112X is a family of high performance low power RF transceivers designed for operation with a
companion MCU. The purpose of this user‟s guide is to describe configurations and functionality
available for implementing a wireless system. CC112X automates all common RF related tasks, greatly
offloading the MCU. Below is a block diagram showing the different parts of the transceiver divided in
an RF related part and a part for digital support functionality.
CC112X
MARC
Main Radio Control Unit
Ultra low power 16 bit
MCU
256 byte
FIFO RAM
buffer
4 kByte
ROM
RF and DSP frontend
Packet handler
and FIFO control
Configuration and
status registers
eWOR
Enhanced ultra low power
Wake On Radio timer
SPI
Serial configuration
and data interface
Interrupt and
IO handler
System bus
PA out
LNA_P
LNA_N
90 dB dynamic
range ADC
90 dB dynamic
range ADC
High linearity
LNA
16 dBm high
efficiency PA
Channel
filter
XOSC
Cordic
AGC
Automatic Gain Control, 60dB VGA range
RSSI measurements and carrier sense detection
Highly flexible FSK / OOK
demodulator
(Optional bit clock)
(Optional low jitter serial
data output for legacy
protocols)
Data interface with
signal chain access
XOSC_Q1
XOSC_Q2
Ultra low power 32 - 40 kHz
auto-calibrated RC oscillator
(Optional 32kHz
clock intput)
CSn (Chip Select)
SI (Serial Input)
SO (Serial Output)
SCLK (Serial Clock)
(Optional GPIO3/2/0)
Modulator
Fully integrated Fractional-N
Frequency Synthesizer
Output power ramping and OOK / ASK modulation
ifamp
ifamp
(optional autodetected
external XOSC / TCXO)
(Optional GPIO for
antenna diversity)
I
Q
Power onReset /
Brown out Reset
Figure 1: CC112X Block Diagram
CC112X can be configured to achieve optimum performance for many different applications using the
SPI interface (see Section 3.1.1 for more details). The following key parameters can be programmed:
Power-down/power-up mode (SLEEP/IDLE)
Crystal oscillator power-up/power-down (IDLE/XOFF)
Receive/transmit mode (RX/TX)
Carrier frequency
Data rate
Modulation format
RX channel filter bandwidth
RF output power
Data buffering with separate 128-byte receive and transmit FIFOs
Packet radio hardware support
Data whitening
Enhanced Wake-On-Radio (eWOR)
Figure 1 shows a simplified state diagram. For detailed information on controlling the CC112X state
machine see Section 8.
The CC1175 is a transmitter based on the CC1120 transceiver. This means that all TX
features/parameters described in this document are valid for the
CC1175
.

CC112X/CC1175
SWRU295C Page 6 of 108
Transmit mode Receive mode
IDLE
Manual freq.
synth. calibration
RX FIFO
ERROR
TX FIFO
ERROR
Frequency
synthesizer on
SFSTXON
SRX or wake-on-radio (WOR)
STX
STX
STX or RXOFF_MODE=10
RXOFF_MODE = 00
SFTX
SRX or TXOFF_MODE = 11
SIDLE
SCAL
SFRX
IDLE
TXOFF_MODE = 00
SFSTXON or RXOFF_MODE = 01
SRX or STX or SFSTXON or wake-on-radio (WOR)
SLEEP
SPWD or wake-on-radio (WOR)
Crystal
oscillator off
SXOFF
CSn = 0
CSn = 0
TXOFF_MODE = 01
Frequency
synthesizer startup,
optional calibration,
settling
Optional freq.
synth. calibration
Default state when the radio is not
receiving or transmitting.
Lowest power mode. Most
register values are retained
(see Table 5 for details ).
All register values are
retained.
Used for calibrating frequency
synthesizer upfront (entering
receive or transmit mode can
then be done quicker).
Transitional state.
Frequency synthesizer is turned on, can optionally be
calibrated, and then settles to the correct frequency.
Transitional state.
Frequency synthesizer is on,
ready to start transmitting.
Transmission starts very
quickly after receiving the STX
command strobe.
Optional transitional state.
In FIFO-based modes,
transmission is turned off and
this state entered if the TX
FIFO becomes empty in the
middle of a packet.
In FIFO-based modes,
reception is turned off and this
state entered if the RX FIFO
overflows.
SRX
Figure 2: Simplified State Diagram
2Configuration Software
CC112X can be configured using the SmartRF™Studio software [1]. SmartRF Studio is highly
recommended for obtaining optimum register settings, and for evaluating performance and
functionality.
After chip reset, all registers have default values and these might differ from the optimum register
setting. It is therefore necessary to configure/reconfigure the radio through the SPI interface after the
chip has been reset. SmartRF Studio provides a code export function making it easy to implement this
in firmware.

CC112X/CC1175
SWRU295C Page 7 of 108
3Microcontroller Interface
3.1 Configuration
In a typical system, CC112X will interface to an MCU. This MCU must be able to communicate with the
CC112X over a 4-wire SPI interface to be able to:
Configure the CC112X
Program CC112X into different modes (RX, TX, SLEEP, IDLE, etc)
Read and write buffered data (RX FIFO and TX FIFO)
Read status information
3.1.1 4-wire Serial Configuration and Data Interface
CC112X is configured via a simple 4-wire SPI-compatible interface (SI, SO, SCLK, and CSn) where
CC112X is the slave. This interface is also used to read and write buffered data. All transfers on the SPI
interface are done most significant bit first.
All transactions on the SPI interface start with a header byte containing a R/W¯ bit, a burst access bit
(B), and a 6-bit address (A5- A0). A status byte is sent on the SO pin each time a header byte is
transmitted on the SI pin (see Section 3.1.2 for more details on the chip status byte).
The CSn pin must be kept low during transfers on the SPI bus. The timing for the address and data
transfers on the SPI interface is shown in Figure 3 with reference to Table 1.
0 B A5A4A3A2A1A0DW7 DW6 DW5 DW4 DW3 DW2 DW1 DW0 X X
S7
tsp
S5S4S3S2S1S0S7S6S5S4S3S2S1S0
Hi Z S0
X
Hi Z
1 B A5A4A3A2A1A0 X X
S7S6S5S4S3S2S1S0DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 S0
Hi Z
0
tch tcl tsd thd tns
SCLK
CSn
SI
SO
SI
SO
Write to Register
Read from Register
Hi Z
Figure 3: Configuration Registers Write and Read Operations

CC112X/CC1175
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Parameter
Description
Min
Max
Units
fSCLK
SCLK frequency read/write access
Note: 100 or 125 ns delay between consecutive data bytes
must be added during burst write access to the configuration
registers depending on fXOSC (40 or 32 MHz)
-
10
fXOSC = 40 MHz
MHz
8
fXOSC = 32 MHz
SCLK frequency read access extended
memory
-
7.7
fXOSC = 40 MHz
6.1
fXOSC = 32 MHz
tsp
CSn low to positive edge on SCLK
50
-
ns
tch
Clock high
47.5
fXOSC = 40 MHz
-
ns
60
fXOSC = 32 MHz
tcl
Clock low
47.5
fXOSC = 40 MHz
-
ns
60
fXOSC = 32 MHz
trise
Clock rise time
-
40
ns
tfall
Clock fall time
-
40
ns
tsd
Setup data before a positive edge on SCLK
10
-
ns
thd
Hold data after positive edge on SCLK
10
-
ns
tns
Negative edge on SCLK to CSn high.
200
-
ns
CSn high time, time from CSn has been pulled
high until it can be pulled low again
50
ns
Table 1: SPI Timing Requirements
When CSn is pulled low, the MCU must wait until CC112X SO pin goes low before starting to transfer
the header byte. This indicates that the crystal is stable. Unless the chip was just reset or was in
SLEEP or XOFF state, or the XOSC configuration has been altered, the SO pin will always go low
immediately after pulling CSn low.
Registers with consecutive addresses can be accessed in an efficient way by setting the burst bit (B)
in the header byte. The address bits (A5- A0) set the start address in an internal address counter. This
counter is incremented by one each new byte (every 8 clock pulses). The burst access is either a
read or write, and must be terminated by setting CSn high.
If a single register shall be accessed multiple times (e.g. SOFT_RX_DATA_OUT/SOFT_TX_DATA_IN
for custom frequency modulation, see Section 4.1.3), the EXT_CTRL.BURST_ADDR_INCR_EN bit can
be set to 0. In this mode the address counter will not increment in burst mode, and it is possible to
read/write the same register repeatedly without address overhead.
Table 3 gives an overview of the different SPI access types possible.
3.1.2 Chip Status Byte
When the header byte, data byte, or command strobe is sent on the SPI interface, the chip status byte
is sent by the CC112X on the SO pin. The status byte contains key status signals, useful for the MCU.
The first bit, S7, is the CHIP_RDYn signal and this signal must go low before the first positive edge of
SCLK. The CHIP_RDYn signal indicates that the crystal is stable.
S6, S5, and S4comprise the STATE value which reflects the state of the chip. In IDLE state the XOSC
and power to the digital core are on and all other modules are in power down. Unless otherwise
stated, registers should not be changed unless the chip is in this state.
Table 2 gives a status byte summary.

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SWRU295C Page 9 of 108
Bits
Name
Description
7
CHIP_RDYn
Stays high until power and crystal have stabilized. Should always be low when using the SPI
interface.
6:4
STATE[2:0]
Indicates the current main state machine mode
Value
State
MARC State
Description
000
IDLE
IDLE
IDLE state
001
RX
RX
RX_END
Receive mode
010
TX
TX
TX_END
Transmit mode
011
FSTXON
FSTXON
Fast TX ready
100
CALIBRATE
BIAS_SETTLE_MC
REG_SETTLE_MC
MANCAL
STARTCAL
ENDCAL
Frequency synthesizer calibration is running
101
SETTLING
BIAS_SETTLE
REG_SETTLE
BWBOOST
FS_LOCK
IFADCON
RXTX_SWITCH
TXRX_SWITCH
IFADCON_TXRX
PLL is settling
110
RX FIFO
ERROR
RX_FIFO_ERR
RX FIFO has over/underflowed. Read out
any useful data, then flush the FIFO with an
SFRX strobe
111
TX FIFO
ERROR
TX_FIFO_ERR
TX FIFO has over/underflowed. Flush the
FIFO with an SFTX strobe
3:0
Reserved
Table 2: Status Byte Summary

CC112X/CC1175
SWRU295C Page 10 of 108
3.2 SPI Access Types
Figure 4 shows the SPI memory map and the following sections are going to explain how the different
SPI access types (see Table 3) should be used. Table 4 shows the SPI address space.
Figure 4: SPI Memory Map
Access type
Command/Address byte
Description
Single Register Access
(register space)
Address: R/W¯ 0 A5A4A3A2A1A0
(A5 - 0 < 0x2F)
The R/W¯ bit determines whether the operation is a read
(1) or a write (0) operation
The register accessed is determined by the address in
A5 - 0
Exactly one data byte is expected after the address byte
The chip status byte is returned on the SO line both
when the address is sent on the SI line as well as when
data are written
Burst Register Access
(register space)
Address: R/W¯ 1 A5A4A3A2A1A0
(A5 - 0 < 0x2F)
The R/W¯ bit determines whether the operation is a read
(1) or a write (0) operation
The address in A5 - 0 determines the first register
accessed, after which an internal address counter is
incremented for each new data byte following the
address byte
Consecutive bytes are expected after the address byte
and the burst access is terminated by setting CSn high
The chip status byte is returned on the SO line both
when the address is sent on the SI line as well as when
data are written
If the internal address counter reaches address 0x2E
(last byte in register space) the counter will not
increment anymore and the same address will be
read/written until the burst access is being terminated
Single Register Access
(extended register space)
Command: R/W¯ 0 1 0 1 1 1 1
Address: A7A6A5A4A3A2A1A0
(A7 - 0: See Table 5)
This access mode starts with a specific command
(0x2F)
The first byte following this command is interpreted as
the extended address
Exactly one data byte is expected after the extended
address byte
When the extended address is sent on the SI line, SO
will return all zeros. The chip status byte is returned on
the SO line when the command is transmitted as well as
when data are written to the extended address
0x00
Register space
0x2E
0x2F Extended address
0x00
Extended register space
0xFF
0x30
Command strobes
0x3D
0x3E FIFO direct access
0x00
Direct FIFO buffer access
(memory mapped
buffers)
0xFF
0x3F FIFO access

CC112X/CC1175
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Access type
Command/Address byte
Description
Burst Register Access
(extended register space)
Command: R/W¯ 1 1 0 1 1 1 1
Address: A7A6A5A4A3A2A1A0
(A7 - 0: See Table 5)
This access mode starts with a specific command
(0x2F)
The first byte following this command is interpreted as
the extended address
Consecutive bytes are expected after the extended
address byte and the burst access is terminated by
setting CSn high
When the extended address is sent on the SI line, SO
will return all zeros. The chip status byte is returned on
the SO line when the command is transmitted as well as
when data are written to the extended address.
If the internal address counter reaches address 0xFF
(last byte in extended register space) the counter will
wrap around to 0x00
Registers not listed in Table 5 can be part of a burst
access
Command Strobe Access
Address: R/W¯ 0 A5A4A3A2A1A0
(0x30 ≤ A5 - 0 ≤ 0x3D)
Accessing one of the command strobe registers triggers
an event determined by the address in A5 - 0, e.g.
resetting the device, enabling the crystal oscillator,
entering TX, etc. No data byte is expected.
The chip status byte is returned on the SO line when a
command strobe is sent on the SI line
Direct FIFO Access
Command: R/W¯ B 1 1 1 1 1 0
Address: A7A6A5A4A3A2A1A0
A7 - 0 < 0x80: TX FIFO
0x80 ≤ A7 - 0 ≤ 0xFF: RX FIFO
This access mode starts with a specific command
(0x3E) which makes it possible to access the FIFOs
directly through memory operations without affecting the
FIFO pointers.
The first byte following this command is interpreted as
the FIFO address. The next byte is read/written to this
address. If burst is enabled, consecutive bytes will be
read/written by incrementing the address.1
FIFO pointers are available in extended register space
for debug purposes.
Standard FIFO Access
Address: R/W¯ B 1 1 1 1 1 1
The R/W¯ bit determines whether the operation is a read
(1) operation from the RX FIFO or a write (0) operation
to the TX FIFO. If the burst bit B is 1, all bytes following
the address byte are treated as data bytes until CSn
goes high. If the burst bit B is 0, the FIFOs are
accessed byte-wise as a normal register.
Table 3: SPI Access Types
1
Note that the first byte received in an empty RX FIFO will not be possible to read using direct FIFO
access. Please see Section 3.2.3 for more details.

CC112X/CC1175
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Write
Read
Single Byte
Burst
Single Byte
Burst
+0x00
+0x40
+0x80
+0xC0
0x00
IOCFG3
R/W configuration registers, burst access possible
0x01
IOCFG2
0x02
IOCFG1
0x03
IOCFG0
0x04
SYNC3
0x05
SYNC2
0x06
SYNC1
0x07
SYNC0
0x08
SYNC_CFG1
0x09
SYNC_CFG0
0x0A
DEVIATION_M
0x0B
MODCFG_DEV_E
0x0C
DCFILT_CFG
0x0D
PREAMBLE_CFG1
0x0E
PREAMBLE_CFG0
0x0F
FREQ_IF_CFG
0x10
IQIC
0x11
CHAN_BW
0x12
MDMCFG1
0x13
MDMCFG0
0x14
DRATE2
0x15
DRATE1
0x16
DRATE0
0x17
AGC_REF
0x18
AGC_CS_THR
0x19
AGC_GAIN_ADJUST
0x1A
AGC_CFG3
0x1B
AGC_CFG2
0x1C
AGC_CFG1
0x1D
AGC_CFG0
0x1E
FIFO_CFG
0x1F
DEV_ADDR
0x20
SETTLING_CFG
0x21
FS_CFG
0x22
WOR_CFG1
0x23
WOR_CFG0
0x24
WOR_EVENT0_MSB
0x25
WOR_EVENT0_LSB
0x26
PKT_CFG2
0x27
PKT_CFG1
0x28
PKT_CFG0
0x29
RFEND_CFG1
0x2A
RFEND_CFG0
0x2B
PA_CFG2
0x2C
PA_CFG1
0x2D
PA_CFG0
0x2E
PKT_LEN
0x2F
EXTENDED MEMORY ACCESS
0x30
SRES
SRES
Command Strobes
0x31
SFSTXON
SFSTXON
0x32
SXOFF
SXOFF
0x33
SCAL
SCAL
0x34
SRX
SRX
0x35
STX
STX
0x36
SIDLE
SIDLE
0x37
SAFC
SAFC
0x38
SWOR
SWOR
0x39
SPWD
SPWD
0x3A
SFRX
SFRX
0x3B
SFTX
SFTX
0x3C
SWORRST
SWORRST
0x3D
SNOP
SNOP
0x3E
DIRECT FIFO ACCESS
0x3F
TX FIFO
TX FIFO
RX FIFO
RX FIFO
Table 4: SPI Address Space

CC112X/CC1175
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3.2.1 Register Space Access and Extended Register Space Access
The configuration registers on the CC112X are located on SPI addresses from 0x00 to 0x2E (register
space) with address extension command at address 0x2F to access the extended register space (see
Figure 4). All configuration registers can be both written to and read and this is controlled by the R/W¯
bit in the header byte. All configuration registers can also be accessed with the burst bit (B) set to
either 1 or 0. Note that all registers in register space (address 0x00 - 0x2E) have retention. In
extended register space, the status register do not have retention. Please see Table 5 for details.
Extended Register Space (0x00 - 0x23)
Retention
0x00
IF_MIX_CFG
Yes
0x01
FREQOFF_CFG
Yes
0x02
TOC_CFG
Yes
0x03
MARC_SPARE
Yes
0x04
ECG_CFG
Yes
0x05
SOFT_TX_DATA_CFG
Yes
0x06
EXT_CTRL
Yes
0x07
RCCAL_FINE
Yes
0x08
RCCAL_COARSE
Yes
0x09
RCCAL_OFFSET
Yes
0x0A
FREQOFF1
Yes
0x0B
FREQOFF0
Yes
0x0C
FREQ2
Yes
0x0D
FREQ1
Yes
0x0E
FREQ0
Yes
0x0F
IF_ADC2
Yes
0x10
IF_ADC1
Yes
0x11
IF_ADC0
Yes
0x12
FS_DIG1
Yes
0x13
FS_DIG0
Yes
0x14
FS_CAL3
Yes
0x15
FS_CAL2
Yes
0x16
FS_CAL1
Yes
0x17
FS_CAL0
Yes
0x18
FS_CHP
Yes
0x19
FS_DIVTWO
Yes
0x1A
FS_DSM1
Yes
0x1B
FS_DSM0
Yes
0x1C
FS_DVC1
Yes
0x1D
FS_DVC0
Yes
0x1E
FS_LBI
Yes
0x1F
FS_PFD
Yes
0x20
FS_PRE
Yes
0x21
FS_REG_DIV_CML
Yes
0x22
FS_SPARE
Yes
0x23
FS_VCO4
Yes
Extended Register Space (0x24 - 0x6E)
Retention
0x24
FS_VCO3
Yes
0x25
FS_VCO2
Yes
0x26
FS_VCO1
Yes
0x27
FS_VCO0
Yes
0x28
GBIAS6
Yes
0x29
GBIAS5
Yes
0x2A
GBIAS4
Yes
0x2B
GBIAS3
Yes
0x2C
GBIAS2
Yes
0x2D
GBIAS1
Yes
0x2E
GBIAS0
Yes
0x2F
IFAMP
Yes
0x30
LNA
Yes
0x31
RXMIX
Yes
0x32
XOSC5
Yes
0x33
XOSC4
Yes
0x34
XOSC3
Yes
0x35
XOSC2
Yes
0x36
XOSC1
Yes
0x37
XOSC0
Yes
0x38
ANALOG_SPARE
Yes
0x39
PA_CFG3
Yes
0x3A - 0x3E
Not Used
0x3F - 0x40
Reserved
0x41 - 0x63
Not Used
0x64
WOR_TIME1
No
0x65
WOR_TIME0
No
0x66
WOR_CAPTURE1
No
0x67
WOR_CAPTURE0
No
0x68
BIST
No
0x69
DCFILTOFFSET_I1
No
0x6A
DCFILTOFFSET_I0
No
0x6B
DCFILTOFFSET_Q1
No
0x6C
DCFILTOFFSET_Q0
No
0x6D
IQIE_I1
No
0x6E
IQIE_I0
No

CC112X/CC1175
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Extended Register Space (0x6F - 0x8C)
Retention
0x6F
IQIE_Q1
No
0x70
IQIE_Q0
No
0x71
RSSI1
No
0x72
RSSI0
No
0x73
MARCSTATE
No
0x74
LQI_VAL
No
0x75
PQT_SYNC_ERR
No
0x76
DEM_STATUS
No
0x77
FREQOFF_EST1
No
0x78
FREQOFF_EST0
No
0x79
AGC_GAIN3
No
0x7A
AGC_GAIN2
No
0x7B
AGC_GAIN1
No
0x7C
AGC_GAIN0
No
0x7D
SOFT_RX_DATA_OUT
No
0x7E
SOFT_TX_DATA_IN
No
0x7F
ASK_SOFT_RX_DATA
No
0x80
RNDGEN
No
0x81
MAGN2
No
0x82
MAGN1
No
0x83
MAGN0
No
0x84
ANG1
No
0x85
ANG0
No
0x86
CHFILT_I2
No
0x87
CHFILT_I1
No
0x88
CHFILT_I0
No
0x89
CHFILT_Q2
No
0x8A
CHFILT_Q1
No
0x8B
CHFILT_Q0
No
0x8C
GPIO_STATUS
No
Extended Register Space (0x8D - 0xD9)
Retention
0x8D
FSCAL_CTRL
No
0x8E
PHASE_ADJUST
No
0x8F
PARTNUMBER
No
0x90
PARTVERSION
No
0x91
SERIAL_STATUS
No
0x92
RX_STATUS
No
0x93
TX_STATUS
No
0x94
MARC_STATUS1
No
0x95
MARC_STATUS0
No
0x96
PA_IFAMP_TEST
No
0x97
FSRF_TEST
No
0x98
PRE_TEST
No
0x99
PRE_OVR
No
0x9A
ADC_TEST
No
0x9B
DVC_TEST
No
0x9C
ATEST
No
0x9D
ATEST_LVDS
No
0x9E
ATEST_MODE
No
0x9F
XOSC_TEST1
No
0xA0
XOSC_TEST0
No
0xA1 - 0xD1
Not Used
0xD2
RXFIRST
No
0xD3
TXFIRST
No
0xD4
RXLAST
No
0xD5
TXLAST
No
0xD6
NUM_TXBYTES
No
0xD7
NUM_RXBYTES
No
0xD8
FIFO_NUM_TXBYTES
No
0xD9
FIFO_NUM_RXBYTES
No
Table 5: Extended Register Space Mapping
3.2.2 Command Strobes
Command Strobes may be viewed as single byte instructions to CC112X . By addressing a command
strobe register, internal sequences will be started. These commands are used to enable receive and
transmit mode, enter SLEEP mode, disable the crystal oscillator, etc. The command strobes are listed
in Table 6.The command strobe registers are accessed by transferring a single header byte (no data
is being transferred). That is, only the R/W¯ bit, the burst access bit (set to 0), and the six address bits
(in the range 0x30 through 0x3D) are written. When sending a strobe, the R/W¯ bit can be either one
or zero. The status byte is available on the SO pin when a command strobe is being sent.

CC112X/CC1175
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Address
Strobe
Name
Description
0x30
SRES
Reset chip
0x31
SFSTXON
Enable and calibrate frequency synthesizer (if SETTLING_CFG.FS_AUTOCAL = 1).
If in RX and PKT_CFG2.CCA_MODE ≠ 0: Go to a wait state where only the synthesizer is running
(for quick RX/TX turnaround).
0x32
SXOFF
Enter XOFF state when CSn is de-asserted
0x33
SCAL
Calibrate frequency synthesizer and turn it off. SCAL can be strobed from IDLE mode without
setting manual calibration mode (SETTLING_CFG.FS_AUTOCAL = 0)
0x34
SRX
Enable RX. Perform calibration first if coming from IDLE and SETTLING_CFG.FS_AUTOCAL = 1
0x35
STX
In IDLE state: Enable TX. Perform calibration first if SETTLING_CFG.FS_AUTOCAL = 1.
If in RX state and PKT_CFG2.CCA_MODE ≠ 0: Only go to TX if channel is clear
0x36
SIDLE
Exit RX/TX, turn off frequency synthesizer and exit eWOR mode if applicable
0x37
SAFC
Automatic Frequency Compensation
0x38
SWOR
Start automatic RX polling sequence (eWOR) as described in Section 8.6 if
WOR_CFG0.RC_PD = 0
0x39
SPWD
Enter SLEEP mode when CSn is de-asserted
0x3A
SFRX
Flush the RX FIFO. Only issue SFRX in IDLE or RX_FIFO_ERR states
0x3B
SFTX
Flush the TX FIFO. Only issue SFTX in IDLE or TX_FIFO_ERR states
0x3C
SWORRST
Reset the eWOR timer to the Event1 value
0x3D
SNOP
No operation. May be used to get access to the chip status byte
Table 6: Command Strobes
A command strobe may be followed by any other SPI access without pulling CSn high, and the
command strobes are executed immediately. This applies for all command strobes except SRES,
SPWD, SWOR, and the SXOFF strobe.
When a SRES strobe is issued the CSn pin must be kept low and wait for SO to go low again before
the next header byte can be issued, as shown in Figure 5.
SI HeaderSRES HeaderAddr Data
SO
CSn
x
Figure 5: SRES Command Strobe
The SPWD, SWOR, and the SXOFF command strobes are not executed before the CSn goes high.
3.2.3 Direct FIFO Access
The complete RX and TX FIFOs, with associated pointers, are mapped in the register space for FIFO
manipulation and SW-debug purposes. The FIFOs are mapped as shown in Table 7 (the address
must be preceded by the command 0x3E) while the FIFO pointers are located in extended register
space (address 0xD2 - 0xD5, see Table 5).
Direct FIFO Access Mapping
Retention
0x00 - 0x7F
TXFIFO
No
0x80 - 0xFF
RXFIFO
No
Table 7: Direct FIFO Access Mapping

CC112X/CC1175
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Both FIFO data and pointers are readable and writeable to enable e.g. re-transmissions, partial flush,
partial readouts, changing only the sequence number before re-transmission etc. Figure 6 shows how
the TX FIFO pointer changes as the FIFO is written and as data are sent on the air (assume variable
packet length mode PKT_CFG0.LENGTH_CONFIG = 01b.
0 1 2 3 4 5 6 7 8 9 10 126 127
1 D02 3 x xD1D2D3D4D5x x
TXFIRST TXLAST
NUM_TXBYTES = 0x09
STX:
0 1 2 3 4 5 6 7 8 9 10 126 127
1 D02 3 x xD1D2D3D4D5x x
TXFIRST TXLAST
NUM_TXBYTES = 0x07
1 D0transmitted on the air
STX: transmitted on the air2 D1D2
0 1 2 3 4 5 6 7 8 9 10 126 127
1 D02 3 x xD1D2D3D4D5x x
TXFIRST TXLAST
NUM_TXBYTES = 0x04
STX: transmitted on the air3 D3D4D5
0 1 2 3 4 5 6 7 8 9 10 126 127
1 D02 3 x xD1D2D3D4D5x x
TXFIRST
TXLAST
NUM_TXBYTES = 0x00
Figure 6: FIFO Pointers (TX FIFO)
To transmit packet number 3 over again one can simply write 0x05 to the TXFIRST register and then
strobe STX again.
In RX mode, when the RX FIFO is empty (i.e. RXFIRST = RXLAST) the first byte received will not be
available to be read from the RXFIFO using direct FIFO access. Please see Figure 7 (it is assumed
that the receiver uses variable packet length mode (PKT_CFG0.LENGTH_CFG = 01) and that
append status is disabled (PKT_CFG1.APPEND_STATUS = 0) for this example).

CC112X/CC1175
SWRU295C Page 17 of 108
0 1 2 3 4 5 6 7 8 9 10 126 127
x x
RXFIRST
RXLAST
NUM_RXBYTES = 0x00
x x x x x x xxxxx
transmitted on the air and received by
the radio
3 D0D1D2
0 1 2 3 4 5 6 7 8 9 10 126 127
x x
RXFIRST RXLAST
NUM_RXBYTES = 0x04
x x x x x x xxD0D1D2
transmitted on the air and received by
the radio
3 D0D1D2
0 1 2 3 4 5 6 7 8 9 10 126 127
x x
RXFIRST RXLAST
x x x xD0D1D2
NUM_RXBYTES = 0x08
3 D0D1D2
Figure 7: FIFO Pointers (RX FIFO) (1)
If 8 bytes (NUM_RXBYTES = 0x08) are read from the RXFIFO using standard FIFO access (see
Section 3.2.4) the following will be read: 3, D0, D1, D2, 3, D0, D1, D2.
If the RX FIFO had been read (using standard FIFO access) in between the two packets, the RX
FIFO pointers would end up with the values shown in Figure 8.
0 1 2 3 4 5 6 7 8 9 10 126 127
x x
RXFIRST RXLAST
x x x xD0D1D2
NUM_RXBYTES = 0x04
D0D1D2x
Figure 8: FIFO Pointers (RX FIFO) (2)
3.2.4 Standard FIFO Access
Using the standard FIFO push/pop interface the 128-byte TX FIFO and the 128-byte RX FIFO are
accessed through the 0x3F address. When the R/W¯ bit is zero the TX FIFO is accessed, and the RX
FIFO is accessed when the R/W¯ bit is one. Using this type of access, the TX FIFO is write-only, while
the RX FIFO is read-only. The burst bit is used to determine if the FIFO access is a single byte access
or a burst access. The single byte access method expects a header byte with the burst bit set to zero
and one data byte. After the data byte, a new header byte is expected; hence CSn can remain low.
The burst access method expects one header byte and then consecutive data bytes until terminating
the access by setting CSn high.

CC112X/CC1175
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If the radio tries to write to the RX FIFO after it is full or if the RX FIFO is tried read when it is empty,
the RXFIFO_OVERFLOW and RXFIFO_UNDERFLOW signals will be asserted and the radio will enter the
RX_FIFO_ERR state. Likewise, if the TX FIFO is tried written when it is full or if the TX FIFO runs
empty in the middle of a packet, the TXFIFO_OVERFLOW and TXFIFO_UNDERFLOW signals will be
asserted and the radio will enter the TX_FIFO_ERR state.
The TX FIFO may be flushed by issuing a SFTX command strobe. Similarly, a SFRX command strobe
will flush the RX FIFO. A SFTX or SFRX command strobe can only be issued in the IDLE,
TX_FIFO_ERR, or RX_FIFO_ERR states. Both FIFOs are flushed when going to the SLEEP state.
3.3 Optional PIN CTRL Radio Control Feature
The CC112X has an optional way of controlling the radio by reusing SI, SCLK, and CSn from the SPI
interface. This feature allows for a simple three-pin control of the major states of the radio: SLEEP,
IDLE, RX, and TX. This optional functionality is enabled with the EXT_CTRL.PIN_CTRL_EN
configuration bit.
State changes are commanded as follows:
When CSn is high, the SI and SCLK are set to the desired state according to Table 8.
When CSn goes low, the state of SI and SCLK is latched and a command strobe is generated
internally according to the pin configuration.
If the device is in the TX state and the TX command is issued, it will be ignored. For RX state, an RX
command will restart RX. When CSn is low the SI and SCLK have normal SPI functionality.
All pin control command strobes are executed immediately, except the SPWD strobe. The SPWD strobe
is delayed until CSn goes high.
Pin control is useful to get precise timing on RX/TX strobes.
CSn
SCLK
SI
Function
1
X
X
Chip unaffected by SCLK/SI
0
0
Generates SPWD strobe
0
1
Generates STX strobe
1
0
Generates SIDLE strobe
1
1
Generates SRX strobe
0
SPI
mode
SPI
mode
SPI mode (wakes up into
IDLE if in SLEEP/XOFF)
Table 8: Optional Pin Control Coding
3.4 General Purpose Input/Output Control Pins
The four digital I/O pins GPIO0, GPIO1, GPIO2 and GPIO3 are general control pins configured with
IOCFGx.GPIOx_CFG (where x is 0, 1, 2, or 3). Table 10 shows the different signals that can be
monitored on the GPIO pins. The signal name field in the table should be interpreted as follows:
One signal name: The signal can be routed out to any of the four GPIO pins for full flexibility
Four signal names: The signal can only be routed out on the GPIO designated in the table.
GPIO1 is shared with the SO pin in the SPI interface. The default setting for GPIO1/SO is HIGHZ (tri-
state) output, which is useful when the SPI interface is shared with other devices. By selecting any
other of the programming options, the GPIO1/SO pin will become a generic pin when CSn is high
and function as SO when CSn is low.
When the IOCFGx.GPIOx_CFG setting is less than 0x30 and IOCFGx.GPIOx_INV is 0 (1) the
GPIO2 pin will be hardwired to 0 (1), and GPIO1 and GPIO3 will be hardwired to 1 (0) in the SLEEP
state. These signals will be hardwired until the CHIP_RDYn signal goes low. GPIO0 will be tri-stated in
SLEEP mode when IOCFG0.GPIO0_CFG[5:4] ≠ 11b. If the IOCFGx.GPIOx_CFG setting is 0x30
or higher, the GPIO pins will work as programmed also in SLEEP state.

CC112X/CC1175
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The GPIOs can also be used as inputs by setting IOCFGx.GPIOx_CFG = HIGHZ (48). Table 9
shows which signals can be input to the CC112X.
GPIO Pin
Signal Name
Signal Description
0
SERIAL_TX
Serial data (TX mode). Used for both synchronous and transparent mode.
Synchronous serial mode: Data is captured on the rising edge of the serial clock
1 - 2
Reserved
3
EXT_32K_CLOCK
External 32 kHz clock signal
Table 9: GPIO Input Pin Mapping
3.4.1 MCU Input/Interrupt
There are two main methods that can be used to generate an input/interrupt to the MCU
1. GPIO Signals
2. MARC MCU WAKEUP
3.4.1.1 GPIO Signals
See Table 10 for the different signals that can be output from the CC112X . Note that all signals
described as a pulse are two XOSC periods long.
GPIOx_CFG
Signal Name
Description
0
RXFIFO_THR
Associated to the RX FIFO. Asserted when the RX FIFO is filled above
FIFO_CFG.FIFO_THR. De-asserted when the RX FIFO is drained below
(or is equal) to the same threshold
1
RXFIFO_THR_PKT
Associated to the RX FIFO. Asserted when the RX FIFO is filled above
FIFO_CFG.FIFO_THR or the end of packet is reached. De-asserted
when the RX FIFO is empty
2
TXFIFO_THR
Associated to the TX FIFO. Asserted when the TX FIFO is filled above
(or is equal to) (127 −FIFO_CFG.FIFO_THR). De-asserted when the TX
FIFO is drained below the same threshold
3
TXFIFO_THR_PKT
Associated to the TX FIFO. Asserted when the TX FIFO is full. De-
asserted when the TX FIFO is drained below
(127 −FIFO_CFG.FIFO_THR)
4
RXFIFO_OVERFLOW
Asserted when the RX FIFO has overflowed. De-asserted when the RX
FIFO is flushed (see Section 3.2.4)
5
TXFIFO_UNDERFLOW
Asserted when the TX FIFO has underflowed. De-asserted when the TX
FIFO is flushed (see Section 3.2.4)
6
PKT_SYNC_RXTX
RX: Asserted when sync word has been received and de-asserted at the
end of the packet. Will de-assert when the optional address and/or
length check fails or the RX FIFO overflows/underflows.
TX: Asserted when sync word has been sent, and de-asserted at the end
of the packet. Will de-assert if the TX FIFO underflows/overflows
7
CRC_OK
Asserted simultaneously as PKT_CRC_OK. De-asserted when the first
byte is read from the RX FIFO
8
SERIAL_CLK
Serial clock (RX and TX mode). Synchronous to the data in synchronous
serial mode. Data is set up on the falling edge in RX and is captured on
the rising edge of the serial clock in TX
9
SERIAL_RX
Serial data (RX mode). Used for both synchronous and transparent
mode.
Synchronous serial mode: Data is set up on the falling edge.
Transparent mode: No timing recovery (outputs just the hard limited
baseband signal)
10
Reserved (used for test)
11
PQT_REACHED
Preamble Quality Reached. Asserted when the quality of the preamble is
above the programmed PQT value (see Section 5.7)
12
PQT_VALID
Preamble quality valid. Asserted when the PQT logic has received a
sufficient number of symbols (see Section 5.7)

CC112X/CC1175
SWRU295C Page 20 of 108
13
RSSI_VALID
RSSI calculation is valid
14
RSSI Signals
3
RSSI_UPDATE
A pulse occurring each time the RSSI value is updated (see Figure 14)
2
RSSI_UPDATE
A pulse occurring each time the RSSI value is updated (see Figure 14)
1
AGC_HOLD
AGC waits for gain settling (see Figure 14)
0
AGC_UPDATE
A pulse occurring each time the front end gain has been adjusted
(see Figure 14)
15
Clear channel assessment
3
CCA_STATUS
Current CCA status
2
TXONCCA_DONE
A pulse occurring when a decision has been made as to whether the
channel is busy or not. This signal must be used as an interrupt to the
MCU. When this signal is asserted/de-asserted, TXONCCA_FAILED can
be checked
1
CCA_STATUS
Current CCA status
0
TXONCCA_FAILED
TX on CCA failed
16
CARRIER_SENSE_VALID
CARRIER_SENSE is valid (see Figure 14)
17
CARRIER_SENSE
Carrier sense. High if RSSI level is above threshold (see section 5.8.1)
(see Figure 14)
18
DSSS signals for DSSS repeat mode (RX). MODCFG_DEV_E.MODEM_MODE = 01b
3
DSSS_CLK
DSSS clock (see Section 4.1.6 for more details)
2
DSSS_DATA0
DSSS data0 (see Section 4.1.6 for more details)
1
DSSS_CLK
DSSS clock (see Section 4.1.6 for more details)
0
DSSS_DATA1
DSSS data1 (see Section 4.1.6 for more details)
19
PKT_CRC_OK
Asserted in RX when PKT_CFG1.CRC_CFG = 01b or 10b and a good
packet is received. This signal is always on if the radio is in TX or if the
radio is in RX and PKT_CFG1.CRC_CFG = 00b. The signal is de-
asserted when RX mode is entered and PKT_CFG1.CRC_CFG ≠ 00b
20
MARC_MCU_WAKEUP
MCU wake up signal. Read MARC_STATUS1.MARC_STATUS_OUT to find
the cause of the wake up event (see Section 3.4.1.2 for more details)
21
SYNC_LOW0_HIGH1
DualSync Detect. Only valid when SYNC_CFG0.SYNC_MODE = 111b.
When SYNC_EVENT is asserted this bit can be checked to see which
sync word is found
22
Reserved (used for test)
23
LNA_PA_REG_PD
Common regulator control for PA and LNA. Indicates RF operation
24
LNA_PD
Control external LNA2
25
PA_PD
Control external PA2
26
RX0TX1_CFG
Indicates whether RF operation is in RX or TX (this signal is 0 in IDLE
state)
27
Reserved (used for test)
28
IMAGE_FOUND
Image detected by image rejection calibration algorithm
29
CLKEN_SOFT
Data clock for demodulator soft data (see Section 4.1.4 for more details)
30
SOFT_TX_DATA_CLK
Data clock for modulator soft data (see Section 4.1.4 for more details)
31 - 32
Reserved (used for test)
2
This signal is active low. To control an external LNA, PA, or RX/TX switch in applications where the
SLEEP state is used it is therefore recommended to map this signal to GDO3 as this signal will be
hardwired to 1(0) in the SLEEP state.