Texas Instruments CC112 Series User manual

CC112X/CC1175
SWRU295C Page 1 of 108
CC112X/CC1175 Low-Power High Performance
Sub-1 GHz RF Transceivers/Transmitter
User’s Guide

CC112X/CC1175
SWRU295C Page 2 of 108
Abbreviations
Abbreviations used in this data sheet are described below.
2-FSK
Binary Frequency Shift Keying
LSB
Least Significant Bit
4-FSK
Quaternary Frequency Shift Keying
LQI
Link Quality Indicator
ACP
Adjacent Channel Power
MCU
Microcontroller Unit
ADC
Analog to Digital Converter
MSB
Most Significant Bit
AFC
Automatic Frequency Compensation
MSK
Minimum Shift Keying
AGC
Automatic Gain Control
OOK
On-Off Keying
ASK
Amplitude Shift Keying
PA
Power Amplifier
BT
Bandwidth-Time Product
PD
Power Down
CCA
Clear Channel Assessment
PER
Packet Error Rate
CRC
Cyclic Redundancy Check
PLL
Phase Locked Loop
CS
Carrier Sense
POR
Power-On Reset
DC
Direct Current
PQT
Preamble Quality Threshold
ESR
Equivalent Series Resistance
QPSK
Quadrature Phase Shift Keying
FCC
Federal Communications Commission
RC
Resistor-Capacitor
FIFO
First-In-First-Out
RF
Radio Frequency
FHSS
Frequency Hopping Spread Spectrum
RSSI
Received Signal Strength Indicator
FS
Frequency Synthesizer
RX
Receive, Receive Mode
GFSK
Gaussian shaped Frequency Shift Keying
SPI
Serial Peripheral Interface
IF
Intermediate Frequency
SRD
Short Range Devices
I/Q
In-Phase/Quadrature
TX
Transmit, Transmit Mode
ISM
Industrial, Scientific, Medical
VCO
Voltage Controlled Oscillator
kbps
kilo bit per second
eWOR
Enhanced Wake on Radio
ksps
kilo symbol per second
XOSC
Crystal Oscillator
LNA
Low Noise Amplifier
XTAL
Crystal
LO
Local Oscillator

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Table of Contents
ABBREVIATIONS...............................................................................................................................................2
TABLE OF CONTENTS.....................................................................................................................................3
1OVERVIEW..............................................................................................................................................5
2CONFIGURATION SOFTWARE..........................................................................................................6
3MICROCONTROLLER INTERFACE .................................................................................................7
3.1 CONFIGURATION .........................................................................................................................................7
3.2 SPI ACCESS TYPES....................................................................................................................................10
3.3 OPTIONAL PIN CTRL RADIO CONTROL FEATURE ....................................................................................18
3.4 GENERAL PURPOSE INPUT/OUTPUT CONTROL PINS ..................................................................................18
4COMMON RECEIVE AND TRANSMIT CONFIGURATIONS......................................................24
4.1 MODULATION FORMATS............................................................................................................................24
4.2 DATA RATE PROGRAMMING......................................................................................................................29
5RECEIVE CONFIGURATION ............................................................................................................30
5.1 RX FILTER BANDWIDTH............................................................................................................................30
5.2 DC OFFSET REMOVAL...............................................................................................................................31
5.3 AUTOMATIC GAIN CONTROL.....................................................................................................................31
5.4 IMAGE COMPENSATION .............................................................................................................................32
5.5 BIT SYNCHRONIZATION.............................................................................................................................33
5.6 BYTE SYNCHRONIZATION,SYNC WORD DETECTION.................................................................................33
5.7 PREAMBLE DETECTION .............................................................................................................................34
5.8 RSSI..........................................................................................................................................................34
5.9 COLLISION DETECTOR...............................................................................................................................38
5.10 CLEAR CHANNEL ASSESSMENT (CCA) .....................................................................................................39
5.11 LISTEN BEFORE TALK (LBT) ....................................................................................................................40
5.12 LINK QUALITY INDICATOR (LQI)..............................................................................................................40
6TRANSMIT CONFIGURATION.........................................................................................................41
6.1 PA OUTPUT POWER PROGRAMMING .........................................................................................................41
6.2 OOK/ASK BIT SHAPING...........................................................................................................................41
7PACKET HANDLING HARDWARE SUPPORT..............................................................................42
7.1 STANDARD PACKET FORMAT ....................................................................................................................42
7.2 PACKET FILTERING IN RECEIVE MODE......................................................................................................48
7.3 PACKET HANDLING IN TRANSMIT MODE...................................................................................................49
7.4 PACKET HANDLING IN RECEIVE MODE .....................................................................................................49
7.5 PACKET HANDLING IN FIRMWARE.............................................................................................................49
7.6 TX FIFO AND RX FIFO............................................................................................................................50
7.7 TRANSPARENT AND SYNCHRONOUS SERIAL OPERATION ..........................................................................51
8RADIO CONTROL................................................................................................................................53
8.1 POWER-ON START-UP SEQUENCE.............................................................................................................53
8.2 CRYSTAL CONTROL...................................................................................................................................53
8.3 VOLTAGE REGULATOR CONTROL..............................................................................................................53
8.4 ACTIVE MODES .........................................................................................................................................54
8.5 RX TERMINATION .....................................................................................................................................55
8.6 ENHANCED WAKE ON RADIO (EWOR)......................................................................................................58
8.7 RX SNIFF MODE........................................................................................................................................61
8.8 RC OSCILLATOR CALIBRATION.................................................................................................................63
8.9 ANTENNA DIVERSITY AND MULTIPLE PATH TRANSMISSION....................................................................63
8.10 RANDOM NUMBER GENERATOR................................................................................................................64
8.11 FREQUENCY SYNTHESIZER CONFIGURATION.............................................................................................64
8.12 RF PROGRAMMING....................................................................................................................................64
8.13 IF PROGRAMMING .....................................................................................................................................65
8.14 FS CALIBRATION.......................................................................................................................................65
8.15 FS OUT OF LOCK DETECTION....................................................................................................................66
9SYSTEM CONSIDERATIONS AND GUIDELINES.........................................................................67
9.1 VOLTAGE REGULATORS ............................................................................................................................67
9.2 SRD REGULATIONS...................................................................................................................................67
9.3 FREQUENCY HOPPING AND MULTI-CHANNEL SYSTEMS............................................................................67

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9.4 CONTINUOUS TRANSMISSIONS ..................................................................................................................67
9.5 BATTERY OPERATED SYSTEMS .................................................................................................................67
10 REGISTER DESCRIPTION.................................................................................................................68
11 SOLDERING INFORMATION..........................................................................................................106
12 DEVELOPMENT KIT ORDERING INFORMATION ...................................................................106
13 REFERENCES .....................................................................................................................................107
14 GENERAL INFORMATION..............................................................................................................108
14.1 DOCUMENT HISTORY ..............................................................................................................................108

CC112X/CC1175
SWRU295C Page 5 of 108
1Overview
CC112X is a family of high performance low power RF transceivers designed for operation with a
companion MCU. The purpose of this user‟s guide is to describe configurations and functionality
available for implementing a wireless system. CC112X automates all common RF related tasks, greatly
offloading the MCU. Below is a block diagram showing the different parts of the transceiver divided in
an RF related part and a part for digital support functionality.
CC112X
MARC
Main Radio Control Unit
Ultra low power 16 bit
MCU
256 byte
FIFO RAM
buffer
4 kByte
ROM
RF and DSP frontend
Packet handler
and FIFO control
Configuration and
status registers
eWOR
Enhanced ultra low power
Wake On Radio timer
SPI
Serial configuration
and data interface
Interrupt and
IO handler
System bus
PA out
LNA_P
LNA_N
90 dB dynamic
range ADC
90 dB dynamic
range ADC
High linearity
LNA
16 dBm high
efficiency PA
Channel
filter
XOSC
Cordic
AGC
Automatic Gain Control, 60dB VGA range
RSSI measurements and carrier sense detection
Highly flexible FSK / OOK
demodulator
(Optional bit clock)
(Optional low jitter serial
data output for legacy
protocols)
Data interface with
signal chain access
XOSC_Q1
XOSC_Q2
Ultra low power 32 - 40 kHz
auto-calibrated RC oscillator
(Optional 32kHz
clock intput)
CSn (Chip Select)
SI (Serial Input)
SO (Serial Output)
SCLK (Serial Clock)
(Optional GPIO3/2/0)
Modulator
Fully integrated Fractional-N
Frequency Synthesizer
Output power ramping and OOK / ASK modulation
ifamp
ifamp
(optional autodetected
external XOSC / TCXO)
(Optional GPIO for
antenna diversity)
I
Q
Power onReset /
Brown out Reset
Figure 1: CC112X Block Diagram
CC112X can be configured to achieve optimum performance for many different applications using the
SPI interface (see Section 3.1.1 for more details). The following key parameters can be programmed:
Power-down/power-up mode (SLEEP/IDLE)
Crystal oscillator power-up/power-down (IDLE/XOFF)
Receive/transmit mode (RX/TX)
Carrier frequency
Data rate
Modulation format
RX channel filter bandwidth
RF output power
Data buffering with separate 128-byte receive and transmit FIFOs
Packet radio hardware support
Data whitening
Enhanced Wake-On-Radio (eWOR)
Figure 1 shows a simplified state diagram. For detailed information on controlling the CC112X state
machine see Section 8.
The CC1175 is a transmitter based on the CC1120 transceiver. This means that all TX
features/parameters described in this document are valid for the
CC1175
.

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Transmit mode Receive mode
IDLE
Manual freq.
synth. calibration
RX FIFO
ERROR
TX FIFO
ERROR
Frequency
synthesizer on
SFSTXON
SRX or wake-on-radio (WOR)
STX
STX
STX or RXOFF_MODE=10
RXOFF_MODE = 00
SFTX
SRX or TXOFF_MODE = 11
SIDLE
SCAL
SFRX
IDLE
TXOFF_MODE = 00
SFSTXON or RXOFF_MODE = 01
SRX or STX or SFSTXON or wake-on-radio (WOR)
SLEEP
SPWD or wake-on-radio (WOR)
Crystal
oscillator off
SXOFF
CSn = 0
CSn = 0
TXOFF_MODE = 01
Frequency
synthesizer startup,
optional calibration,
settling
Optional freq.
synth. calibration
Default state when the radio is not
receiving or transmitting.
Lowest power mode. Most
register values are retained
(see Table 5 for details ).
All register values are
retained.
Used for calibrating frequency
synthesizer upfront (entering
receive or transmit mode can
then be done quicker).
Transitional state.
Frequency synthesizer is turned on, can optionally be
calibrated, and then settles to the correct frequency.
Transitional state.
Frequency synthesizer is on,
ready to start transmitting.
Transmission starts very
quickly after receiving the STX
command strobe.
Optional transitional state.
In FIFO-based modes,
transmission is turned off and
this state entered if the TX
FIFO becomes empty in the
middle of a packet.
In FIFO-based modes,
reception is turned off and this
state entered if the RX FIFO
overflows.
SRX
Figure 2: Simplified State Diagram
2Configuration Software
CC112X can be configured using the SmartRF™Studio software [1]. SmartRF Studio is highly
recommended for obtaining optimum register settings, and for evaluating performance and
functionality.
After chip reset, all registers have default values and these might differ from the optimum register
setting. It is therefore necessary to configure/reconfigure the radio through the SPI interface after the
chip has been reset. SmartRF Studio provides a code export function making it easy to implement this
in firmware.

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3Microcontroller Interface
3.1 Configuration
In a typical system, CC112X will interface to an MCU. This MCU must be able to communicate with the
CC112X over a 4-wire SPI interface to be able to:
Configure the CC112X
Program CC112X into different modes (RX, TX, SLEEP, IDLE, etc)
Read and write buffered data (RX FIFO and TX FIFO)
Read status information
3.1.1 4-wire Serial Configuration and Data Interface
CC112X is configured via a simple 4-wire SPI-compatible interface (SI, SO, SCLK, and CSn) where
CC112X is the slave. This interface is also used to read and write buffered data. All transfers on the SPI
interface are done most significant bit first.
All transactions on the SPI interface start with a header byte containing a R/W¯ bit, a burst access bit
(B), and a 6-bit address (A5- A0). A status byte is sent on the SO pin each time a header byte is
transmitted on the SI pin (see Section 3.1.2 for more details on the chip status byte).
The CSn pin must be kept low during transfers on the SPI bus. The timing for the address and data
transfers on the SPI interface is shown in Figure 3 with reference to Table 1.
0 B A5A4A3A2A1A0DW7 DW6 DW5 DW4 DW3 DW2 DW1 DW0 X X
S7
tsp
S5S4S3S2S1S0S7S6S5S4S3S2S1S0
Hi Z S0
X
Hi Z
1 B A5A4A3A2A1A0 X X
S7S6S5S4S3S2S1S0DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 S0
Hi Z
0
tch tcl tsd thd tns
SCLK
CSn
SI
SO
SI
SO
Write to Register
Read from Register
Hi Z
Figure 3: Configuration Registers Write and Read Operations

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Parameter
Description
Min
Max
Units
fSCLK
SCLK frequency read/write access
Note: 100 or 125 ns delay between consecutive data bytes
must be added during burst write access to the configuration
registers depending on fXOSC (40 or 32 MHz)
-
10
fXOSC = 40 MHz
MHz
8
fXOSC = 32 MHz
SCLK frequency read access extended
memory
-
7.7
fXOSC = 40 MHz
6.1
fXOSC = 32 MHz
tsp
CSn low to positive edge on SCLK
50
-
ns
tch
Clock high
47.5
fXOSC = 40 MHz
-
ns
60
fXOSC = 32 MHz
tcl
Clock low
47.5
fXOSC = 40 MHz
-
ns
60
fXOSC = 32 MHz
trise
Clock rise time
-
40
ns
tfall
Clock fall time
-
40
ns
tsd
Setup data before a positive edge on SCLK
10
-
ns
thd
Hold data after positive edge on SCLK
10
-
ns
tns
Negative edge on SCLK to CSn high.
200
-
ns
CSn high time, time from CSn has been pulled
high until it can be pulled low again
50
ns
Table 1: SPI Timing Requirements
When CSn is pulled low, the MCU must wait until CC112X SO pin goes low before starting to transfer
the header byte. This indicates that the crystal is stable. Unless the chip was just reset or was in
SLEEP or XOFF state, or the XOSC configuration has been altered, the SO pin will always go low
immediately after pulling CSn low.
Registers with consecutive addresses can be accessed in an efficient way by setting the burst bit (B)
in the header byte. The address bits (A5- A0) set the start address in an internal address counter. This
counter is incremented by one each new byte (every 8 clock pulses). The burst access is either a
read or write, and must be terminated by setting CSn high.
If a single register shall be accessed multiple times (e.g. SOFT_RX_DATA_OUT/SOFT_TX_DATA_IN
for custom frequency modulation, see Section 4.1.3), the EXT_CTRL.BURST_ADDR_INCR_EN bit can
be set to 0. In this mode the address counter will not increment in burst mode, and it is possible to
read/write the same register repeatedly without address overhead.
Table 3 gives an overview of the different SPI access types possible.
3.1.2 Chip Status Byte
When the header byte, data byte, or command strobe is sent on the SPI interface, the chip status byte
is sent by the CC112X on the SO pin. The status byte contains key status signals, useful for the MCU.
The first bit, S7, is the CHIP_RDYn signal and this signal must go low before the first positive edge of
SCLK. The CHIP_RDYn signal indicates that the crystal is stable.
S6, S5, and S4comprise the STATE value which reflects the state of the chip. In IDLE state the XOSC
and power to the digital core are on and all other modules are in power down. Unless otherwise
stated, registers should not be changed unless the chip is in this state.
Table 2 gives a status byte summary.

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Bits
Name
Description
7
CHIP_RDYn
Stays high until power and crystal have stabilized. Should always be low when using the SPI
interface.
6:4
STATE[2:0]
Indicates the current main state machine mode
Value
State
MARC State
Description
000
IDLE
IDLE
IDLE state
001
RX
RX
RX_END
Receive mode
010
TX
TX
TX_END
Transmit mode
011
FSTXON
FSTXON
Fast TX ready
100
CALIBRATE
BIAS_SETTLE_MC
REG_SETTLE_MC
MANCAL
STARTCAL
ENDCAL
Frequency synthesizer calibration is running
101
SETTLING
BIAS_SETTLE
REG_SETTLE
BWBOOST
FS_LOCK
IFADCON
RXTX_SWITCH
TXRX_SWITCH
IFADCON_TXRX
PLL is settling
110
RX FIFO
ERROR
RX_FIFO_ERR
RX FIFO has over/underflowed. Read out
any useful data, then flush the FIFO with an
SFRX strobe
111
TX FIFO
ERROR
TX_FIFO_ERR
TX FIFO has over/underflowed. Flush the
FIFO with an SFTX strobe
3:0
Reserved
Table 2: Status Byte Summary

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3.2 SPI Access Types
Figure 4 shows the SPI memory map and the following sections are going to explain how the different
SPI access types (see Table 3) should be used. Table 4 shows the SPI address space.
Figure 4: SPI Memory Map
Access type
Command/Address byte
Description
Single Register Access
(register space)
Address: R/W¯ 0 A5A4A3A2A1A0
(A5 - 0 < 0x2F)
The R/W¯ bit determines whether the operation is a read
(1) or a write (0) operation
The register accessed is determined by the address in
A5 - 0
Exactly one data byte is expected after the address byte
The chip status byte is returned on the SO line both
when the address is sent on the SI line as well as when
data are written
Burst Register Access
(register space)
Address: R/W¯ 1 A5A4A3A2A1A0
(A5 - 0 < 0x2F)
The R/W¯ bit determines whether the operation is a read
(1) or a write (0) operation
The address in A5 - 0 determines the first register
accessed, after which an internal address counter is
incremented for each new data byte following the
address byte
Consecutive bytes are expected after the address byte
and the burst access is terminated by setting CSn high
The chip status byte is returned on the SO line both
when the address is sent on the SI line as well as when
data are written
If the internal address counter reaches address 0x2E
(last byte in register space) the counter will not
increment anymore and the same address will be
read/written until the burst access is being terminated
Single Register Access
(extended register space)
Command: R/W¯ 0 1 0 1 1 1 1
Address: A7A6A5A4A3A2A1A0
(A7 - 0: See Table 5)
This access mode starts with a specific command
(0x2F)
The first byte following this command is interpreted as
the extended address
Exactly one data byte is expected after the extended
address byte
When the extended address is sent on the SI line, SO
will return all zeros. The chip status byte is returned on
the SO line when the command is transmitted as well as
when data are written to the extended address
0x00
Register space
0x2E
0x2F Extended address
0x00
Extended register space
0xFF
0x30
Command strobes
0x3D
0x3E FIFO direct access
0x00
Direct FIFO buffer access
(memory mapped
buffers)
0xFF
0x3F FIFO access