Texas Instruments FlatLink SN75LVDS83B User manual

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LVDS83BTSSOPEVM User’s Guide
User's Guide
SNLU233–October 2017
LVDS83BTSSOPEVM User’s Guide
The SN75LVDS83B FlatLink™ transmitter contains the following functions within a single integrated
circuit:
• Four 7-bit, parallel-load, serial-out, shift registers
• A 7x clock synthesizer
• Five low-voltage differential signaling (LVDS) line drivers
These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five
balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels
with integrated LVDS receivers.
This evaluation module (EVM) acts as a reference design that can be easily modified for any projected
application. Target applications include the following:
• LCD panel drivers
• Ultra-mobile PCs (UMPCs)
• Netbook PCs
• Digital picture frames
Schematics and layout information are included at the end of the manual.

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Contents
1 Introduction ................................................................................................................... 3
2 LVDS83BTSSOPEVM Configuration...................................................................................... 3
2.1 LVDS83BTSSOPEVM Kit Contents.............................................................................. 3
2.2 Description of EVM Board......................................................................................... 3
2.3 Power-Up Sequence ............................................................................................... 4
2.4 Signal Connectivity ................................................................................................. 5
3 PCB Construction .......................................................................................................... 10
3.1 LVDS83BTSSOPEVM Board Layout........................................................................... 10
4 LVDS83BTSSOPEVM Bill of Materials.................................................................................. 17
5 LVDS83BTSSOPEVM Schematics ...................................................................................... 18
List of Figures
1 LVDS83BTSSOPEVM ...................................................................................................... 3
2 Clock Rising Edge (High) Jumper Setting................................................................................ 4
3 Clock Falling Edge (Low) Jumper Setting................................................................................ 4
4 Active Shutdown/Clear Jumper Setting................................................................................... 4
5 24-Bit Color Host to 24-Bit LCD Panel Application With 2 MSB Transfer Over Fourth Data Channel .......... 6
6 24-Bit Color Host to 24-Bit LCD Panel Application With 2 LBS Transfer Over Fourth Data Channel............ 7
7 18-Bit Color Host to 18-Bit LCD Panel Application...................................................................... 8
8 12-Bit Color Host to 18-Bit LCD Panel Application...................................................................... 9
9 24-Bit Color Host to 18-Bit LCD Panel Application .................................................................... 10
10 LVDS83BTSSOPEVM Top Layer........................................................................................ 11
11 LVDS83BTSSOPEVM Layer 2 – GND.................................................................................. 12
12 LVDS83BTSSOPEVM Layer 3 – DUT GND............................................................................ 13
13 LVDS83BTSSOPEVM Layer 4 – VCC .................................................................................... 14
14 LVDS83BTSSOPEVM Layer 5 – GND.................................................................................. 15
15 LVDS83BTSSOPEVM Bottom Layer.................................................................................... 16
16 LVDS83BTSSOPEVM Schematics (1/3)................................................................................ 18
17 LVDS83BTSSOPEVM Schematics (2/3)................................................................................ 19
18 LVDS83BTSSOPEVM Schematic (3/3) ................................................................................. 20
List of Tables
1 BOM.......................................................................................................................... 17
Trademarks
FlatLink is a trademark of Texas Instruments.

CLKIN CLKSEL
DUT_GND SHTDN
DUT_GND
VCCIO DUT_GND SIGNAL_GND VCC
1p8V
2p5V
3p3V
3p3V
P1 P2 P3 P4
LVDS83BTSSOPEVM
INT061A
SIGNAL_GND
DUT_GND
Y2M
J6
Y0P
J9
Y1M
J8
J7
JMP6
U1
PIN1
D19
D20
D21
D22
D24
D25
D26
D8
D9
D12
D13
D14
D15
D18
JMP4
JMP3
JMP2
JMP1
D0
D1
D2
D3
D4
D6
D7
D27
D5
D10
D11
D16
D17
D23
SIGNAL_GNDSIGNAL_GND
SIGNAL_GNDSIGNAL_GND
JMP7 JMP8
Y0M
J10
Y2P
J5
CLKINM
J2
Y3M
J4
Y3P
J3
CLKINP
J1
Y1P
C1
C3
C4
C5
C10
C9
C8
C7
C6 C11
C12
C13
C14
C15
C2
R2
R1
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LVDS83BTSSOPEVM User’s Guide
1 Introduction
The SN75LVDS83B FlatLink transmitter is a single integrated circuit which contains four 7-bit, parallel-
load, serial-out, shift registers, a 7x clock synthesizer, and LVDS line drivers. This user’s guide describes
the construction and handling of the EVM for the SN75LVDS83B. The guide serves as an evaluation tool
for the SN75LVDS83B, as well as a reference design for the device.
Figure 1. LVDS83BTSSOPEVM
2 LVDS83BTSSOPEVM Configuration
2.1 LVDS83BTSSOPEVM Kit Contents
This EVM kit contains the following items:
• LVDS83BTSSOPEVM board
• LVDS83BTSSOPEVM User’s Guide
2.2 Description of EVM Board
The LVDS83BTSSOPEVM is designed to provide straightforward evaluation of the SN75LVDS83B device
using four 7-bit, parallel-load, serial-out, shift registers. Power to the board is provided through banana
jacks P4 for VCC and P1 for VCCIO. For correct board operation, power must be fixed at VCC = 3.3 V,
and the I/O power (VCCIO) may be adjusted at 1.8 V, 2.5 V, or 3.3 V.
The transmission of data bits D0 through D27 occurs as each bit is loaded into registers upon the edge of
the CLKIN signal (JMP5), where the rising or falling edge of the clock may be selected using CLKSEL
(JMP7). To select a clock rising edge, input a high level to CLKSEL. Removing the strap on the jumper
allows the pull-up resistor to pull CLKSEL=high (see Figure 2). To input a low level to select a clock falling
edge, place the strap on the jumper to allow a path to GND (see Figure 3).
Additionally, use of SHTDN (JMP8) for possible Shutdown/Clear settings can be obtained with an active-
low input, by placing the strap on the jumper to allow a path to GND, which inhibits the clock and shuts off
the LVDS output drivers for lower power consumption (see Figure 4). A low-level on this signal clears all
internal registers to a low-level. Remove the strap on JMP8 to enable the device for normal operation.

R2
SHTDN
DUT_GND
JMP8
Pull-up resistor
R1
CLKSEL
DUT_GND
JMP7
Pull-up resistor
R1
CLKSEL
DUT_GND
JMP7
Pull-up resistor
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Figure 2. Clock Rising Edge (High) Jumper Setting
Figure 3. Clock Falling Edge (Low) Jumper Setting
Figure 4. Active Shutdown/Clear Jumper Setting
2.3 Power-Up Sequence
The SN75LVDS83B does not require a specific power-up sequence; however, it is permitted to power up
the IOVCC while VCC, VCCPLL, and VCCLVDS remain powered down and connected to GND. The input
level of Shutdown/Clear during this time does not matter because only the input stage is powered up while
all other devices blocks are still powered down.
Additionally, it is also permitted to power up all 3.3 V power domains while IOVCC is still powered down to
GND. The device will not suffer damage. However, in this case, all the I/Os are detected as logic HIGH,
regardless of the input voltage level. Therefore connecting Shutdown/Clear to GND will still be interpreted
as logic HIGH, consequently turning the LVDS output stage on. The power consumption at this stage is
significantly higher that in standby mode, but lower than normal mode.
The user experience may be impacted by the way a system powers up and powers down an LCD screen.
The following sequences are suggested:
Power-up sequence (SN75LVDS83B SHTDN input initially LOW):
1. Ramp up the LCD power (0.5 ms to 10 ms) with the backlight turned off.
2. Wait an additional 0 to 200 ms to avoid display noise.
3. Enable the video source output – start sending black video data.

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4. Toggle SN75LVDS83B shutdown to SHTDN = VIH.
5. Send > 1 ms of black data to allow the SN75LVDS83B to be phase-locked and allow the display to
show black data first.
6. Start sending true imaging data.
7. Enable the backlight.
Power-down sequence (SN75LVDS83B SHTDN input initially HIGH):
1. Disable the LCD backlight and wait for the minimum time specified in the LCF data sheet for the
backlight to go low.
2. Switch the video source output data from active video to black data image (all visible pixels turn black)
on a drive > 2 frame times.
3. Set SN75LVDS83B SHTDN = GND and wait for 250 ns.
4. Disable the video output of the video source.
5. Remove power from the LCD panel for the lowest system power.
2.4 Signal Connectivity
While there is no formal, industrial standardization for the input interface of LVDS LCD panels, over the
years the industry has aligned a specific data bit order format. Figure 5 through Figure 9 show how each
signal must be connected from the graphic source through the SN75LVDS83B input/output and LVDS
LCD panel input.
The outputs are available at J1 to J10 for direct connection to oscilloscope inputs. Matched length cables
must be used when connecting the EVM to a scope to avoid inducing skew between the noninverting (+)
and inverting (-) outputs.
Power jacks P1 to P4 are used to provide power, ground, and signal ground reference for the EVM. The
power connections to the EVM determine the common-mode load to the device, because LVDS drivers
have limited common-mode driver capability. When connecting the EVM outputs directly to oscilloscope
inputs, setting the common-mode offset voltage of the oscilloscope is required, because it presents low
common-mode load impedance to the device.
In Figure 5 through Figure 9, the power supply is used to provide the required 3.3 V to the EVM.
Additionally, the signal ground input from the power supply is used to offset the EVM ground relative to the
DUT ground. Obtain optimum device setup by adjusting the signal ground voltage on the power supply
until its current is minimized. It is important to note that use of the dual supplies and offsetting the EVM
ground relative to the DUT ground are simply steps needed for the test and evaluation of devices. Actual
designs would include receivers 100-Ωtermination resistor across each differential input while keeping a
high-impedance between each RX input signal and GND, which would not require the setup steps
previously outlined.

CLKIN CLKSEL
DUT_GND SHTDN
DUT_GND
Power Supply
GND
1p8V
2p5V
3p3V 1p2V 3p3V
VCCIO DUT_GND SIGNAL_GND VCC
1p8V
2p5V
3p3V
3p3V
P1 P2 P3 P4
LVDS83BTSSOPEVM
INT061A
SIGNAL_GND
DUT_GND
Y2M
J6
Y0P
J9
Y1M
J8
J7
JMP6
U1
PIN1
D19
D20
D21
D22
D24
D25
D26
D8
D9
D12
D13
D14
D15
D18
JMP4
JMP3
JMP2
JMP1
D0
D1
D2
D3
D4
D6
D7
D27
D5
D10
D11
D16
D17
D23
SIGNAL_GNDSIGNAL_GND
SIGNAL_GNDSIGNAL_GND
JMP7 JMP8
Y0M
J10
Y2P
J5
CLKINM
J2
Y3M
J4
Y3P
J3
CLKINP
J1
Y1P
24bpp LCD Display
FPC Cable
LVDS
Timing
Controller
(8bpc, 24bpp)
Notes:
Current setup uses rising edge triggered clocking. If
rising edge triggered clocking is desired, place jumper
to create LOW level input at JMP7.
100
ToColumnDriver
Panel Connector
Main Board Connector
100
100
100
100
ToRowDriver
24-bpcGPU
R0(LSB)
R1
R2
R3
R4
R5
R6
R7(MSB)
G0(LSB)
G1
G2
G3
G4
G5
G6
G7(MSB)
HSYNC
VSYNC
ENABLE
RSVD
CLK
B0(LSB)
B1
B2
B3
B4
B5
B6
B7(MSB)
C1
C3
C4
C5
C10
C9
C8
C7
C6 C11
C12
C13
C14
C15
C2
R2
R1
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This configuration is most popular for 24-bit panels.
Figure 5. 24-Bit Color Host to 24-Bit LCD Panel Application
With 2 MSB Transfer Over Fourth Data Channel

CLKSEL
DUT_GND SHTDN
DUT_GND
Power Supply
GND
1p8V
2p5V
3p3V 1p2V 3p3V
VCCIO DUT_GND SIGNAL_GND VCC
1p8V
2p5V
3p3V
3p3V
P1 P2 P3 P4
LVDS83BTSSOPEVM
INT061A
SIGNAL_GND
DUT_GND
Y2M
J6
Y0P
J9
Y1M
J8
J7
JMP6
U1
PIN1
JMP7 JMP8
Y0M
J10
Y2P
J5
CLKINM
J2
Y3M
J4
Y3P
J3
CLKINP
J1
Y1P
24bpp LCD Display
FPC Cable
LVDS
Timing
Controller
(8bpc, 24bpp)
Notes:
Current setup uses rising edge triggered clocking. If
rising edge triggered clocking is desired, place jumper
to create LOW level input at JMP7.
100
ToColumnDriver
Panel Connector
Main Board Connector
100
100
100
100
ToRowDriver
24-bpcGPU
R0(LSB)
R1
R2
R3
R4
R5
R6
R7(MSB)
G0(LSB)
G1
G2
G3
G4
G5
G6
G7(MSB)
HSYNC
VSYNC
ENABLE
RSVD
CLK
B0(LSB)
B1
B2
B3
B4
B5
B6
B7(MSB)
CLKIN
D19
D20
D21
D22
D24
D25
D26
D8
D9
D12
D13
D14
D15
D18
JMP4
JMP3
JMP2
JMP1
D0
D1
D2
D3
D4
D6
D7
D27
D5
D10
D11
D16
D17
D23
SIGNAL_GNDSIGNAL_GND
SIGNAL_GNDSIGNAL_GND
C1
C3
C4
C5
C10
C9
C8
C7
C6 C11
C12
C13
C14
C15
C2
R2
R1
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This configuration is fairly uncommon.
Figure 6. 24-Bit Color Host to 24-Bit LCD Panel Application
With 2 LBS Transfer Over Fourth Data Channel

CLKSEL
DUT_GND SHTDN
DUT_GND
Power Supply
GND
1p8V
2p5V
3p3V 1p2V 3p3V
VCCIO DUT_GND SIGNAL_GND VCC
1p8V
2p5V
3p3V
3p3V
P1 P2 P3 P4
LVDS83BTSSOPEVM
INT061A
SIGNAL_GND
DUT_GND
Y2M
J6
Y0P
J9
Y1M
J8
J7
U1
PIN1
JMP7 JMP8
Y0M
J10
Y2P
J5
CLKINM
J2
Y3M
J4
Y3P
J3
CLKINP
J1
Y1P
LVDS
Timing
Controller
(8bpc, 18bpp)
Notes:
Current setup uses rising edge triggered clocking. If
rising edge triggered clocking is desired, place jumper
to create LOW level input at JMP7.
100
Panel Connector
Main Board Connector
100
100
100
18-bpcGPU
R0(LSB)
R1
R2
R3
R4
R5(MSB)
G0(LSB)
G1
G2
G3
G4
G5(MSB)
HSYNC
VSYNC
ENABLE
RSVD
CLK
B0(LSB)
B1
B2
B3
B4
B5(MSB) 24bpp LCD Display
FPC Cable
ToColumnDriver
ToRowDriver
CLKIN
D19
D20
D21
D22
D24
D25
D26
D8
D9
D12
D13
D14
D15
D18
JMP4
JMP3
JMP2
JMP1
D0
D1
D2
D3
D4
D6
D7
D27
D5
D10
D11
D16
D17
D23
SIGNAL_GNDSIGNAL_GND
SIGNAL_GNDSIGNAL_GND
C1
C3
C4
C5
C10
C9
C8
C7
C6 C11
C12
C13
C14
C15
C2
R2
R1
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Figure 7. 18-Bit Color Host to 18-Bit LCD Panel Application

CLKSEL
DUT_GND SHTDN
DUT_GND
Power Supply
GND
1p8V
2p5V
3p3V 1p2V 3p3V
VCCIO DUT_GND SIGNAL_GND VCC
1p8V
2p5V
3p3V
3p3V
P1 P2 P3 P4
LVDS83BTSSOPEVM
INT061A
SIGNAL_GND
DUT_GND
Y2M
J6
Y0P
J9
Y1M
J8
J7
U1
PIN1
JMP7 JMP8
Y0M
J10
Y2P
J5
CLKINM
J2
Y3M
J4
Y3P
J3
CLKINP
J1
Y1P
LVDS
Timing
Controller
(6bpc, 18bpp)
Notes:
Current setup uses rising edge triggered clocking. If rising edge triggered
clocking is desired, place jumper to create LOW level input at JMP7.
Leave output Y3 NC (No Connection).
*R3, G3, and B3 are MSB that may be connected to the 5th bit of each color
increased dynamics range of entire color space at the expense of non-
linear step sizes between each step. For linear steps with less dynamic
range, connect D1, D8, and D18 to GND.
*R32 G2, and B2 may be connected to the LSB of each color increased
dynamics range of entire color space at the expense of non-linear step
sizes between each step. For linear steps with less dynamic range,
connect D0, D7, and D15 to VCC.
100
Panel Connector
Main Board Connector
100
100
100
12-bpcGPU
R2orVcc*
R3orGND*
R0(LSB)
R1
R2
R3(MSB)
G2orVcc*
G3orGND*
G0(LSB)
G1
G2
G3(MSB)
HSYNC
VSYNC
ENABLE
RSVD
CLK
B2orVcc*
B3orGND*
B0(LSB)
B1
B2
B3(MSB) 24bpp LCD Display
FPC Cable
ToColumnDriver
ToRowDriver
CLKIN
D19
D20
D21
D22
D24
D25
D26
D8
D9
D12
D13
D14
D15
D18
JMP4
JMP3
JMP2
JMP1
D0
D1
D2
D3
D4
D6
D7
D27
D5
D10
D11
D16
D17
D23
SIGNAL_GNDSIGNAL_GND
SIGNAL_GNDSIGNAL_GND
C1
C3
C4
C5
C10
C9
C8
C7
C6 C11
C12
C13
C14
C15
C2
R2
R1
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Figure 8. 12-Bit Color Host to 18-Bit LCD Panel Application

24-bpcGPU
R0(LSB)
R1
R2
R3
R4
R5
R6
R7(MSB)
G0(LSB)
G1
G2
G3
G4
G5
G6
G7(MSB)
HSYNC
VSYNC
ENABLE
RSVD
CLK
B0(LSB)
B1
B2
B3
B4
B5
B6
B7(MSB)
CLKSEL
DUT_GND SHTDN
DUT_GND
Power Supply
GND
1p8V
2p5V
3p3V 1p2V 3p3V
VCCIO DUT_GND SIGNAL_GND VCC
1p8V
2p5V
3p3V
3p3V
P1 P2 P3 P4
LVDS83BTSSOPEVM
INT061A
SIGNAL_GND
DUT_GND
Y2M
J6
Y0P
J9
Y1M
J8
J7
U1
PIN1
JMP7 JMP8
Y0M
J10
Y2P
J5
CLKINM
J2
Y3M
J4
Y3P
J3
CLKINP
J1
Y1P
LVDS
Timing
Controller
(6bpc, 18bpp)
100
Panel Connector
Main Board Connector
100
100
100
24bpp LCD Display
FPC Cable
ToColumnDriver
ToRowDriver
CLKIN
D19
D20
D21
D22
D24
D25
D26
D8
D9
D12
D13
D14
D15
D18
JMP4
JMP3
JMP2
JMP1
D0
D1
D2
D3
D4
D6
D7
D27
D5
D10
D11
D16
D17
D23
SIGNAL_GNDSIGNAL_GND
SIGNAL_GNDSIGNAL_GND
Notes:
Current setup uses rising edge triggered clocking. If rising edge triggered
clocking is desired, place jumper to create LOW level input at JMP7.
Leave output Y3 NC (No Connection).
R0, R1, G0, G1, B0 and B1 are for improved image quality purposes. The
GPU should dither 24-bit output pixel down to 18-bit per pixel.
C1
C3
C4
C5
C10
C9
C8
C7
C6 C11
C12
C13
C14
C15
C2
R2
R1
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Figure 9. 24-Bit Color Host to 18-Bit LCD Panel Application
3 PCB Construction
This section discusses the construction of the LVDS83BTSSOPEVM boards. The section includes the
board layers to show how the board was built.
3.1 LVDS83BTSSOPEVM Board Layout
This EVM was designed to show the implementation of the SN75LVDS83B device on a 6-layer board.
The pin assignments of the input ports of the SN75LVDS83B device are optimized for the PCB mount of
the GPU connector. This allows easy routing of the traces and a minimal number of vias to preserve good
signal integrity. Every effort was made to keep the routing as clean as possible to the GPU connectors.
The board was designed to maintain 50 Ωto GND single-ended impedance for each individual trace. This
design uses FR4 – TurboClad 370 material with the board stack up shown in Figure 18, and requires the
traces to be 9.25 mil wide and 5 mils above the GND reference plane. A minimum spacing of 3 times the
trace width was maintained to all other components to prevent unwanted coupling.
A differential routing scheme that creates 100-Ωimpedance between the differential traces could have
also been implemented equally as well with this device.

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Figure 10. LVDS83BTSSOPEVM Top Layer

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Figure 11. LVDS83BTSSOPEVM Layer 2 – GND

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Figure 12. LVDS83BTSSOPEVM Layer 3 – DUT GND

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Figure 13. LVDS83BTSSOPEVM Layer 4 – VCC

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Figure 14. LVDS83BTSSOPEVM Layer 5 – GND

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Figure 15. LVDS83BTSSOPEVM Bottom Layer

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4 LVDS83BTSSOPEVM Bill of Materials
Table 1 lists the LVDS83BTSSOPEVM BOM.
Table 1. BOM
Item QTY Value Part Manufacturer Manufacture Part Number PCB Footprint Description
1 4 10000 pF C22, C25, C19,
C16 Samsung CL05B103KP5NNNC CC0402 10000 pF, ±10%, 10 V, ceramic capacitor X7R, 0402 (1005 metric)
2 4 0.1 µF C21, C24, C27,
C17 Murata GRM155R61A104KA01D CC0402 0.1 µF, ±10%, 10 V, ceramic capacitor X5R, 0402 (1005 metric)
3 4 1.0 µF C20, C23, C26,
C18 Murata GRM155R61A105KE15D CC0402 1 µF, ±10% 10 V, ceramic capacitor X5R, 0402 (1005 metric)
4 3 10000 pF C5, C10, C15 Würth Electronics 885012207011 CC0805 10000 pF, ±10%, 10 V, ceramic capacitor X7R,
0805 (2012 metric)
5 3 0.1 µF C4, C9, C14 Würth Electronics 885012208009 CC1206 0.1 µF, ±10%, 10 V, ceramic capacitor X7R, 1206
(3216 metric)
6 3 1.0 µF C3, C8, C13 KEMET C1206C105K4RACTU CC1206 1 µF, ±10%, 16 V, ceramic capacitor X7R, 1206
(3216 metric)
7 3 10 µF C2, C7, C12 KEMET C0805C106K8PACTU CC7343 10 µF, ±10%, 10 V, ceramic capacitor X5R, 0805
(2012 metric)
8 3 68 µF -
LESR C1, C6, C11 TDK C3216X5R0J686M160AB CC7343 68 µF, ±20%, 6.3 V, ceramic capacitor X5R, 1206 (3216 metric)
9 2 0.0 ΩR3, R4 Panasonic - Ecg ERJ-3GEY0R00V R0603 0.0-Ωjumper, 0.1 W, 1/10W, chip resistor 0603
(1608 metric), automotive AEC-Q200 thick film
10 2 4.75 KΩR2, R1 Yageo RC0603FR-074K75L R0603 4.75-kΩ, ±1%, 0.1 W, 1/10W, chip resistor, 0603
(1608 metric) moisture resistant thick film
11 1 SN75LVDS
83B U1 Texas Instruments SN75LVDS83B 56-TSSOP IC FlatLink XMITTER 56TSSOP
12 4 2 × 7 JMP1, JMP2,
JMP3, JMP4 Harwin M22-2520705 0.1 × 0.1" 14-position header, cuttable connector 0.079" (2.00 mm) through hole gold
13 4 1 × 2 JMP5, JMP7,
JMP8, JMP6 Harwin M20-9990546 0.1 × 0.1" 5-position header, cuttable connector 0.100" (2.54 mm) through hole tin
14 4 Banana Jack -
Metal P1, P2, P3, P4 Cinch Connectivity
Solutions Johnson
Power Co 108-0740-001 BJACK Connector, Jack Banana UNINS Panel MOU
15 10 Jack J10, J9, J8, J7, J6, J5, J4, J3,
J2, J1 Rosenberger 32K141-40ML5 32K141-40M-
FR4WVIA_2LAYER RF connectors / coaxial connectors SMA straight jack PCB
16 4 Round
Spacer Standoffs Keystone Electronics 885 – Round spacer #6 NYLON 3/8"
17 4 4 - 40 /
0.25 Screws B&F Fastener Supply PMSSS 440 0025 PH Building Fasteners Machine screw pan Phillips 4 – 40

VCCIO
VCC
VCCIO
VCC
VCC
VCC
C4
.1uF
C10
.01uF
C22
.01uF
C14
.1uF
C15
.01uF
R3
0
P3
Banana-Jack
1
C6
68uF
U1D
SN75LVDS83B
Vcc
9
Vccio1
1
Vccio2
26
LVDSVcc 44
PLLVcc 34
C20
1uF
C3
1uF
C23
1uF
C12
10uF
C9
.1uF
C7
10uF
C24
.1uF
C25
.01uF
C11
68uF
C8
1uF
C21
.1uF
C18
1uF
C17
.1uF
JMP6
1
2
C13
1uF
C16
.01uF
U1C
SN75LVDS83B
GND1
5
GND2
13
GND3
21
GND4
29
GND5
53 PLLGND2 35
PLLGND1 33
LVDSGND3 49
LVDSGND2 43
LVDSGND1 36
P1
Banana-Jack
1
C26
1uF
P4
Banana jack
1
P2
Banana-Jack
1
C27
.1uF
C2
10uF
C5
.01uF
C1
68uF
C19
.01uF
R4
0
Copyright © 2017, Texas Instruments Incorporated
VCC and Bulk Bypass Capacitors
Signal Ground and Bulk Bypass Capacitor
Device Ground
VCCIO and Bulk Bypass Capacitors
Short to JMP9 to short
VCC = 3.3 V
GND_SIGNAL to GND_POWER
LVDS83BTSSOPEVM Schematics www.ti.com
18 SNLU233–October 2017
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Copyright © 2017, Texas Instruments Incorporated
LVDS83BTSSOPEVM User’s Guide
5 LVDS83BTSSOPEVM Schematics
Figure 16,Figure 17, and Figure 18 show the LVDS83BTSSOPEV schematics.
Figure 16. LVDS83BTSSOPEVM Schematics (1/3)

VCC
VCC
JMP4
Header 7x2
1
3
5
7
9
2
4
6
8
10
11 12
13 14
JMP2
Header 7x2
1
3
5
7
9
2
4
6
8
10
11 12
13 14
JMP7
1
2
JMP3
Header 7x2
1
3
5
7
9
2
4
6
8
10
11 12
13 14
U1E
SN75LVDS83B
CLKSEL
17
/SHTDN
32
R1
4.7k
R2
4.7k
JMP5
1
2
JMP8
1
2
JMP1
Header 7x2
1
3
5
7
9
2
4
6
8
10
11 12
13 14
U1B
SN75LVDS83B
D8
6
D9
7
D0
51
D1
52
D2
54
D3
55
D4
56
D6
3
D7
4
D12
11
D13
12
D14
14
D15
15
D18
19
D19
20
D20
22
D21
23
D22
24
D24
27
D25
28
D26
30
D27
50
D5
2
D10
8
D11
10
D16
16
D17
18
D23
25
CLKIN
31
Copyright © 2017, Texas Instruments Incorporated
VCC = 3.3 V
Clock Edge Select
Jumper high for rising edge
Jumper low for falling edge
Jumper high to enable device
Jumper low to disable device
www.ti.com LVDS83BTSSOPEVM Schematics
19
SNLU233–October 2017
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LVDS83BTSSOPEVM User’s Guide
Figure 17. LVDS83BTSSOPEVM Schematics (2/3)

Channel 0 to 3
SMA SURFACE
J5
sma_surface
SMA SURFACE
J10
sma_surface
SMA SURFACE
J9
sma_surface
SMA SURFACE
J2
sma_surface
SMA SURFACE
J3
sma_surface
SMA SURFACE
J1
sma_surface
SMA SURFACE
J4
sma_surface
SMA SURFACE
J7
sma_surface
SMA SURFACE
J8
sma_surface
SMA SURFACE
J6
sma_surface
U1A
SN75LVDS83B
Y0M 48
Y0P 47
Y2P 41
42
Y2M
Y1P 45
Y3M 38
Y3P 37
CLKOUTM 40
CLKOUTP 39
Y1M 46
Copyright © 2017, Texas Instruments Incorporated
LVDS83BTSSOPEVM Schematics www.ti.com
20 SNLU233–October 2017
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Copyright © 2017, Texas Instruments Incorporated
LVDS83BTSSOPEVM User’s Guide
Figure 18. LVDS83BTSSOPEVM Schematic (3/3)