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CC1150
SWRS037B –JANUARY 2006–REVISED MARCH 2015
CC1150 Low Power Sub-1 GHz RF Transmitter
1 Device Overview
1.1 Features
1
• Small Size • 64-byte TX Data FIFO
– QLP 4-mm × 4-mm Package, 16 Pins • Suited for Systems Compliant with EN 300 220
and FCC CFR Part 15
• True Single Chip UHF RF Transmitter • Many Powerful Digital Features Allow a High-
• Frequency Bands performance RF system to be made Using an
– 300 to 348 MHz Inexpensive Microcontroller
– 400 to 464 MHz • Efficient SPI interface: All Registers Can be
– 800 to 928 MHz Programmed With One "Burst" Transfer
• Programmable Data Rate Up to 500 kBaud • Integrated Analog Temperature Sensor
• Low Current Consumption • Lead-free “Green” Package
• Programmable Output Power Up to +10 dBm for • Flexible Support for Packet Oriented Systems
All Supported Frequencies – On-chip Support for Sync-Word Insertion,
• Programmable Baseband Modulator Flexible Packet Length and Automatic CRC
• Ideal For Multi-channel Operation Handling
• Very Few External Components • OOK and Flexible ASK Shaping Supported
– Completely On-chip Frequency Synthesizer • 2-FSK, GFSK and MSK Supported
– No External Filters Needed • Optional Automatic Whitening of Data
• Configurable Packet Handling Hardware • Support for Asynchronous Transparent Transmit
• Suitable for Frequency Hopping Systems Due to a Mode for Backwards Compatibility with Existing
Fast Settling Frequency Synthesizer Radio Communication Protocols
• Optional Forward Error Correction with Interleaving
1.2 Applications
• Ultra-low Power UHF Wireless Transmitters • Low Power Telemetry
• Operating in the 315-, 433-, 868-, and 915-MHz • Home and Building Automation
ISM/SRD bands • Wireless Alarm and Security Systems
• AMR – Automatic Meter Reading • Industrial Monitoring and Control
• Consumer Electronics • Wireless Sensor Networks
• RKE – Remote Keyless Entry
1.3 Description
The CC1150 is a true single-chip UHF transmitter designed for very low power wireless applications. The
circuit is mainly intended for the ISM (Industrial, Scientific and Medical) and SRD (Short Range Device)
frequency bands at 315-, 433-, 868-, and 915-MHz, but can easily be programmed for operation at other
frequencies in the 300 to 348 MHz, 400 to 464 MHz and 800 to 928 MHz bands.
The RF transmitter is integrated with a highly configurable baseband modulator. The modulator supports
various modulation formats and has a configurable data rate up to 500 kBaud. The CC1150 device
provides extensive hardware support for packet handling, data buffering and burst transmissions.
The main operating parameters and the 64-byte transmit FIFO of CC1150 can be controlled via an SPI
interface. In a typical system, the CC1150 device will be used together with a microcontroller and a few
additional passive components.
CC1150 is part of the SmartRF™ technology platform based on 0.18-μm CMOS technology from Texas
Instruments.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

BIAS
XOSC_Q1 XOSC_Q2
XOSC
FREQ
SYNTH
RADIO CONTROL
RF_P
RF_N
CSn
SI
SO (GDO1)
SCLK
GDO0 (ATEST)
RBIAS
PA
FEC /
INTERLEAVER
PACKET
HANDLER
MODULATOR
TX FIFO
DIGITAL
INTERFACE
TO MCU
CC1150
SWRS037B –JANUARY 2006–REVISED MARCH 2015 www.ti.com
Table 1-1. Device Information(1)
PART NUMBER PACKAGE BODY SIZE
CC1150 VQFNP (16) 4.00 mm × 4.00 mm
(1) For more information, see Section 8,Mechanical Packaging and Orderable Information.
1.4 Functional Block Diagram
2Device Overview Copyright © 2006–2015, Texas Instruments Incorporated
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Table of Contents
1 Device Overview ......................................... 15.7 Data Rate Programming ............................ 18
1.1 Features .............................................. 15.8 Packet Handling Hardware Support................. 19
1.2 Applications........................................... 15.9 Modulation Formats ................................. 23
1.3 Description............................................ 15.10 Forward Error Correction with Interleaving.......... 24
1.4 Functional Block Diagram ............................ 25.11 Radio Control........................................ 26
2 Revision History ......................................... 45.12 Data FIFO........................................... 29
3 Terminal Configuration and Functions.............. 55.13 Frequency Programming ........................... 31
3.1 Pin Attributes ......................................... 55.14 VCO ................................................. 31
4 Specifications ............................................ 65.15 Voltage Regulators.................................. 32
4.1 Absolute Maximum Ratings .......................... 65.16 Output Power Programming......................... 32
4.2 ESD Ratings.......................................... 65.17 General Purpose and Test Output Control Pins .... 33
4.3 Recommended Operating Conditions................ 65.18 Asynchronous and Synchronous Serial Operation.. 35
4.4 General Characteristics .............................. 65.19 System Considerations and Guidelines............. 36
4.5 Current Consumption................................. 75.20 Memory.............................................. 38
4.6 RF Transmit .......................................... 76 Applications, Implementation, and Layout........ 51
4.7 Crystal Oscillator ..................................... 86.1 Application Information.............................. 51
4.8 Frequency Synthesizer Characteristics .............. 86.2 Design Requirements ............................... 53
4.9 Analog Temperature Sensor ......................... 96.3 PCB Layout Recommendations..................... 55
4.10 DC Characteristics ................................... 97 Device and Documentation Support ............... 58
4.11 Power-On Reset .................................... 10 7.1 Device Support...................................... 58
4.12 Thermal Resistance Characteristics for VQFNP 7.2 Documentation Support ............................. 58
Package ............................................. 10 7.3 Trademarks.......................................... 59
5 Detailed Description ................................... 11 7.4 Electrostatic Discharge Caution..................... 59
5.1 Overview ............................................ 11 7.5 Export Control Notice ............................... 59
5.2 Functional Block Diagram........................... 11 7.6 Glossary............................................. 59
5.3 Configuration Overview ............................. 11 8 Mechanical Packaging and Orderable
5.4 Configuration Software.............................. 12 Information .............................................. 59
5.5 4-wire Serial Configuration and Data Interface ..... 13 8.1 Packaging Information .............................. 59
5.6 Microcontroller Interface and Pin Configuration..... 17
Copyright © 2006–2015, Texas Instruments Incorporated Table of Contents 3
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SWRS037B –JANUARY 2006–REVISED MARCH 2015 www.ti.com
2 Revision History
This data manual revision history highlights the changes made to the SWRS037A device-specific data
manual to make it an SWRS037B revision.
Changes from January 1, 2006 to February 19, 2015 Page
• Updated RST package to RGV. .................................................................................................. 58
4Revision History Copyright © 2006–2015, Texas Instruments Incorporated
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GND
Exposed die
attach pad
5
XOSC_Q1
6
AVDD
7
XOSC_Q2
8
GDO0 (ATEST)
9 CSn
10 RF_P
11 RF_N
12 AVDD
13
AVDD
14
RBIAS
15
DGUARD
16
SI
1SCLK
2SO (GDO1)
3DVDD
4DCOUPL
CC1150
www.ti.com SWRS037B –JANUARY 2006–REVISED MARCH 2015
3 Terminal Configuration and Functions
The CC1150 pinout is shown in Figure 3-1 and Table 3-1
Figure 3-1. Pinout Top View
3.1 Pin Attributes
Table 3-1. Pin Attributes(1)
PIN NO. PIN NAME TYPE DESCRIPTION
1 SCLK Digital Input Serial configuration interface, clock input.
Serial configuration interface, data output.
2 SO (GDO1) Digital Output Optional general output pin when CSn is high.
1.8-V to 3.6-V digital power supply for digital I/Os and for the digital
3 DVDD Power (Digital) core voltage regulator.
4 DCOUPL(2) Power (Digital) 1.6-V to 2.0-V digital power supply output for decoupling.
5 XOSC_Q1 Analog I/O Crystal oscillator pin 1, or external clock input.
6 AVDD Power (Analog) 1.8-V to 3.6-V analog power supply connection.
7 XOSC_Q2 Analog I/O Crystal oscillator pin 2.
Digital output pin for general use:
• Test signals
GDO0 • FIFO status signals
8 Digital I/O
(ATEST) • Clock output, down-divided from XOSC
• Serial input TX data
Also used as analog test I/O for prototype/production testing.
9 CSn Digital Input Serial configuration interface, chip select.
10 RF_P RF I/O Positive RF output signal from PA.
11 RF_N RF I/O Negative RF output signal from PA.
12 AVDD Power (Analog) 1.8-V to 3.6-V analog power supply connection.
13 AVDD Power (Analog) 1.8-V to 3.6-V analog power supply connection.
14 RBIAS Analog I/O External bias resistor for reference current.
15 DGUARD Power (Digital) Power supply connection for digital noise isolation.
16 SI Digital Input Serial configuration interface, data input.
(1) The exposed die attach pad must be connected to a solid ground plane as this is the main ground connection for the chip.
(2) This pin is intended for use with the CC1150 only. It can not be used to provide supply voltage to other devices.
Copyright © 2006–2015, Texas Instruments Incorporated Terminal Configuration and Functions 5
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4 Specifications
4.1 Absolute Maximum Ratings(1)(2)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT CONDITION
All supply pins must have the same
Supply voltage –0.3 3.6 V voltage
Voltage on any digital pin –0.3 VDD + 0.3, max 3.6 V
Voltage on the pins RF_P, RF_N and –0.3 2.0 V
DCOUPL
Voltage ramp-up 120 kV/µs
Input RF level +10 dBm
Storage temperature range, Tstg –50 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
4.2 ESD Ratings
VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) < 500
V(ESD) Electrostatic discharge V
Charged-device model (CDM) 250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) According to JEDEC STD 22, method A114, Human Body Model
4.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT CONDITION
Operating temperature –40 85 °C All supply pins must have the same
Operating supply voltage 1.8 3.6 V voltage
4.4 General Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT CONDITION
300 348 MHz
Frequency range 400 464 MHz
800 928 MHz
1.2 500 kBaud 2-FSK
1.2 250 kBaud GFSK, OOK and ASK
(Shaped) MSK (also known as
Data rate differential offset QPSK)
26 500 kBaud Optional Manchester encoding (the
data rate in kbps will be half the
baud rate)
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4.5 Current Consumption
Tc= 25°C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1150EM reference design
(see [1] and [2]).
PARAMETER TYP UNIT CONDITION
200 nA Voltage regulator to digital part off, register values lost (SLEEP state)
Voltage regulator to digital part on, all other modules in power down
222 µA (XOFF state)
Only voltage regulator to digital part and crystal oscillator running
1.1 mA
Current consumption (IDLE state)
Only the frequency synthesizer running (FSTXON state). This
current consumption also representative for the other intermediate
7.7 mA states when going from IDLE until reaching TX, and frequency
calibration states
25.6 mA Transmit mode, +10 dBm output power (0xC4)
Current consumption, 315 MHz 14.1 mA Transmit mode, 0 dBm output power (0x60)
See more in Section 5.16 and DN012 [3].
26.1 mA Transmit mode, +10 dBm output power (0xC2)
Current consumption, 433 MHz 14.6 Transmit mode, 0 dBm output power (0x60)
See more in Section 5.16 and DN012 [3].
29.3 mA Transmit mode, +10 dBm output power (0xC3)
Current consumption, 868 MHz 15.5 Transmit mode, 0 dBm output power (0x60)
See more in Section 5.16 and DN012 [3].
29.3 mA Transmit mode, +10 dBm output power (0xC0)
Current consumption, 915 MHz 15.2 mA Transmit mode, 0 dBm output power (0x50)
See more in Section 5.16 and DN012 [3].
4.6 RF Transmit
Tc= 25°C, VDD = 3.0 V, if nothing else stated. All measurement results are obtained using the CC1150EM reference design
(see [1] and [2]). PARAMETER TYP MAX UNIT CONDITION
315 MHz 122 + j31 ΩDifferential impedance as seen from the RF-
Differential load 433 MHz 116 + j41 Ωport (RF_P and RF_N) towards the antenna.
impedance Follow the CC1150EM reference design
86.5 +
868/915 MHz Ω(see [1] and [2]).
j43 Output power is programmable, and full
range is available across all frequency
bands. Output power may be restricted by
regulatory limits. See also
DN006 [5].
Delivered to a 50-Ωsingle-ended load via
Output power, highest setting +10 dBm CC1150 EM reference design (see [1] and
[2]) RF matching network. Maximum output
power can be increased 1 to 2 dB by using
wire-wound inductors instead of multilayer
inductors in the balun and filter circuit for the
868/915 MHz band, see more in DN017 [6].
Output power is programmable, and full
range is available across all frequency
bands.
Output power, lowest setting –30 dBm Delivered to a 50 Ωsingle-ended load via
CC1150 EM reference design (see [1] and
[2]) RF matching network.
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RF Transmit (continued)
Tc= 25°C, VDD = 3.0 V, if nothing else stated. All measurement results are obtained using the CC1150EM reference design
(see [1] and [2]). PARAMETER TYP MAX UNIT CONDITION
25 MHz to 1 GHz –36 dBm
Spurious 47 to 74 MHz,
emissions and 87.5 to 118 MHz, –54 dBm
harmonics(1), 174 to 230 MHz,
433/868 MHz 470 to 862 MHz
Otherwise above 1 GHz –30 dBm
< 200 µV/m at 3 m below dBm
–49.2
960 MHz EIRP
Spurious emissions,
315/915 MHz < 500 µV/m at 3 m above dBm
–41.2
960 MHz EIRP Whe output power is maximum
2nd, 3rd and 4th harmonic –20 dBc 6 mV/m at 3 m (–19.6 dBm EIRP)
Harmonics 315 MHz 5th harmonic –41.2 dBm
2nd harmonic –20 dBc With +10 dBm output power
Harmonics 915 MHz 3rd, 4th, and 5th harmonic –41.2 dBm Serial operation. Time from sampling the
TX latency 8 Bits data on the transmitter data input pin until it
is observed on the RF output ports.
(1) Note that close-in spurs vary with centre frequency and limits the frequencies and output power level which the CC1150 can operate at
without violating regulatory restrictions. See also Section 6.2.5 for information regarding additional filtering.
4.7 Crystal Oscillator
Tc= 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1150EM reference design
(see [1] and [2]).
PARAMETER MIN TYP MAX UNIT CONDITION
Crystal frequency 26 26 27 MHz This is the total tolerance including a) initial
tolerance, b) aging and c) temperature
dependence.
Tolerance ±40 ppm The acceptable crystal tolerance depends on
RF frequency and channel spacing /
bandwidth
Load capacitance 10 13 20 pF Simulated over operating conditions
ESR 100 Ω
Measured on the CC1150EM reference
Start-up time 150 µs design (see [1] and [2]). This parameter is to
a large degree crystal dependent.
4.8 Frequency Synthesizer Characteristics
Tc= 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1150EM reference design
(see [1] and [2]).
PARAMETER MIN TYP MAX UNIT CONDITION
Programmed frequency 26 MHz to 27 MHz crystals. The resolution
397 FXOSC / 216 412 Hz
resolution (in Hz) is equal for all frequency bands.
Given by crystal used. Required accuracy
(including temperature and aging) depends
Synthesizer frequency tolerance ±40 ppm on frequency band and channel bandwidth /
spacing.
@ 50 kHz offset from carrier,
RF carrier phase noise –82 dBc/Hz carrier at 868 MHz
@ 100 kHz offset from carrier,
RF carrier phase noise –86 dBc/Hz carrier at 868 MHz
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Frequency Synthesizer Characteristics (continued)
Tc= 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1150EM reference design
(see [1] and [2]).
PARAMETER MIN TYP MAX UNIT CONDITION
@ 200 kHz offset from carrier,
RF carrier phase noise –90 dBc/Hz carrier at 868 MHz
@ 500 kHz offset from carrier,
RF carrier phase noise –98 dBc/Hz carrier at 868 MHz
@ 1 MHz offset from carrier,
RF carrier phase noise –106 dBc/Hz carrier at 868 MHz
@ 2 MHz offset from carrier,
RF carrier phase noise –113 dBc/Hz carrier at 868 MHz
@ 5 MHz offset from carrier,
RF carrier phase noise –119 dBc/Hz carrier at 868 MHz
@ 10 MHz offset from carrier,
RF carrier phase noise –127 dBc/Hz carrier at 868 MHz
Time from leaving the IDLE state until
arriving in the FSTXON or TX state, when
PLL turn-on / hop time 85.1 88.4 88.4 µs not performing calibration.
Crystal oscillator running.
Calibration can be initiated manually or
XOSC
18739 automatically before entering or after leaving
cycles TX.
PLL calibration time Min/typ/max time is for 27/26/26 MHz crystal
694 721 721 µs frequency.
4.9 Analog Temperature Sensor(1)
Tc= 25°C, VDD = 3.0 V if nothing else is stated.
PARAMETER MIN TYP MAX UNIT CONDITION
Output voltage at –40°C 0.651 V
Output voltage at 0°C 0.747 V
Output voltage at +40°C 0.847 V
Output voltage at +80°C 0.945 V
Temperature coefficient 2.45 mV/°C Fitted from –20°C to +80°C
From –20°C to +80°C
when using
Absolute error in calculated temperature –2(2) 2(2) °C 2.45 mV / °C, after 1-point
calibration at room
temperature
Current consumption increase when 0.3 mA
enabled
(1) It is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state.
(2) Indicated minimum and maximum error with 1-point calibration is based on simulated values for typical process parameters
4.10 DC Characteristics
Tc= 25°C if nothing else stated.
DIGITAL INPUTS/OUTPUTS MIN MAX UNIT CONDITION
Logic "0" input voltage 0 0.7 V
Logic "1" input voltage VDD – 0.7 VDD V
Logic "0" output voltage 0 0.5 V For up to 4 mA output current
Logic "1" output voltage VDD – 0.3 VDD V For up to 4 mA output current
Logic "0" input current N/A –1 µA Input equals 0 V
Logic "1" input current N/A 1 µA Input equals VDD
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4.11 Power-On Reset
For proper Power-On-Reset functionality, the power supply must comply with the requirements in this table. Otherwise, the
chip should be assumed to have unknown state until transmitting an SRES strobe over the SPI interface. See Section 5.11.1
for a description of the recommended start-up sequence after turning power on.
PARAMETER MIN TYP MAX UNIT CONDITION
Power up ramp-up time 5 ms From 0 V until reaching 1.8 V
Minimum time between power on and
Power-off time 1 ms power off
4.12 Thermal Resistance Characteristics for VQFNP Package
NAME DESCRIPTION °C/W(1) (2)
RθJC(top) Junction-to-case (top) 54.0
RθJB Junction-to-board 25.1
RθJA Junction-to-free air 48.3
PsiJT Junction-to-package top 1.6
PsiJB Junction-to-board 25.2
RθJC(bottom) Junction-to-case (bottom) 6.3
(1) °C/W = degrees Celsius per watt.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.
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