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CC1150
SWRS037B –JANUARY 2006–REVISED MARCH 2015
CC1150 Low Power Sub-1 GHz RF Transmitter
1 Device Overview
1.1 Features
1
• Small Size • 64-byte TX Data FIFO
– QLP 4-mm × 4-mm Package, 16 Pins • Suited for Systems Compliant with EN 300 220
and FCC CFR Part 15
• True Single Chip UHF RF Transmitter • Many Powerful Digital Features Allow a High-
• Frequency Bands performance RF system to be made Using an
– 300 to 348 MHz Inexpensive Microcontroller
– 400 to 464 MHz • Efficient SPI interface: All Registers Can be
– 800 to 928 MHz Programmed With One "Burst" Transfer
• Programmable Data Rate Up to 500 kBaud • Integrated Analog Temperature Sensor
• Low Current Consumption • Lead-free “Green” Package
• Programmable Output Power Up to +10 dBm for • Flexible Support for Packet Oriented Systems
All Supported Frequencies – On-chip Support for Sync-Word Insertion,
• Programmable Baseband Modulator Flexible Packet Length and Automatic CRC
• Ideal For Multi-channel Operation Handling
• Very Few External Components • OOK and Flexible ASK Shaping Supported
– Completely On-chip Frequency Synthesizer • 2-FSK, GFSK and MSK Supported
– No External Filters Needed • Optional Automatic Whitening of Data
• Configurable Packet Handling Hardware • Support for Asynchronous Transparent Transmit
• Suitable for Frequency Hopping Systems Due to a Mode for Backwards Compatibility with Existing
Fast Settling Frequency Synthesizer Radio Communication Protocols
• Optional Forward Error Correction with Interleaving
1.2 Applications
• Ultra-low Power UHF Wireless Transmitters • Low Power Telemetry
• Operating in the 315-, 433-, 868-, and 915-MHz • Home and Building Automation
ISM/SRD bands • Wireless Alarm and Security Systems
• AMR – Automatic Meter Reading • Industrial Monitoring and Control
• Consumer Electronics • Wireless Sensor Networks
• RKE – Remote Keyless Entry
1.3 Description
The CC1150 is a true single-chip UHF transmitter designed for very low power wireless applications. The
circuit is mainly intended for the ISM (Industrial, Scientific and Medical) and SRD (Short Range Device)
frequency bands at 315-, 433-, 868-, and 915-MHz, but can easily be programmed for operation at other
frequencies in the 300 to 348 MHz, 400 to 464 MHz and 800 to 928 MHz bands.
The RF transmitter is integrated with a highly configurable baseband modulator. The modulator supports
various modulation formats and has a configurable data rate up to 500 kBaud. The CC1150 device
provides extensive hardware support for packet handling, data buffering and burst transmissions.
The main operating parameters and the 64-byte transmit FIFO of CC1150 can be controlled via an SPI
interface. In a typical system, the CC1150 device will be used together with a microcontroller and a few
additional passive components.
CC1150 is part of the SmartRF™ technology platform based on 0.18-μm CMOS technology from Texas
Instruments.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

BIAS
XOSC_Q1 XOSC_Q2
XOSC
FREQ
SYNTH
RADIO CONTROL
RF_P
RF_N
CSn
SI
SO (GDO1)
SCLK
GDO0 (ATEST)
RBIAS
PA
FEC /
INTERLEAVER
PACKET
HANDLER
MODULATOR
TX FIFO
DIGITAL
INTERFACE
TO MCU
CC1150
SWRS037B –JANUARY 2006–REVISED MARCH 2015 www.ti.com
Table 1-1. Device Information(1)
PART NUMBER PACKAGE BODY SIZE
CC1150 VQFNP (16) 4.00 mm × 4.00 mm
(1) For more information, see Section 8,Mechanical Packaging and Orderable Information.
1.4 Functional Block Diagram
2Device Overview Copyright © 2006–2015, Texas Instruments Incorporated
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Table of Contents
1 Device Overview ......................................... 15.7 Data Rate Programming ............................ 18
1.1 Features .............................................. 15.8 Packet Handling Hardware Support................. 19
1.2 Applications........................................... 15.9 Modulation Formats ................................. 23
1.3 Description............................................ 15.10 Forward Error Correction with Interleaving.......... 24
1.4 Functional Block Diagram ............................ 25.11 Radio Control........................................ 26
2 Revision History ......................................... 45.12 Data FIFO........................................... 29
3 Terminal Configuration and Functions.............. 55.13 Frequency Programming ........................... 31
3.1 Pin Attributes ......................................... 55.14 VCO ................................................. 31
4 Specifications ............................................ 65.15 Voltage Regulators.................................. 32
4.1 Absolute Maximum Ratings .......................... 65.16 Output Power Programming......................... 32
4.2 ESD Ratings.......................................... 65.17 General Purpose and Test Output Control Pins .... 33
4.3 Recommended Operating Conditions................ 65.18 Asynchronous and Synchronous Serial Operation.. 35
4.4 General Characteristics .............................. 65.19 System Considerations and Guidelines............. 36
4.5 Current Consumption................................. 75.20 Memory.............................................. 38
4.6 RF Transmit .......................................... 76 Applications, Implementation, and Layout........ 51
4.7 Crystal Oscillator ..................................... 86.1 Application Information.............................. 51
4.8 Frequency Synthesizer Characteristics .............. 86.2 Design Requirements ............................... 53
4.9 Analog Temperature Sensor ......................... 96.3 PCB Layout Recommendations..................... 55
4.10 DC Characteristics ................................... 97 Device and Documentation Support ............... 58
4.11 Power-On Reset .................................... 10 7.1 Device Support...................................... 58
4.12 Thermal Resistance Characteristics for VQFNP 7.2 Documentation Support ............................. 58
Package ............................................. 10 7.3 Trademarks.......................................... 59
5 Detailed Description ................................... 11 7.4 Electrostatic Discharge Caution..................... 59
5.1 Overview ............................................ 11 7.5 Export Control Notice ............................... 59
5.2 Functional Block Diagram........................... 11 7.6 Glossary............................................. 59
5.3 Configuration Overview ............................. 11 8 Mechanical Packaging and Orderable
5.4 Configuration Software.............................. 12 Information .............................................. 59
5.5 4-wire Serial Configuration and Data Interface ..... 13 8.1 Packaging Information .............................. 59
5.6 Microcontroller Interface and Pin Configuration..... 17
Copyright © 2006–2015, Texas Instruments Incorporated Table of Contents 3
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2 Revision History
This data manual revision history highlights the changes made to the SWRS037A device-specific data
manual to make it an SWRS037B revision.
Changes from January 1, 2006 to February 19, 2015 Page
• Updated RST package to RGV. .................................................................................................. 58
4Revision History Copyright © 2006–2015, Texas Instruments Incorporated
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GND
Exposed die
attach pad
5
XOSC_Q1
6
AVDD
7
XOSC_Q2
8
GDO0 (ATEST)
9 CSn
10 RF_P
11 RF_N
12 AVDD
13
AVDD
14
RBIAS
15
DGUARD
16
SI
1SCLK
2SO (GDO1)
3DVDD
4DCOUPL
CC1150
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3 Terminal Configuration and Functions
The CC1150 pinout is shown in Figure 3-1 and Table 3-1
Figure 3-1. Pinout Top View
3.1 Pin Attributes
Table 3-1. Pin Attributes(1)
PIN NO. PIN NAME TYPE DESCRIPTION
1 SCLK Digital Input Serial configuration interface, clock input.
Serial configuration interface, data output.
2 SO (GDO1) Digital Output Optional general output pin when CSn is high.
1.8-V to 3.6-V digital power supply for digital I/Os and for the digital
3 DVDD Power (Digital) core voltage regulator.
4 DCOUPL(2) Power (Digital) 1.6-V to 2.0-V digital power supply output for decoupling.
5 XOSC_Q1 Analog I/O Crystal oscillator pin 1, or external clock input.
6 AVDD Power (Analog) 1.8-V to 3.6-V analog power supply connection.
7 XOSC_Q2 Analog I/O Crystal oscillator pin 2.
Digital output pin for general use:
• Test signals
GDO0 • FIFO status signals
8 Digital I/O
(ATEST) • Clock output, down-divided from XOSC
• Serial input TX data
Also used as analog test I/O for prototype/production testing.
9 CSn Digital Input Serial configuration interface, chip select.
10 RF_P RF I/O Positive RF output signal from PA.
11 RF_N RF I/O Negative RF output signal from PA.
12 AVDD Power (Analog) 1.8-V to 3.6-V analog power supply connection.
13 AVDD Power (Analog) 1.8-V to 3.6-V analog power supply connection.
14 RBIAS Analog I/O External bias resistor for reference current.
15 DGUARD Power (Digital) Power supply connection for digital noise isolation.
16 SI Digital Input Serial configuration interface, data input.
(1) The exposed die attach pad must be connected to a solid ground plane as this is the main ground connection for the chip.
(2) This pin is intended for use with the CC1150 only. It can not be used to provide supply voltage to other devices.
Copyright © 2006–2015, Texas Instruments Incorporated Terminal Configuration and Functions 5
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4 Specifications
4.1 Absolute Maximum Ratings(1)(2)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT CONDITION
All supply pins must have the same
Supply voltage –0.3 3.6 V voltage
Voltage on any digital pin –0.3 VDD + 0.3, max 3.6 V
Voltage on the pins RF_P, RF_N and –0.3 2.0 V
DCOUPL
Voltage ramp-up 120 kV/µs
Input RF level +10 dBm
Storage temperature range, Tstg –50 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
4.2 ESD Ratings
VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) < 500
V(ESD) Electrostatic discharge V
Charged-device model (CDM) 250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) According to JEDEC STD 22, method A114, Human Body Model
4.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT CONDITION
Operating temperature –40 85 °C All supply pins must have the same
Operating supply voltage 1.8 3.6 V voltage
4.4 General Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT CONDITION
300 348 MHz
Frequency range 400 464 MHz
800 928 MHz
1.2 500 kBaud 2-FSK
1.2 250 kBaud GFSK, OOK and ASK
(Shaped) MSK (also known as
Data rate differential offset QPSK)
26 500 kBaud Optional Manchester encoding (the
data rate in kbps will be half the
baud rate)
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4.5 Current Consumption
Tc= 25°C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1150EM reference design
(see [1] and [2]).
PARAMETER TYP UNIT CONDITION
200 nA Voltage regulator to digital part off, register values lost (SLEEP state)
Voltage regulator to digital part on, all other modules in power down
222 µA (XOFF state)
Only voltage regulator to digital part and crystal oscillator running
1.1 mA
Current consumption (IDLE state)
Only the frequency synthesizer running (FSTXON state). This
current consumption also representative for the other intermediate
7.7 mA states when going from IDLE until reaching TX, and frequency
calibration states
25.6 mA Transmit mode, +10 dBm output power (0xC4)
Current consumption, 315 MHz 14.1 mA Transmit mode, 0 dBm output power (0x60)
See more in Section 5.16 and DN012 [3].
26.1 mA Transmit mode, +10 dBm output power (0xC2)
Current consumption, 433 MHz 14.6 Transmit mode, 0 dBm output power (0x60)
See more in Section 5.16 and DN012 [3].
29.3 mA Transmit mode, +10 dBm output power (0xC3)
Current consumption, 868 MHz 15.5 Transmit mode, 0 dBm output power (0x60)
See more in Section 5.16 and DN012 [3].
29.3 mA Transmit mode, +10 dBm output power (0xC0)
Current consumption, 915 MHz 15.2 mA Transmit mode, 0 dBm output power (0x50)
See more in Section 5.16 and DN012 [3].
4.6 RF Transmit
Tc= 25°C, VDD = 3.0 V, if nothing else stated. All measurement results are obtained using the CC1150EM reference design
(see [1] and [2]). PARAMETER TYP MAX UNIT CONDITION
315 MHz 122 + j31 ΩDifferential impedance as seen from the RF-
Differential load 433 MHz 116 + j41 Ωport (RF_P and RF_N) towards the antenna.
impedance Follow the CC1150EM reference design
86.5 +
868/915 MHz Ω(see [1] and [2]).
j43 Output power is programmable, and full
range is available across all frequency
bands. Output power may be restricted by
regulatory limits. See also
DN006 [5].
Delivered to a 50-Ωsingle-ended load via
Output power, highest setting +10 dBm CC1150 EM reference design (see [1] and
[2]) RF matching network. Maximum output
power can be increased 1 to 2 dB by using
wire-wound inductors instead of multilayer
inductors in the balun and filter circuit for the
868/915 MHz band, see more in DN017 [6].
Output power is programmable, and full
range is available across all frequency
bands.
Output power, lowest setting –30 dBm Delivered to a 50 Ωsingle-ended load via
CC1150 EM reference design (see [1] and
[2]) RF matching network.
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RF Transmit (continued)
Tc= 25°C, VDD = 3.0 V, if nothing else stated. All measurement results are obtained using the CC1150EM reference design
(see [1] and [2]). PARAMETER TYP MAX UNIT CONDITION
25 MHz to 1 GHz –36 dBm
Spurious 47 to 74 MHz,
emissions and 87.5 to 118 MHz, –54 dBm
harmonics(1), 174 to 230 MHz,
433/868 MHz 470 to 862 MHz
Otherwise above 1 GHz –30 dBm
< 200 µV/m at 3 m below dBm
–49.2
960 MHz EIRP
Spurious emissions,
315/915 MHz < 500 µV/m at 3 m above dBm
–41.2
960 MHz EIRP Whe output power is maximum
2nd, 3rd and 4th harmonic –20 dBc 6 mV/m at 3 m (–19.6 dBm EIRP)
Harmonics 315 MHz 5th harmonic –41.2 dBm
2nd harmonic –20 dBc With +10 dBm output power
Harmonics 915 MHz 3rd, 4th, and 5th harmonic –41.2 dBm Serial operation. Time from sampling the
TX latency 8 Bits data on the transmitter data input pin until it
is observed on the RF output ports.
(1) Note that close-in spurs vary with centre frequency and limits the frequencies and output power level which the CC1150 can operate at
without violating regulatory restrictions. See also Section 6.2.5 for information regarding additional filtering.
4.7 Crystal Oscillator
Tc= 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1150EM reference design
(see [1] and [2]).
PARAMETER MIN TYP MAX UNIT CONDITION
Crystal frequency 26 26 27 MHz This is the total tolerance including a) initial
tolerance, b) aging and c) temperature
dependence.
Tolerance ±40 ppm The acceptable crystal tolerance depends on
RF frequency and channel spacing /
bandwidth
Load capacitance 10 13 20 pF Simulated over operating conditions
ESR 100 Ω
Measured on the CC1150EM reference
Start-up time 150 µs design (see [1] and [2]). This parameter is to
a large degree crystal dependent.
4.8 Frequency Synthesizer Characteristics
Tc= 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1150EM reference design
(see [1] and [2]).
PARAMETER MIN TYP MAX UNIT CONDITION
Programmed frequency 26 MHz to 27 MHz crystals. The resolution
397 FXOSC / 216 412 Hz
resolution (in Hz) is equal for all frequency bands.
Given by crystal used. Required accuracy
(including temperature and aging) depends
Synthesizer frequency tolerance ±40 ppm on frequency band and channel bandwidth /
spacing.
@ 50 kHz offset from carrier,
RF carrier phase noise –82 dBc/Hz carrier at 868 MHz
@ 100 kHz offset from carrier,
RF carrier phase noise –86 dBc/Hz carrier at 868 MHz
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Frequency Synthesizer Characteristics (continued)
Tc= 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1150EM reference design
(see [1] and [2]).
PARAMETER MIN TYP MAX UNIT CONDITION
@ 200 kHz offset from carrier,
RF carrier phase noise –90 dBc/Hz carrier at 868 MHz
@ 500 kHz offset from carrier,
RF carrier phase noise –98 dBc/Hz carrier at 868 MHz
@ 1 MHz offset from carrier,
RF carrier phase noise –106 dBc/Hz carrier at 868 MHz
@ 2 MHz offset from carrier,
RF carrier phase noise –113 dBc/Hz carrier at 868 MHz
@ 5 MHz offset from carrier,
RF carrier phase noise –119 dBc/Hz carrier at 868 MHz
@ 10 MHz offset from carrier,
RF carrier phase noise –127 dBc/Hz carrier at 868 MHz
Time from leaving the IDLE state until
arriving in the FSTXON or TX state, when
PLL turn-on / hop time 85.1 88.4 88.4 µs not performing calibration.
Crystal oscillator running.
Calibration can be initiated manually or
XOSC
18739 automatically before entering or after leaving
cycles TX.
PLL calibration time Min/typ/max time is for 27/26/26 MHz crystal
694 721 721 µs frequency.
4.9 Analog Temperature Sensor(1)
Tc= 25°C, VDD = 3.0 V if nothing else is stated.
PARAMETER MIN TYP MAX UNIT CONDITION
Output voltage at –40°C 0.651 V
Output voltage at 0°C 0.747 V
Output voltage at +40°C 0.847 V
Output voltage at +80°C 0.945 V
Temperature coefficient 2.45 mV/°C Fitted from –20°C to +80°C
From –20°C to +80°C
when using
Absolute error in calculated temperature –2(2) 2(2) °C 2.45 mV / °C, after 1-point
calibration at room
temperature
Current consumption increase when 0.3 mA
enabled
(1) It is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state.
(2) Indicated minimum and maximum error with 1-point calibration is based on simulated values for typical process parameters
4.10 DC Characteristics
Tc= 25°C if nothing else stated.
DIGITAL INPUTS/OUTPUTS MIN MAX UNIT CONDITION
Logic "0" input voltage 0 0.7 V
Logic "1" input voltage VDD – 0.7 VDD V
Logic "0" output voltage 0 0.5 V For up to 4 mA output current
Logic "1" output voltage VDD – 0.3 VDD V For up to 4 mA output current
Logic "0" input current N/A –1 µA Input equals 0 V
Logic "1" input current N/A 1 µA Input equals VDD
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4.11 Power-On Reset
For proper Power-On-Reset functionality, the power supply must comply with the requirements in this table. Otherwise, the
chip should be assumed to have unknown state until transmitting an SRES strobe over the SPI interface. See Section 5.11.1
for a description of the recommended start-up sequence after turning power on.
PARAMETER MIN TYP MAX UNIT CONDITION
Power up ramp-up time 5 ms From 0 V until reaching 1.8 V
Minimum time between power on and
Power-off time 1 ms power off
4.12 Thermal Resistance Characteristics for VQFNP Package
NAME DESCRIPTION °C/W(1) (2)
RθJC(top) Junction-to-case (top) 54.0
RθJB Junction-to-board 25.1
RθJA Junction-to-free air 48.3
PsiJT Junction-to-package top 1.6
PsiJB Junction-to-board 25.2
RθJC(bottom) Junction-to-case (bottom) 6.3
(1) °C/W = degrees Celsius per watt.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.
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BIAS
XOSC_Q1 XOSC_Q2
XOSC
FREQ
SYNTH
RADIO CONTROL
RF_P
RF_N
CSn
SI
SO (GDO1)
SCLK
GDO0 (ATEST)
RBIAS
PA
FEC /
INTERLEAVER
PACKET
HANDLER
MODULATOR
TX FIFO
DIGITAL
INTERFACE
TO MCU
CC1150
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5 Detailed Description
5.1 Overview
The CC1150 transmitter is based on direct synthesis of the RF frequency. The frequency synthesizer
includes a completely on-chip LC VCO.
A crystal is to be connected to XOSC_Q1 and XOSC_Q2. The crystal oscillator generates the reference
frequency for the synthesizer, as well as clocks for the digital part. A 4-wire SPI serial interface is used for
configuration and data buffer access. The digital baseband includes support for channel configuration,
packet handling and data buffering.
5.2 Functional Block Diagram
Figure 5-1. CC1150 Simplified Block Diagram
5.3 Configuration Overview
CC1150 can be configured to achieve optimum performance for many different applications. Configuration
is done using the SPI interface. The following key parameters can be programmed:
• Power-down and power-up mode
• Crystal oscillator power up and power down
• Transmit mode
• RF channel selection
• Data rate
• Modulation format
• RF output power
• Data buffering with 64-byte transmit FIFO
• Packet radio hardware support
• Forward Error Correction with interleaving
• Data Whitening
Details of each configuration register can be found in Section 5.20.
Figure 5-2 shows a simplified state diagram that explains the main CC1150 states, together with typical
usage and current consumption. For detailed information on controlling the CC1150 state machine, and a
complete state diagram, see Section 5.11.
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Transmit mode
IDLE
Manual freq.
synth. calibration
TX FIFO
underflow
Frequency
synthesizer on
SFSTXON
STX
STX
SFTX
SIDLE
SCAL
IDLE
TXOFF_MODE=00
SRX or STX or SFSTXON
Sleep
SPWD
Crystal
oscillator off
SXOFF
CSn=0
CSn=0
TXOFF_MODE=01
Frequency
synthesizer startup,
optional calibration,
settling
Optional freq.
synth. calibration
Default state when the radio is not
receiving or transmitting. Typ.
current consumption: 1.1 mA.
Lowest power mode.
Register values are lost.
Current consumption typ
200nA.
All register values are
retained. Typ. current
consumption; 0.22 mA.
Used for calibrating frequency
synthesizer upfront (entering
transmit mode can then be
done quicker). Transitional
state. Typ. current
consumption: 7.7 mA.
Frequency synthesizer is turned on, can optionally be
calibrated, and then settles to the correct frequency.
Transitional state. Typ. current consumption: 7.7 mA.
Frequency synthesizer is on,
ready to start transmitting.
Transmission starts very
quickly after receiving the STX
command strobe.Typ. current
consumption: 7.7 mA.
Typ. current consumption 868 MHz:
14 mA at -10 dBm output,
15 mA at 0 dBm output,
24 mA at +7 dBm output,
29 mA at +10 dBm output.
Optional transitional state. Typ.
current consumption: 7.7 mA.
In FIFO-based modes,
transmission is turned off and
this state entered if the TX
FIFO becomes empty in the
middle of a packet. Typ.
current consumption: 1.1 mA.
CC1150
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Figure 5-2. Simplified State Diagram with Typical Usage and Current Consumption
5.4 Configuration Software
CC1150 can be configured using the SmartRF Studio [11] software. The SmartRF Studio software is
highly recommended for obtaining optimum register settings, and for evaluating performance and
functionality. A screenshot of the SmartRF Studio user interface for CC1150 is shown in Figure 5-3.
After chip reset, all the registers have default values as shown in the tables in Section 5.20. The optimum
register setting might differ from the default value. After a reset all registers that shall be different from the
default value therefore needs to be programmed through the SPI interface.
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Figure 5-3. SmartRF Studio User Interface
5.5 4-wire Serial Configuration and Data Interface
CC1150 is configured via a simple 4-wire SPI-compatible interface (SI, SO, SCLK and CSn) where
CC1150 is the slave. This interface is also used to read and write buffered data. All address and data
transfer on the SPI interface is done most significant bit first.
All transactions on the SPI interface start with a header byte containing a read/write bit, a burst access bit
and a 6-bit address.
During address and data transfer, the CSn pin (Chip Select, active low) must be kept low. If CSn goes
high during the access, the transfer will be cancelled. The timing for the address and data transfer on the
SPI interface is shown in Figure 5-4 with reference to Table 5-1.
When CSn is pulled low, the MCU must wait until the CC1150 SO pin goes low before starting to transfer
the header byte. This indicates that the voltage regulator has stabilized and the crystal is running. Unless
the chip is in the SLEEP or XOFF states, the SO pin will always go low immediately after taking CSn low.
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0A6 A5 A4 A3 A2 A0A1 DW7 DW6 DW5 DW4 D W
3 DW2 DW1 D W0
1A6 A5 A4 A3 A2 A0A1
DR 7 DR 6 DR5 DR 4 DR 3 D R 2 DR1 DR0
Read from register:
Write to register:
Hi-Z
X
SCLK:
CSn:
SI
SO
SI
SO Hi-Z
tsp tch tcl tsd thd tns
X X
Hi-Z
X
S7 S6 S5 S4 S3 S2 S1 S0
Hi-Z
S7 S6 S5 S4 S3 S2 S1 S0 S7 S6 S5 S4 S3 S2 S1 S0 S7
X
CC1150
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Figure 5-4. Configuration Registers Write and Read Operations
Table 5-1. SPI Interface Timing Requirements
PARAMETER DESCRIPTION MIN MAX UNIT
SCLK frequency — 10
100 ns delay inserted between address byte and data byte (single access), or
between address and data, and between each data byte (burst access).
SCLK frequency, single access
fSCLK MHz
9
No delay between address and data byte
SCLK frequency, burst access 6.5
No delay between address and data byte, or between data bytes
tsp,pd CSn low to positive edge on SCLK, in power-down mode 150 — µs
tsp CSn low to positive edge on SCLK, in active mode 20 — ns
tch Clock high 50 — ns
tcl Clock low 50 — ns
trise Clock rise time — 5 ns
tfall Clock fall time — 5 ns
Setup data (negative SCLK edge) to positive edge on Single access 55 — ns
SCLK
tsd (tsd applies between address and data bytes, and Burst access 76 — ns
between data bytes)
thd Hold data after positive edge on SCLK 20 — ns
tns Negative edge on SCLK to CSn high 20 — ns
NOTE
The minimum tsp,pd figure in Table 5-1 can be used in cases where the user does not read
the CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from
power-down depends on the start-up time of the crystal being used. The 150 μs in Table 5-1
is the crystal oscillator start-up time measured using crystal AT-41CD2 from NDK.
5.5.1 Chip Status Byte
When the header byte, data byte or command strobe is sent on the SPI interface, the chip status byte is
sent by the CC1150 on the SO pin. The status byte contains key status signals, useful for the MCU. The
first bit, s7, is the CHIP_RDYn signal; this signal must go low before the first positive edge of SCLK. The
CHIP_RDYn signal indicates that the crystal is running and the regulated digital supply voltage is stable.
Bit 6, 5 and 4 comprises the STATE value. This value reflects the state of the chip. The XOSC and power
to the digital core is on in the IDLE state, but all other modules are in power down. The frequency and
channel configuration should only be updated when the chip is in this state. The TX state will be active
when the chip is transmitting.
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The last four bits (3:0) in the status byte con-tains FIFO_BYTES_AVAILABLE. This field contains the
number of bytes free for writing into the TX FIFO. When FIFO_BYTES_AVAILABLE=15, 15 or more bytes
are free. Table 5-2 gives a status byte summary.
Table 5-2. Status Byte Summary
BITS NAME DESCRIPTION
Stays high until power and crystal have stabilized. Should always be low when using the
7 CHIP_RDYn SPI interface.
Indicates the current main state machine mode.
The binary number is the value, the result is the state, and the definition is the current
main state machine mode.
000 = Idle : IDLE state(1)
001 = Not used : Not used
6:04 STATE[2:0] 010 = TX : Transmit mode
011 = FSTXON : Fast TX ready
100 = CALIBRATE : Frequency synthesizer calibration is running
101 = SETTLING : PLL is settling
110 = Not used : Not used
111 = TXFIFO_UNDERFLOW : TX FIFO has underflowed. Acknowledge with SFTX
3:00 FIFO_BYTES_AVAILABLE[3:0] The number of free bytes in the TX FIFO.
(1) Also reported for some transitional states instead of SETTLING or CALIBRATE, due to a small error.
5.5.2 Register Access
The configuration registers on the CC1150 are located on SPI addresses from 0x00 to 0x2E. Table 5-12
lists all configuration registers. The detailed description of each register is found in Section 5.20.
All configuration registers can be both written and read. The read/write bit controls if the register should be
written or read. When writing to registers, the status byte is sent on the SO pin each time a header byte or
data byte is transmitted on the SI pin. When reading from registers, the status byte is sent on the SO pin
each time a header byte is transmitted on the SI pin.
Registers with consecutive addresses can be accessed in an efficient way by setting the burst bit in the
address header. The address sets the start address in an internal address counter. This counter is
incremented by one each new byte (every 8 clock pulses). The burst access is either a read or a write
access and must be terminated by setting CSn high.
For register addresses in the range 0x30 through 0x3D, the burst bit is used to select between status
registers (burst bit is 1) and command strobes (burst bit is 0). See more in Section 5.5.3. Because of this,
burst access is not available for status registers, so they must be read one at a time. The status registers
can only be read.
5.5.3 SPI Read
When reading register fields over the SPI interface while the register fields are updated by the radio
hardware (for example, MARCSTATE or TXBYTES), there is a small, but finite, probability that a single
read from the register is being corrupt. As an example, the probability of any single read from TXBYTES
being corrupt, assuming the maximum data rate is used, is approximately 80 ppm. Refer to the CC1150
Errata Notes [8] for more details.
5.5.4 Command Strobes
Command Strobes may be viewed as single byte instructions to CC1150. By addressing a Command
Strobe register, internal sequences will be started. These commands are used to disable the crystal
oscillator, enable transmit mode, flush the TX FIFO, and so on. The nine command strobes are listed in
Table 5-11.
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CSn
SO
SI
SRES Sxxx Sxxx
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NOTE
An SIDLE strobe will clear all pending command strobes until IDLE state is reached. This
means that if for example an SIDLE strobe is issued while the radio is in TX state, any other
command strobes issued before the radio reaches IDLE state will be ignored.
The command strobe registers are accessed in the same way as for a register write operation, but no data
is transferred. That is, only the R/W bit (set to 0), burst access (set to 0) and the six address bits (in the
range 0x30 through 0x3D) are written.
When writing command strobes, the status byte is sent on the SO pin.
A command strobe may be followed by any other SPI access without pulling CSn high. However, if an
SRES command strobe is being issued, on will have to wait for the SO pin to go low before the next
command strobe can be issued as shown in Figure 5-5.The command strobes are executed immediately,
with the exception of the SPWD and the SXOFF strobes that are executed when CSn goes high.
Figure 5-5. SRES Command Strobe
5.5.5 FIFO Access
The 64-byte TX FIFO is accessed through the 0x3F addresses. When the read/write bit is zero, the TX
FIFO is accessed. The TX FIFO is write-only.
The burst bit is used to determine if FIFO access is single byte or a burst access. The single byte access
method expects address with burst bit set to zero and one data byte. After the data byte a new address is
expected; hence, CSn can remain low. The burst access method expects one address byte and then
consecutive data bytes until terminating the access by setting CSn high.
The following header bytes access the FIFO:
• 0x3F: Single byte access to TX FIFO
• 0x7F: Burst access to TX FIFO
When writing to the TX FIFO, the status byte (see Section 5.5.1) is output for each new data byte on SO,
as shown in Figure 5-5. This status byte can be used to detect TX FIFO underflow while writing data to
the TX FIFO.
NOTE
The status byte contains the number of bytes free before writing the byte in progress to the
TX FIFO.
When the last byte that fits in the TX FIFO is transmitted to the SI pin, the status byte received
concurrently on the SO pin will indicate that one byte is free in the TX FIFO.
The TX FIFO may be flushed by issuing a SFTX command strobe. The SFTX command strobe can only
be issues in the IDLE or TX_UNDERFLOW states. The FIFO is cleared when going to the SLEEP state.
Figure 5-6 gives a brief overview of different register access types possible.
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DATA
byte 0
ADDR
FIFO DATA byte 1 DATA
byte 2 DATA byte n-1 DATA byte n
...
ADDR
strobe
DATA
ADDR
strobe
ADDR
reg
ADDR
reg n DATA nDATA n+1 DATA n+2 ...
ADDR
strobe ...
CSn:
Command strobe(s):
Read or write register(s):
Read or write consecutive registers (burst):
DATA
ADDR
reg DATA
ADDR
reg ...
DATA
byte 0
ADDR
FIFO DATA byte 1
Combinations: DATAADDR
reg DATAADDR reg
ADDR
strobe ADDR strobe ...
Read or write n+1 bytes from/to RF FIFO:
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Figure 5-6. Register Access Types
5.5.6 PATABLE Access
The 0x3E address is used to access the PATABLE, which is used for selecting PA power control settings.
The SPI expects up to eight data bytes after receiving the address. By programming the PATABLE,
controlled PA power ramp-up and ramp-down can be achieved, as well as ASK modulation shaping for
reduced bandwidth.
NOTE
The ASK modulation shaping is limited to output powers below –1 dBm. See SmartRF Studio
[11] for recommended shaping sequence.
See also Section 5.16 for details on output-power programming.
The PATABLE is an 8-byte table that defines the PA control settings to use for each of the eight PA power
values (selected by the 3-bit value FREND0.PA_POWER). The table is written and read from the lowest
setting (0) to the highest (7), one byte at a time. An index counter is used to control the access to the
table. This counter is incremented each time a byte is read or written to the table, and set to the lowest
index when CSn is high. When the highest value is reached the counter restarts at zero.
The access to the PATABLE is either single byte or burst access depending on the burst bit. When using
burst access the index counter will count up; when reaching 7 the counter will restart at 0. The read/write
bit controls whether the access is a write access (R/W=0) or a read access (R/W=1).
If one byte is written to the PATABLE and this value is to be read out then CSn must be set high before
the read access in order to set the index counter back to zero.
NOTE
The content of the PATABLE is lost when entering the SLEEP state. For more information,
see DN501 [8].
5.6 Microcontroller Interface and Pin Configuration
In a typical system, CC1150 will interface to a microcontroller. This microcontroller must be able to do the
following:
• Program CC1150 into different modes
• Write buffered data
• Read back status information via the 4-wire SPI-bus configuration interface (SI, SO, SCLK and CSn)
5.6.1 Configuration Interface
The microcontroller uses four I/O pins for the SPI configuration interface (SI, SO, SCLK and CSn). The
SPI is described in Section 5.5.
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( ) DRATE _ E
DATA XOSC
28
256 DRATE _ M 2
R f
2
+ ´
= ´
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5.6.2 General Control and Status Pins
The CC1150 has one dedicated configurable pin (GDO0) and one shared pin (GDO1/SO) that can output
internal status information useful for control software. These pins can be used to generate interrupts on
the MCU. See Section 5.17 for more details of the signals that can be programmed. The shared pin is the
SO pin in the SPI interface. The default setting for GDO1/SO is 3-state output. By selecting any other of
the programming options the GDO1/SO pin will become a generic pin. When CSn is low, the pin will
always function as a normal SO pin.
In the synchronous and asynchronous serial modes, the GDO0 pin is used as a serial TX data input pin
while in transmit mode.
The GDO0 pin can also be used for an on-chip analog temperature sensor. By measuring the voltage on
the GDO0 pin with an external ADC, the temperature can be calculated. Specifications for the temperature
sensor are found in Section 4.9. With default PTEST register setting (0x7F), the temperature sensor
output is only available when the frequency synthesizer is enabled (for example, the MANCAL, FSTXON
and TX states). It is necessary to write 0xBF to the PTEST register to use the analog temperature sensor
in the IDLE state. Before leaving the IDLE state, the PTEST register should be restored to its default value
(0x7F).
5.6.3 Optional Radio Control Feature
The CC1150 has an optional way of controlling the radio by reusing SI, SCLK, and CSn from the SPI
interface. This feature allows for a simple three-pin control of the major states of the radio: SLEEP, IDLE,
and TX.
This optional functionality is enabled with the MCSM0.PIN_CTRL_EN configuration bit.
State changes are commanded as follows:
• If CSn is high, the SI and SCLK are set to the desired state according to Table 5-3.
• If CSn goes low, the state of SI and SCLK is latched and a command strobe is generated internally
according to the pin configuration.
It is only possible to change state with the latter functionality. That means that for instance TX will not be
restarted if SI and SCLK are set to TX and CSn toggles. When CSn is low the SI and SCLK has normal
SPI functionality.
All pin control command strobes are executed immediately except the SPWD strobe. The SPWD strobe is
delayed until CSn goes high.
Table 5-3. Optional Pin Control Coding
CSn SCLK SI FUNCTION
1 X X Chip unaffected by SCLK/SI
↓0 0 Generates SPWD strobe
↓0 1 Generates STX strobe
↓1 0 Generates SIDLE strobe
↓1 1 Defined on the transceiver version (CC1101)
SPI mode (wakes up into IDLE if in
0 SPI mode SPI mode SLEEP/XOFF)
5.7 Data Rate Programming
The data rate used when transmitting is programmed by the MDMCFG3.DRATE_M and the
MDMCFG4.DRATE_E configuration registers. The data rate is given by the formula below. As Equation 1
shows, the programmed data rate depends on the crystal frequency.
(1)
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20
DATA
2
XOSC
28
DATA
DRATE _ E
XOSC
R 2
DRATE _ E log f
R 2
DRATE _ M 256
f 2
é ù
æ ö
´
ê ú
ç ÷
=ç ÷
ê ú
è ø
ë û
´
= -
´
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The following approach shown in Equation 2 can be used to find suitable values for a given data rate.
(2)
If DRATE_M is rounded to the nearest integer and becomes 256, increment DRATE_E and use
DRATE_M=0.
The data rate can be set from 0.8 kBaud to 500 kBaud with the minimum data rate step size changes
according to Table 5-4.
Table 5-4. Data Rate Step Size
MIN DATA RATE TYPICAL DATA RATE MAX DATA RATE DATA RATE STEP SIZE
[kBaud] [kBaud] [kBaud] [kBaud]
0.8 1.2 / 2.4 3.17 0.0062
3.17 4.8 6.35 0.0124
6.35 9.6 12.7 0.0248
12.7 19.6 25.4 0.0496
25.4 38.4 50.8 0.0992
50.8 76.8 101.6 0.1984
101.6 153.6 203.1 0.3967
203.1 250 406.3 0.7935
406.3 500 500 1.5869
5.8 Packet Handling Hardware Support
The CC1150 has built-in hardware support for packet oriented radio protocols.
In transmit mode, the packet handler can be configured to add the following elements to the packet stored
in the TX FIFO:
• A programmable number of preamble bytes.
• A two byte Synchronization Word. Can be duplicated to give a 4-byte sync word (recommended). It is
not possible to only insert preamble or only insert a sync word.
• Optionally whitening the data with a PN9 sequence.
• Optionally Interleave and Forward Error Code the data.
• Optionally compute and add a 2-byte CRC checksum over the data field.
In a system where CC1150 is used as the transmitter and CC1101 as the receiver the recommended
setting is 4-byte preamble and 4-byte sync word except for 500 kBaud data rate where the recommended
preamble length is 8 bytes.
NOTE
Register fields that control the packet handling features should only be altered when CC1150
is in the IDLE state.
5.8.1 Data Whitening
From a radio perspective, the ideal over the air data are random and DC free. This results in the
smoothest power distribution over the occupied bandwidth. This also gives the regulation loops in the
receiver uniform operation conditions (no data dependencies).
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Preamble bits
(1010...1010)
Sync word
Length field
Address field
Data field
CRC-16
Optional CRC-16 calculation
Optionally FEC encoded/decoded
Optional data whitening
Legend:
Inserted automatically in TX,
processed and removed in RX.
Optional user-provided fields processed in TX,
processed but not removed in RX.
Unprocessed user data (apart from FEC
and/or whitening)
8 x n bits 16/32
bits
8
bits
8
bits 8 x n bits 16 bits
TX_OUT[7:0]
TX_DATA
8 7 6 5 4 3 2 1 0
76 5 4 3 2 1 0
The first TX_DATA byte is shifted in before doing the XOR-operation providing the first TX_OUT[7:0] byte. The
second TX_DATA byte is then shifted in before doing the XOR-operation providing the second TX_OUT[7:0] byte.
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Real world data often contain long sequences of zeros and ones. Performance can then be improved by
whitening the data before transmitting, and de-whitening in the receiver. With CC1150, in combination with
a CC1101 at the receiver end, this can be done automatically by setting PKTCTRL0WHITE_DATA=1. All
data, except the preamble and the sync word, are then XOR-ed with a 9-bit pseudo-random (PN9)
sequence before being transmitted as shown in Figure 5-7. The PN9 sequence is initialized to all ones. At
the receiver end, the data are XOR-ed with the same pseudo-random sequence. This way, the whitening
is reversed, and the original data appear in the receiver.
Setting PKTCTRL0.WHITE_DATA=1 is recommended for all uses, except when over-the-air compatibility
with other systems is needed.
Figure 5-7. Data Whitening in TX Mode
5.8.2 Packet Format
The format of the data packet can be configured and consists of the following items:
• Preamble
• Synchronization word
• Optional length byte
• Optional Address byte
• Payload
• Optional 2 byte CRC
Figure 5-8. Packet Format
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