
vii
Themis Computer
Table of Contents
4. Universe II Description ................................................................................................ 4-1
4.1 Features .................................................................................................................. 4-1
4.2 VMEbus Interface .................................................................................................. 4-2
4.2.1 VMEbus Configuration .............................................................................. 4-2
4.2.2 Universe II as the VMEbus Slave .............................................................. 4-2
4.2.3 Universe II as the VMEbus Master ............................................................ 4-3
4.2.4 VMEbus First Slot Detector ...................................................................... 4-5
4.2.4.1 Automatic Slot Identification ...................................................... 4-6
4.2.4.2 Register Access at Power Up ......................................................4-7
4.2.5 Universe II’s Hardware Power-Up Options ...............................................4-7
4.3 Slave Image Programming ..................................................................................... 4-9
4.3.1 VME Slave Images .................................................................................... 4-9
4.3.1.1 VMEbus Fields ........................................................................... 4-9
4.3.1.2 PCI Bus Fields .......................................................................... 4-10
4.3.1.3 Control Fields ........................................................................... 4-11
4.3.2 PCI Bus Target Images ............................................................................ 4-12
4.3.2.1 PCI Bus Fields .......................................................................... 4-12
4.3.2.2 VMEbus Fields ......................................................................... 4-12
4.3.2.3 Control Fields ........................................................................... 4-13
4.3.2.4 Special PCI Target Image ......................................................... 4-14
4.4 Universe II’s Interrupt and Interrupt Handler ...................................................... 4-17
4.4.1 VME and PCI Interrupters ....................................................................... 4-17
4.4.2 VMEbus Interrupt Handling .................................................................... 4-18
4.4.3 Universe II’s Mailbox Registers .............................................................. 4-18
4.4.4 Universe II’s Semaphores ........................................................................ 4-18
4.4.5 Programmable Slave Images on the VMEbus and PCI bus ..................... 4-18
4.4.6 DMA Controller ....................................................................................... 4-19
5. Field-Programmable Gate Array (FPGA) .................................................................. 5-1
5.1 Introduction ............................................................................................................ 5-1
5.2 VME Reset Control ............................................................................................... 5-2
5.3 Watchdog Timer .................................................................................................... 5-3
5.3.1 Watchdog Timers ....................................................................................... 5-3
5.3.2 Watchdog-Related Registers ...................................................................... 5-3
5.3.3 Watchdog Start/Restart .............................................................................. 5-3