Themis USPIIi-1v User manual

USPIIi-1v
Hardware Manual
Revision B4

Themis Computer—Rest of World
20 rue du Tour de l’Eau
38400 Saint Martin d’Hères, France
Phone [phone]
Fax [phone]
Themis Computer—Americas and Pacific Rim
3185 Laurelview Court
Fremont, CA 94538
Phone [phone]
Fax [phone]
World Wide Web http://www.themis.com
USPIIi-1v Hardware Manual
Version B4 — December 2001

Copyright © 2000 Themis Computer, Inc.
ALL RIGHTS RESERVED. No part of this publication may be reproduced in any form, by
photocopy, microfilm, retrieval system, or by any other means now known or hereafter invented without
the prior written permission of Themis Computer.
The information in this publication has been carefully checked and is believed to be accurate. However,
Themis Computer assumes no responsibility for inaccuracies. Themis Computer retains the right to
make changes to this publication at any time without prior notice. Themis Computer does not assume
any liability arising from the application or use of this publication or the product(s) described herein.
RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the United States Government
is subject to the restrictions set forth in DFARS 252.227-7013 (c)(1)(ii) and FAR 52.227-19.
TRADEMARKS
SOLARIS™is a registered trademark of Sun Microsystems
SPARC™ is a registered trademark of SPARC International
All other trademarks used in this publication are the property of their respective owners.
USPIIi-1v Hardware Manual
December 2001
Part Number: 105614
Themis Customer Support
Telephone: [phone]
Fax: [phone]
E-mail: [e-mail]
Web Site: http://www.themis.com

Version Revision History
Version B4 December 2001
Replaced Universe II with Universe IIB throughout manual.
Corrected misspellings throughout manual.
Reenforced definition of backplane reset on pages 2-2 and B-2.
Defined non-standard signal for P2 pin B3 in Table A-2, page A-3.
Reversed Serial Port C and D callouts, pages C-3, C-4, and D-5.
Version B3 October 5, 2000
Corrected I/O Board Jumper Setting references on page B-5.
Version B2 July 20, 2000
Changed definition of OBP in System and User 1 flash.
Fixed minor inconsistencies in B.2.1 and 3.2.3.
Version B1 May 25, 2000
Reworked for 360/440 MHz CPU.
Fixed Jumper references.
Version B January 17, 2000
Version A1 September 29, 1998
Version A July 29, 1998
Initial Customer Release.

USPIIi-1v User’s Manual
Themis Computer

Themis Computer v
Table of Contents
1 Introduction ........................................................................................................... 1-1
1.1 How to Use This Manual ....................................................................................... 1-1
1.2 Intended Audience ................................................................................................. 1-1
1.3 Product Warranty and Registration........................................................................ 1-2
1.4 Unpacking.............................................................................................................. 1-2
1.5 How to Start Quickly ............................................................................................. 1-3
1.6 Chapter Overview .................................................................................................. 1-4
1.7 Related References ................................................................................................ 1-4
2 Installation ............................................................................................................. 2-1
2.1 Determine Board Type and Configuration ............................................................ 2-1
2.2 Configuration ......................................................................................................... 2-2
2.3 Backplane Jumper Settings.................................................................................... 2-2
2.4 Installing The USPIIi-1v Paddle Board ................................................................. 2-3
2.5 Attaching Cables to Peripheral Devices ................................................................ 2-4
2.5.1 Console Port (TTYA) ............................................................................ 2-4
2.5.2 Keyboard and Mouse ............................................................................. 2-5
2.5.3 Ethernet Network................................................................................... 2-5
2.5.4 SCSI A and B......................................................................................... 2-5
2.5.5 Creator Graphics Card ........................................................................... 2-6
2.6 Configuring The VME Interface............................................................................ 2-6
3 Specification.......................................................................................................... 3-1
3.1 Overview................................................................................................................ 3-1
3.1.1 Baseboard............................................................................................... 3-1
3.1.2 I/O Board and Creator Graphics ............................................................ 3-2
3.1.3 PMC Carrier Board................................................................................ 3-2
3.1.4 Paddle Board.......................................................................................... 3-2
3.1.5 Block Diagram....................................................................................... 3-3
3.2 System Specification.............................................................................................. 3-4
3.2.1 Processor & Memory Subsystems ......................................................... 3-4

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vi Themis Computer
3.2.2 I/O Subsystem........................................................................................ 3-5
3.2.3 Auxiliary Functions ............................................................................... 3-6
3.3 Environmental Specification.................................................................................. 3-7
3.4 Estimated Power Requirements ............................................................................. 3-8
4 Hardware Overview................................................................................................ 4-1
4.1 Major Components ................................................................................................ 4-1
4.1.1 SME UltraSPARC-IIi Processor and Cache.......................................... 4-1
4.1.2 E-Cache.................................................................................................. 4-1
4.1.3 SME Advanced PCI Bridge (APB) ....................................................... 4-2
4.1.4 SME Reset, Interrupt, and Clock (RIC)................................................. 4-2
4.1.5 Tundra Universe IIB .............................................................................. 4-2
4.1.6 SME PCI I/O Controller ........................................................................ 4-3
4.1.7 Symbios SCSI Controller....................................................................... 4-3
4.1.8 FPGA ..................................................................................................... 4-3
4.1.9 National Super I/O ................................................................................. 4-3
4.1.10 Seimens SAB 82532 .............................................................................. 4-3
4.1.11 FLASH.................................................................................................. 4-3
4.1.12 TOD and NVRAM................................................................................. 4-4
4.2 Memory Subsystem ............................................................................................... 4-4
4.3 PMC Carrier Subsystem ........................................................................................ 4-5
4.4 OpenBoot PROM................................................................................................... 4-5
5 Universe-IIB Description ....................................................................................... 5-1
5.1 Features.................................................................................................................. 5-1
5.2 USPIIi-1v and the Universe IIB PCI Interface ...................................................... 5-2
5.3 VMEbus Interface.................................................................................................. 5-2
5.3.1 VMEbus Configuration.......................................................................... 5-2
5.3.2 Universe IIB as the VMEbus Slave ....................................................... 5-2
5.3.3 Universe IIB as the VMEbus Master..................................................... 5-3
5.3.4 VMEbus First Slot Detector .................................................................. 5-4
5.3.4.1 Automatic Slot Identification............................................. 5-5
5.3.4.2 Registered Access at the power up .................................... 5-6
5.3.5 Universe IIB’s hardware Power -Up Options........................................ 5-6
5.4 Slave Image Programming..................................................................................... 5-7
5.4.1 VME Slave Images ................................................................................ 5-8
5.4.1.1 VMEbus Fields .................................................................. 5-8
5.4.1.2 PCI Bus Fields ................................................................... 5-8
5.4.1.3 Control Fields .................................................................... 5-9
5.4.2 PCI Bus Target Images .......................................................................... 5-9
5.4.2.1 PCI Bus Fields ................................................................... 5-10
5.4.2.2 VMEbus Fields .................................................................. 5-10
5.4.2.3 Control Fields .................................................................... 5-11
5.4.2.4 Special PCI Target Image .................................................. 5-11

Themis Computer vii
Table of Contents
5.5 Universe IIB’s Interrupt and Interrupt Handler ..................................................... 5-14
5.5.1 VME and PCI Interrupters:.................................................................... 5-14
5.5.2 VMEbus Interrupt Handling: ................................................................. 5-15
5.5.3 Universe IIB’s Mailbox Registers: ........................................................ 5-15
5.5.4 Universe IIB’s Semaphores ................................................................... 5-15
5.5.5 Programmable slave images on the VMEbus and PCI bus: .................. 5-15
5.5.6 DMA Controller..................................................................................... 5-16
6 FPGA, Watchdog, Voltage and Temperature Sensors ...................................... 6-1
6.1 FPGA ..................................................................................................................... 6-1
6.1.1 Introduction............................................................................................ 6-1
6.1.2 Boot Address Decoder ........................................................................... 6-1
6.1.3 3-Level Watchdog.................................................................................. 6-2
6.1.4 Power Management System................................................................... 6-3
6.2 Temperature Sensor ............................................................................................... 6-4
7 Resets .................................................................................................................... 7-1
7.1 Overview................................................................................................................ 7-1
7.2 UltraSPARC-IIiReset Request Signals................................................................. 7-2
7.2.1 Power-On Reset (POR).......................................................................... 7-2
7.2.2 Externally Initiated Reset (XIR) ............................................................ 7-2
7.2.3 Watchdog Reset (WDR) ........................................................................ 7-2
7.2.4 Software Initiated Reset (SIR) ............................................................... 7-3
7.3 Reset Sources......................................................................................................... 7-3
7.3.1 Push Button Reset.................................................................................. 7-3
7.3.2 Power Management Resets.................................................................... 7-3
7.3.3 VMEbus Resets...................................................................................... 7-4
7.3.4 3-Level Watchdog Resets ...................................................................... 7-4
7.3.5 Software POR ........................................................................................ 7-4
7.3.6 Software XIR ......................................................................................... 7-4
7.4 UltraSPARC-IIiReset Control Register ................................................................ 7-5
7.5 USPIIi-1v Reset Tree Diagram.............................................................................. 7-6
A Connector Pinouts, LEDs, Switches ................................................................... A-1
A.1 Introduction............................................................................................................ A-1
A.2 Baseboard Front Panel ........................................................................................... A-1
A.2.1 Baseboard VME P1 ............................................................................... A-1
A.2.2 Baseboard VME P2 ............................................................................... A-3
A.2.3 SCSI A and B......................................................................................... A-6
A.2.4 RJ45 Ethernet A Connector ................................................................... A-8
A.2.5 Keyboard/Mouse Connector and Serial Port A (PS/2 Mode only)........ A-9
A.2.6 PS/2 Keyboard/Mouse Split Cable ........................................................ A-10
A.2.7 Serial Port A (Console) Adapter Cable (PS/2 Mode only).................... A-11
A.2.8 Keyboard/Mouse Connector and Serial Port A (Sun Mode only) ......... A-12
A.2.9 LEDs ...................................................................................................... A-13

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A.2.10 Push-Button RESET .............................................................................. A-13
A.3 I/O Board ............................................................................................................... A-14
A.3.1 I/O Board VME P2 ................................................................................ A-14
A.3.2 Serial Port C (TTYC or Console) and Serial Port D (TTYD or Aux Port) A-
16
A.3.3 Parallel Port............................................................................................ A-18
A.3.4 RJ45 Ethernet B Connector ................................................................... A-19
A.3.5 Audio ..................................................................................................... A-19
A.3.6 Creator Graphics Slot............................................................................. A-19
A.4 PMC Carrier Board................................................................................................ A-20
A.4.1 PMC Carrier Board P1 Connector ......................................................... A-20
A.4.2 PMC Carrier Board VME P2 Connector ............................................... A-22
A.4.3 PMC Carrier Slot User I/O .................................................................... A-24
A.4.3.1 PMC Carrier Slot #1: 64 Bit User I/O Configuration........ A-24
A.4.3.2 PMC Carrier Slot #1: 32 Bit User I/O Configuration........ A-26
A.4.3.3 PMC Carrier Slot #2: 32 Bit User I/O Configuration........ A-27
A.5 Paddle Board.......................................................................................................... A-28
A.5.1 SCSI Connector ..................................................................................... A-28
A.5.2 MII Connector........................................................................................ A-30
A.5.3 DB9 Connector ...................................................................................... A-31
B Jumper and Solder Bead Configurations ............................................................ B-1
B.1 Overview................................................................................................................ B-1
B.2 Field Configurables................................................................................................ B-1
B.2.1 Baseboard Jumpers ................................................................................................ B-1
B.2.2 I/O Board Jumpers ................................................................................................. B-4
B.2.3 PMC Carrier Board Jumpers.................................................................. B-6
B.3 Factory Configurables............................................................................................ B-6
B.3.1 Baseboard Solder Beads ........................................................................ B-6
B.3.2 I/O Board Solder Beads ......................................................................... B-10
B.3.3 PMC Carrier Board Solder Beads.......................................................... B-10
C Front Panel Diagrams............................................................................................ C-1
C.1 Introduction............................................................................................................ C-1
C.2 Baseboard Front Panel ........................................................................................... C-2
C.3 Baseboard, I/O Board, and Creator Graphics Front Panels ................................... C-3
C.4 Baseboard, I/O Board, and PMC Carrier Board Front Panel................................. C-4
D Board Diagrams ..................................................................................................... D-1
D.1 Baseboard Board Diagrams ................................................................................... D-1
D.2 I/O Board Diagrams............................................................................................... D-5
D.3 PMC Board ............................................................................................................ D-6
D.4 Paddle Board.......................................................................................................... D-8
E Glossary.................................................................................................................. F-1
E.1 Terminology........................................................................................................... F-1