Toshiba TDP-P75 User manual

SERVICE MANUAL
FILE NO. 330-200509
DLP PROJECTOR
TDP-P75
Document Created in Japan Jun.,2005

TDP-P75 Service Manual
Table of Contents
1. Safety Precautions................................................................................................2
2. Servicing Precautions ..........................................................................................3
3. Specification..........................................................................................................4
4. Circuit Operation.................................................................................................9
5. Alignment Procedure.........................................................................................20
6. Trouble Shooting Guide.....................................................................................28
7. Factory Mode OSD............................................................................................32
8. Parts Exploded View..........................................................................................37
9. Spare Parts List..................................................................................................42
10. Parts Disassembly ..............................................................................................46
(*1) GREEN PRODUCT PROCUREMENT
The EC is actively promoting the WEEE & RoHS Directives that define standards for
recycling and reuse of Waste Electrical and Electronic Equipment and for the
Restriction of the use of certain Hazardous Substances. From July 1, 2006, the RoHS
Directive will prohibit any marketing of new products containing lead.
Increasing attention is given to issues related to the global environmental. Toshiba
Corporation recognizes environmental protection as a key management tasks, and is
doing its utmost to enhance and improve the quality and scope of its environmental
activities. In line with this, Toshiba proactively promotes Green Procurement, and
seeks to purchase and use products, parts and materials that have low environmental
impacts.
Green procurement of parts is not only confined to manufacture. The same green parts
used in manufacture must also be used as replacement parts.
(*2) LEAD-FREE SOLDER
This product is manufactured using lead-free solder as a part of a movement within
the CE industry at large to be environmentally responsible. Lead-free solder must be
used in the servicing and repair of this product.
WARNING
This product is manufactured using lead free solder.
DO NOT USE LEAD BASED SOLDER TO REPAIR THIS PRODUCT !
CAUTION
BEFORE SERVICING THE PROJECTOR,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
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1. Safety Precautions
1. Be sure to read this manual before servicing and save it for future reference.
2. The lamp becomes extremely hot during operation. Allow the projector to cool for
approximately 60 minutes prior to removing the lamp assembly for replacement.
Do not operate lamps beyond the rated lamp life. Excessive operation of lamps
beyond the rated life could cause them to explode on rare occasions.
3. Never replace the lamp assembly or any electronic components unless the
projector is unplugged.
4. To reduce the risk of electric shock, do not disassemble this appliance. Take it to
a qualified technician when service or repair is required. Incorrect re-assembly
can cause electric shock when the appliance is subsequently used.
5. Do not place this product on an unstable cart, stand, or table. The product may
fail, sustaining serious damage.
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2. Servicing Precautions
1. When replace the lamp, be sure to avoid burns your fingers because the lamp
becomes too hot.
2. Never touch the lamp bulb with a finger or anything else. Never drop it or give it a
shock. They may cause bursting of the bulb.
3. This projector is provided with a high voltage circuit for the lamp. Do not touch the
electric parts of power unit when turn on the projector.
4. Do not touch the exhaust fan during operation.
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3. Specification
1.0 Optical Performance Tested under 60” (diagonal) image size with Wide projection
lens position, Toshiba meter and “SPOKE mode” unless
otherwise specified.
1.1 ANSI Brightness Minimum 1760 Lumens (Spoke mode)
1.2 Brightness Uniformity
1.2.1 ANSI Uniformity Minimum 50% (Spoke mode)
1.3 Contrast Ratio
1.3.1 ANSI Contrast Minimum 150:1
Typical 400:1 (reference)
1.3.2 FOFO Contrast Minimum 1000:1 (Spoke mode)
Typical 1400:1 (reference)
1.4 Light Leakage (need RD explain)
1.4.1 Light Leakage inActive Area <2 lux + center point darkness within 60” (diagonal) image
size
1.4.2 Light Leakage out ofActive
Area <2 lux when active area is 60” (diagonal) , wide
1.5 Color
X Y
1.5.1 White .299±.025 .325±.030
1.5.2 Red .632±.035 .351±.035
1.5.3 Green .316±.040 .570+.030
1.5.4 Blue .143±.015 .085±.040
ΔX ΔY
1.6.1 White .030 .030
1.6.2 Red .040 .040
1.6.3 Green .030 .030
1.6.4 Blue .040 .040
2.0 Image Quality
2.1 Throw Ratio 60”±5% Diagonal at 2m, Wide
2.2 Zoom Ratio (tolerance applied) 1.2 : 1
2.3 Distortion
2.3.1 Keystone Distortion <1.0%
2.3.2 Vertical TV Distortion <1.0%
2.4 Projection Offset 133% ±5%
Distance Wide/Tele
1.50m(min) 45/37
2.00m 60/49
3.33m 100/82
2.5 Focus Range
Zoom Ratio (tolerance applied)
6.00m(max) 180/148
2.6 Focus
2.6.1 X Pattern (1) if pattern can be uniformly focused, pass!
(2) if not, check 2.6.2
2.6.2 Focus & defocus (A17) – follow
BenQ & TOSHIBA’s limit sample
approved by 1/19
Flare (B)
R <=3.5 Defocus (A)
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G<=3.5
B<=3.5
Slight flare no count
R<=2.5
G<=2.5
B<=2.5
Center of screen
(Center of screen is
defined as center grid
when divide screen in
to 9 grids)
All other area
R-G <1/2 <1
G-B <1/2 <1
2.7 Lateral Color
Spectrum 450-600 nm
R-B <1 <1
3.0 Mechanical Specification
3.1 Dimensions 183 x 245 x 86 mm (L x W x H) (with protrusion part)
3.2 Weight <1991g (without lens cap)
3.3 Security Slot Kensington compatible slot 150N break away force
3.5 Lens Cover Detached Lens Cover
4.0 Packaging
4.1 Outside Dimensions 340 x 365 x 247mm (L x W x H) (TBD)
4.2 Weight <5.0 Kg (Including Accessories, Projector). (TBD)
4.3 Palletization 36 by Air; 1536 / 40’ container, or 672/20’ container by sea
(TBD)
4.4 Shock 50G, 20ms, Half-sine.
5.0 Thermal Specification Maximum temperature (0~35 °C)
Metal Plastic
5.1 Handles, knobs, grips, etc. and
surface Held or touched for short
periods only 60°C 85°C
(Bottom surface) (55°C) @25°C (70°C) @25°C
Metal Plastic
5.2 External surface or equipment
which may be touched 70°C 95°C
5.3 Exhaust Air 95°
6.0 Environmental
Operating 0~35°C, without condensation
6.1 Temperature Storage -20~60°C, without condensation
Operating 10~90%RH, without condensation
6.2 Humidity Storage 10~90%RH, without condensation
6.3 Audible Noise Level Maximum Normal mode: 37dBA@ 25°C
Eco mode: 35dBA @ 25°C
@Sea level
6.4 Altitude
Operation Temperature
0~35°C for height：0~2,500 ft
0~30°C for height：2,500~3,000 ft
0~30°C for height：3,000~10,000 ft (high fan speed mode)
Non-Operation Temperature
0~30°C / 4 hrs for height：0~40,000 ft
Operating test 0~35°C, Humidity：10%~90%
6.5 Temperature cycle test
(Follow CNS：68-2,12919) Non-operating test -10~60°C, Humidity：
10%~90%
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Safety
ULApproved (UL 1950, CSA950), TUV-GS, CCC, CB Report, PSE, SJQA, GOST
EMC FCC Class B requirements, C-Tick, PSE
CE Marks Directive 73/23/EEC;
Directive 89/336/EEC;
7.0 Reliability(TBD)
8.0 Reliability
8.1 General Failure Def.
8.2 MTBF 20000 hours except DMD chip, Color wheel, Lamp and Fan
8.3 Lamp Lifetime (Add continuous
ECO mode spec.)
1500 hours (50% brightness maintenance with survival
ratio more than 50%) “continuous" ECO mode lamp usage
hour 2500 Hrs
9.0 Power Requirements
9.1 Input Voltage Range 90 V ac to 264 V ac
9.2 Frequency Range 47 Hz to 63 Hz.
110V 40A Max
9.3 Inrush Current (Cold start only) 240V 50A Max
9.4 Power consumption 280W Max
9.5 Standby Power consumption < 10W
FCC part 15 Class B
9.8 EMI CISPR22 1997 Class B
9.9 Electro Static Discharge (ESD) Standard (CE standard) +\-4 KV contact,+\-8KV
air discharge 330Ω
150pf
9.10 Electrical Fast Transients (EFT) +\-1KV on input power lines.
Standard +\-1KV line to line, +\-
2KV line to ground on
input power lines.
9.11 Surge Toshiba Standard (Target, can
be discussed)
+\-6KV line to line once
for design goal
+\-12KV line to line once
for RD Design test stage
Standard EN61000-4-11
9.12 Voltage Dips Toshiba Standard 20ms for RD design goal
9.13 Power Connector IEC
10.0 Panel Specification
10.1 Type Single Chip 0.7” XGA12°tilt DDR DMD
10.2 Pixels H: 1024 X V: 768
10.3 Color Depth 24 Bits (16770000 colors)
11.1 PC PC Compatible 640X480 Æ1024X768, compressed
1280X1024;
11.2 Video NTSC/ NTSC4.43/ PAL (Including PAL-M, PAL-N)/ SECAM/
PAL60/
11.3 YPbPr NTSC (480i)/ 480p/ PAL (576i)/ 576p, HDTV (720p/ 1080i)
11.4 DDC DDC 2B
11.0 Control Interface
12.1 Analog RGB Input 15 pin D-Sub (Female) x 1
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G(Y): Video amplitude 0.7/1.0 Vp-p : Impedance 75 ・
RB(CbCr): Video amplitude 0.7 Vp-p : Impedance 75 ・
HD/VD/CS: TTL Level
12.2 Video Input RCA jack (Yellow)
Video amplitude 1.0 Vp-p : Impedance 75Ω
12.3 S-Video Input 4 pin Mini-Din (Female)
Y: Luminance amplitude 1.0 Vp-p : Impedance75Ω
C: Chroma amplitude 0.268 Vp-p : Impedance75Ω
12.4 RGB output 15 pin D-Sub (Female) x 1
12.0
13.1 IR Receiver IR Receiver x2 (Front, Rear)
13.2 USB port for FW download
14.0 User Interface
14.1 Operator Keypad 8 Keys:
On/Standby; Input; Auto Set; Menu; Left/(Vol+);
Right/(Vol-); Up; Down
14.2 Indicators 3 LEDs:
Power On/Off Status; Lamp Status; Temperature Status;
15.0 Audio
15.1 Audio Input Φ3.5mm stereo mini jack
350mVrms 10 KΩor more
15.2 Audio Output Φ3.5mm stereo mini jack (monaural signal)
1.4 Vrms, 250mW (MAX), Load impedance >8Ω
15.3 Speaker 8Ω1W X 1 (Size: 40 X 28 X 11.2 mm3)
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3.1. Interface Definition
15 pin definition of the mini D-sub male for DDC2B protocol
15
610
11 15
Pin Definition Pin Definition Pin Definition Pin Definition
GRD
(
R
)
GRD
(
G
)
GRD
(
B
)
GRD
(
Pr
)
GRD
(
Y
)
GRD
(
Pb
)
9 NC 10 GRD 11 GRD 12 SD
A
13 Horizontal Sync 14
V
ertical Sync 15 SCL
1 Pin
1
Composite input
1
2
3
434
21
GRD
GRD
Luminance
Chroma
8
Definition
Composite video
S-Video input
5 GRD 6 7
3
Blue Signal
4 GRD
Colo
r
Difference
Si
g
nal
(
Pr
)
1
Red Signal
2
Green Signal
Colo
r
Difference
Si
g
nal
(
Pr
)
Luminance
Signal (Y)
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4. Circuit Operation
4.1. Functional Description
4.1.1. 1.1 Overview
The DDP2000 Component set consists of the DDP2000 projector controllerASIC, a Double
Data Rate DMD (XGAor SVGA resolution), and the DAD1000 analogASIC. The DDP2000
reference design includes these components along with peripheral devices which form the
electronics portion of a projector design. Please see Figure 1.
The DDP2000 is the first DLP TM data processor component to integrate all of the system image
processing and system control, as well as DMD data formatting, on to a single integrated circuit (IC).
4.1.2. Signal Conditioning: Decoding and A/D Conversion
The DDP2000 ASIC receives data on two identical 24bit RGB digital buses. In order to
process video inputs from a variety of sources, the TI reference design makes use of an
Analog Devices AD9882 analog interface and a Micronas VPX3226E video decoder.
The video decoder accepts NTSC/PAL/SECAM composite and s-video inputs. The output is
formatted as YCrCb and routed to the DDP2000.
The AD9882 analog interface will convert analog RGB/YUV signals to 24 bit digital data. The
AD9882 includes a DVI 1.0 compatible receiver which includes HDCP support. The 24 bit
RGB/YUV output is routed to the DDP2000.
4.1.3. Signal Processing in the DDP2000
The DDP2000 combines the DLP TM data processing functions used in the DDP1000 with high
performance DLP TM front-end image processing in the same device. The DDP2000 includes
the front-end functions ofAutoLock, Motion-Adaptive De-Interlacing, Spatial-Temporal Noise
Reduction Filters, Edge-Preserving Scaling, KeystoneAdjustment and On-Screen Display.
For computer graphics the DDP2000 accepts up to SXGA+ (1400 x 1050) resolutions. For
motion video, the DDP2000 accepts inputs for NTSC, PAL, SECAM, 480p, and both 720p and
1080i HD.
A single RDRAM™ is used with the DDP2000 for bit-plane storage and as an extensive
workspace for de-interlacing, noise reduction filters, and AutoLock. Unlike other front-end ICs,
no additional external RAM is needed for supporting de-interlacing. Sharing the bit-plane
storage RAM with image processing storage is a unique DLP TM capability that reduces overall
system cost.
In addition to the new front-end functions, the DDP2000 includes all of the DLP TM data
processing algorithms that are currently provided in the DDP1000 such as the functions of
degamma, spoke light recapture, white segment processing, secondary color boost, and
spatial-temporal multiplexing. In total there are 26 DLP TM proprietary algorithms used in theDDP2000
for pixel processing, data formatting, and mirror PWM control resulting in images
that are optimized in quality for display on a DMD device.
4.1.4. System Controller
A 120MHz ARM946 processor embedded in the DDP2000 is used to execute custom software
developed by OEMs. TheARM946 serves as the master controller of the projector and
provides the link between the display screen and end-user controls such as a keypad and IR
remote control. These inputs can be processed in the ARM946 by OEM created software so
that commands can be issued to configure the DDP2000, the analog interface device, the
video decoder and other peripheral devices as desired.
The ARM946 utilizes a single external FLASH IC as the program memory. An optional SDRAM
may also be added externally for more demanding OEM software applications. For ease of
interfacing to peripherals the DDP2000 includes busses for USB, I 2 C, UART, SCP, IR devices, and
24 GPIO pins.
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Figure 1. TI Reference Design
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Figure 2. Circuit Block Diagram
Figure 3. Main Board
、 IR Board 、 Chip Board
Main Board
Input Board
Ballast
Chip Board Color Wheel
Sensor
IR ＆
Keystone
Keypad
Thermal
Sensor
Power Board
100 MSPS
A/D
convert
D-Sub in D-Sub out
Triple
vide
o
RGB analog signal
YPbPr analog
DDP200
0
DLP
Imag
e
Processor
RGB888
24bits
NTSC/PAL
/SECAM
Video
Decode
Y
UV422
16bits
Color
Whee
l
Motor
RAMBUS
RDRAM
DMD
Power
and
Reset
MBRS
16 M Flash
Memory
I
MXD2020E
F
Chip Board
IR Board
Color wheel
1.4.1.5.
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4.2. Power and Start-up
4.2.1. Power Supply Voltages
The DDP2000 TI reference design requires the following voltages and currents to be available:
Table 1. Power Requirements
Voltage Tolerance Current (min)
+12 VDC +/- 0.6 V 1.5 A (includes fan power)
+5 VDC +/- 0.25 V 1.5 A
+3.3 VDC +/- 0.165 V 3.0 A
4.2.2. On board voltage regulators
In order to make use of existing and standard power supplies, TI has chosen to generate the
following voltages in the reference design. For production implementations, OEMs may chose
to create these voltages as part of the power supply. Doing so will result in a requirement for
5V current and 3.3V current which is less that that shown above.
Table 2. Voltage Regulators on the
TI Reference Design Voltage Tolerance Current (max)
+2.5 VDC +/- 0.125 V 1.0 A
+1.8 VDC +/- 0.09 V 1.0 A
+1.5 VDC +/- 0.075 V 1.0 A
4.2.3. Power-up Sequence
All of the power supplies should be applied or removed simultaneously.
4.2.4. Recommended Operation Conditions
Signals which interface directly to the DDP2000 ASIC shall comply with the following
requirements: Please see the DDP2000ASIC data sheet for a complete description of
requirements.
4.2.5. Recommended Operation Conditions:
DC Supply Voltage to theASIC (VDD): 3.0 to 3.6 V
Voltage Levels to the I/O Buffers:
.... VIH: 0.8 * VDD minimum
.... VIL: 0.2 * VDD maximum
4.2.6. Performance of the I/O Buffers
.... VOH: VDD – 0.6 V minimum
.... VOL: 0.4 V maximum
.... Sink current: varies, see specific signals
.... Source Current: varies, see specific signals
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4.3. Graphics and DVI Inputs
4.3.1. AD9882
TI has chosen the AD9882 dual interface device fromAnalog Devices as the analog
interface for the first DDP2000 reference design. This choice was based on availability,
expected cost, the inclusion of DVI (with HDCP support) and the performance
characteristics as stated in the data sheet from Analog Devices.
Projector designers are encouraged to read and understand the data sheet for this device
which is available on theAnalog Devices web site.
This device operates under software control. Projector designers should review the
DDP2000 Software User’s Guide to obtain information pertaining to application software
used to configure the device.
4.3.2. Computer Graphics
Graphics inputs (up to 140 MSPS) are initially received by the AD9882 Analog Interface
device. This device digitizes analog RGB graphics into three 8-bit channels of red, green
and blue data. The three 8 bit RGB busses are routed directly to the DDP2000 for digital
processing.
Horizontal and vertical sync signals are buffered and routed to both the AD9882 and the
DDP2000. The DDP2000 uses the unprocessed sync signals as inputs to the autolock
function.
4.3.3. Component Video
The AD9882 can also support the A/D conversion of Standard and High Definition
(SD/HD) component video YPbPr signals from PC and video sources. The Y signal must
be connected to the G_Ain input. The Pb must be connected to B_Ain and the Pr must be
connected to R_Ain.
4.3.4. DVI inputs
The Digital Visual Interface (DVI) is an industry standard high speed data transfer
interface based on Transition Minimized Differential Signaling (T.M.D.S.). The AD9882
contains a DVI 1.0 receiver which supports display resolutions up to SXGA (1280 x 1024)
at 60 Hz.
The AD9882 includes support for High Bandwidth Digital Content Protection (HDCP) v
1.0. This feature allows for decryption of encoded data at the receiver, and renewability of
the authentication of the receiver during transmission.
4.3.5. Data Output Clock
The DATACK signal is the data output clock for both the analog an digital interfaces. This
signal is routed to the DP2000 as the Port 1 input clock.
4.3.6. High bandwidth Digital Content Protection (HDCP)
The TI reference design has incorporated the HDCP interface as detailed on theAD9882
data sheet. This interface includes the DDC_SCL (data clock) and DDC_SDAdata)
signals as well as the MCL (encryption key clock) and MDA (encryption key data) signals
from an external EEPROM (U32).
See the Analog Devices AD9882 data sheet for details on the ADI software license
agreement for HDCP.
4.3.7. Control Signals
The DDP2000 provides control signals to the AD9882 via a 2-wire serial control port (I2C).
The SCL (clock) signal is connected to SCL0 on the DDP2000. SDL (bidirectional data) is
connected to SDA0. See the AD9882 data sheet for timing information.
4.3.8. EDID
The TI reference design demonstrates the use of PROMs to communicate both analog
and digital EDID data. If the projector designer chooses to implement the DVI receiver
option, a digital EDID response is required when DVI data is the chosen input.
When the projector is used to receive analog graphics data, the analog EDID data is
available to the host system.
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4.4. Video Inputs
4.4.1. VPC3226E
TI has chosen the Micronas VPC3226E as the video decoder for the DDP2000 reference
design. The device was chosen based on availability, projected costs and the
performance characteristics as stated in the data sheet.
Projector designers are encouraged to read and understand the data sheet for this device
which is available on the Micronas web site.
This device operates under software control. Projector designers should review the
DDP2000 Software User’s Guide to obtain information pertaining to application software
used to configure the device
4.4.2. Composite and S-Video
Composite and S-Video inputs are initially received by the Micronas Video Pixel Decoder.
This device digitizes and decodes base-band analog video into digital component video.
The Micronas VPC3226E has four analog inputs which can be used for either
3 composite video sources or
2 Y/C sources (S-video) or
2 composite sources and 1 Y/C source.
Composite video can be either NTSC, PAL or SECAM.
The VPX3226E can decode and detect Macrovision 7.1 protected video.
The output of the decoder is programmable. The TI reference design will use the YCrCb
4:2:2 with separate syncs option in an 8 bit format and both port A and port B active.
4.4.3. Clock Signals
The VPX3226E generates a clock signal from a 20.25MHz crystal, shown on the
reference design as reference designator X1.
4.4.4. Pixel Clock
The TI reference design board can be configured to use either the PIXCLK or LLC clock
outputs from the decoder depending on the selected output data format.
4.4.5. Control Signals
The DDP2000 provides control signals to the VPX3226E via a 2-wire serial control port.
SCL (clock) is connected to SCL0 on the DDP2000. SDL (bidirectional data) is connected
to SDA0.
4.4.6. Reset
The RESZ input signal is connected to the system reset signal on the DDP2000.
4.4.7. Output Enable
The Output Enable signal for this device is hardwired to GP_IO pin 10 on the DDP2000.
Under software control, the output buses can be tri-stated.
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4.5. Clock Circuitry
4.5.1. Clocks
4.5.1.1. Reference Clock
The DDP2000 is designed to support both DRCG based Rambus™ memory operation
and DRCG-Lite Rambus™ memory operation.
4.5.1.2. DRCG
In regular DRCG operation, an external DRCG clock IC (CDCR83) aligns the Rambus™
memory channel clocks with an otherwise unrelated clock system inside the ASIC. This is
done by phase adjusting the Rambus™ memory channel clocks into alignment with an
external reference. In this case, an external 50MHz oscillator IC is required.
The DDP2000 ASIC uses a divide by 5 circuit to arrive at a 10 MHz reference clock for all
other timing.
4.5.1.3. DRCG-Lite
The DRCG-Lite Rambus™ memory clocking topology uses a special, lower cost “DRCG-Lite”
clock driver (CDCR61A) that derives the Rambus™ memory channel clocks from a
low cost 18.75MHz crystal, and provides no ability to phase align the Rambus™ memory
clock. Rather, it is assumed that the clocking system within the ASIC will align itself to the
Rambus™ memory channel. This is accomplished by using a PLL to phase lock the
internal 100MHz memory clock with the Rambus™ memory clock signal.
A second output of the DRCG-Lite is the LCLK which is configured to output a clock at ½
the input rate, or 9.375 MHz. The DDP2000, in the DRGC-Lite mode, uses the 9.375
MHZ clock for reset timing.
4.6. Lamp and Ballast
4.6.1. Lamp and Ballast Overview
The DDP2000 ASIC is compatible with a variety of lamp/ballast combinations. The
communication between the ballast and the DDP2000ASIC requires two signals, and may
also include a serial data link if the ballast is so equipped.
4.6.2. Discrete signals
The DDP2000 electronics can control a variety of DC and AC type lamp ballasts. The
DDP2000 electronics provides a lamp enable (LAMPEN) signal for lamp control and a
lamp lit (LAMPLITZ) signal for status from the lamp ballast.
4.6.3. Lamp Enable – LAMPEN
The DDP2000 electronics provides a lamp enable (LAMPEN) signal to control the projector
lamp and ballast. The LAMPEN is used for on/off control as well as synchronization of AC
lamps.
The state of LAMPEN after a reset is low. This is normally the off state of the lamp ballast.
Once PWRGOOD and RESETZ are high and the color wheel is spinning at speed, the
DPP2000 electronics drives the LAMPEN high. ForAC and DC ballasts it is assumed that
the lamp ballast will ignite the lamp when LAMPEN is driven from low to high. ForAC
lamps the ballast must drive the lamp with internal synchronization if LAMPEN is held high.
The LAMPEN signal can also be used to synchronize an AC lamp, once the lamp is lit and
stable. The DDP2000ASIC can output lamp synchronization timing on the LAMPEN. The
DDP2000 ASIC supports two types of lamp synchronization signaling:
.... Level
.... Rising edge
In the level synchronization mode, the level of the LAMPEN controls the direction of the
current to the lamp.
The second type of synchronization is referred to as rising edge. In this mode, the rising
edge of the LAMPEN causes the current to the lamp to alternate.
4.6.4. Lamp Lit – LAMPLITZ
The LAMPLITZ signal shall be asserted to the DDP2000 electronics after successful
ignition of the projector lamp. The transition of LAMPLITZ from high to low may be used
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to reset the DDP2000 electronics, so the LAMPLITZ signal must transition from high to
low after the lamp ignition EMI pulse is over to guarantee operation is not affected by the
ignition EMI. No DDP2000 electronics configuration should be attempted until LAMPLITZ
is low and stable.
When the lamp is disabled the LAMPLITZ shall be driven high. See Figure 2 for detailed
timing on the LAMPLITZ during power up.
Figure 2. Lamp Timing
4.6.5. UART Interface
Some manufacturers of lamp ballasts have provided a UART communication port on the
ballast. The DDP2000 has two UART ports, one of which can be used to support lamp
ballasts communications.
Please consult the lamp ballast manufacturer’s documentation for information on ballasts
pin assignments, data formats and functions.
Please see the DDP2000 Software User’s Guide for information on data types and
structures.
4.7. Peripherals
4.7.1. Peripherals Overview
Peripherals can be connected to the DDP2000ASIC via several communication paths.
Those include:
.... GPIO
.... USB
.... IR Sensor port
.... Power Monitor
.... UART
.... JTAG
.... Dedicated Test Points
4.7.2. General Purpose I/O
24 GPIO signals are available to deliver or send data to or from the ARM 946 processor in
order to monitor or control peripheral devices such as fans, temperature sensors, audio
amplifiers, keypads, etc. Each of the 24 pins is available as an input or an output. The
recommended operating conditions for these signals are given in section 2 and include
the following:
For GPIO signals GPIO_0 to GPIO_17
Sink current: 8 mA maximum
Source Current: 8 mA maximum
For GPIO signals GPIO_18 to GPIO_23
Sink current: 16 mA maximum
Source Current: 16 mA maximum
4.7.3. USB
The DDP2000 supports the universal serial bus version 1.1 in a slave mode only.
4.7.4. IR Sensor Port
There are two pins on the DDP2000 dedicated to IR Sensor inputs. Those pins,
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designated IR0 and IR1 have the following characteristics:
.... Voltage Level: LVTTL (3.3 VDC)
.... Maximum Frequency: 1 MHz
.... Typical Frequency: 2 KHz
.... Noise immunity: See the Software User’s Guide.
4.7.5. Power Monitor and Reset
There are 3 inputs to the DDP2000 ASIC used for initialization, reset, and power
monitoring.
POSENSE ("power on" sense) is a signal which must be generated by an external power
monitor IC, as shown in the reference design. POSENSE should be asserted low only
during initial application of power to the projector system. The DDP2000 is immediately
and ASYNCHRONOUSLY reset, without regard to the DMD status. The DMD mirror park
sequence is NOT performed in this case. The power-up initialization sequence requires
at least 165ms after POSENSE goes high. PWSENSE should remain low until the core
voltage is greater than 1.3V
PWRGOOD is a high true signal which indicates that all supplies are within operational
limits. Ideally this signal is generated near the front-end of the system power supply, so
that there will be some advance indication of power loss. When PWRGOOD goes low,
the DMD mirrors are "parked" prior to reset of theASIC and external devices. The time
required to "park" the DMD mirrors is typically 1 msec.
SYSRSTZ is a general purpose reset and causes the DMD mirrors to be "parked" prior to
reset of the ASIC and external devices. Atypical use of the SYSRSTZ signal is for
processor initialization following lamp ignition.
For a "normal" power down event, the system design must ensure that PWRGOOD (or
SYSRSTZ) goes low prior to POSENSE low, so that enough time exists for the mirror park
sequence to complete successfully.
4.7.6. UART
There are two separate UART ports on the DDP2000ASIC. Each port contains the
following signals:
.... UARTx_TXD: Transmit data
.... UARTx_RXD: Receive Data
.... UARTx_CTS: Clear to Send
.... UARTx_RTS: Ready to Send
Please see section 6 for details on using a UART to support a lamp ballast
communication path.
The recommended operating conditions for the TXD and RTS signals are given in section
2 and include the following:
Sink current: 16 mA maximum
Source Current: 16 mA maximum
The input buffers for the RXD and CTS signals have the following recommended
operating conditions:
High Level Input Current (IIH): -10 uA to +10 uA
Low Level Input Current (IIL): -10 uA to +10 uA
4.7.7. I2C
The DDP2000 supports an I 2 C bus up to 400 KHz. The dedicated pins are as follows:
.... SCL0
.... SDA0
For interface definition, please see the I 2 C bus specification.
The recommended operating conditions for these signals are given in section 2 and
include the following:
Sink current: 16 mA maximum
Source Current: 16 mA maximum
4.7.8. JTAG IEEE 1149.1 (JTAG) Test Port
The DDP2000 ASIC provides a standard IEEE 1149.1 (JTAG) test port. TI highly
recommends utilizing the JTAG port for in-circuit-test (ICT) board test.
4.7.9. Dedicated Test Points
Eight test points, TSTPT(7:0) are available. Those signals are routed from the DDP2000
to the Test Point header located on the reference design board. Each of the eight signals
is an output only. See the software User’s Guide for information regarding programming
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the DDP2000 to place specific data on each pin.
The recommended operating conditions for these signals are given in section 2 and
include the following:
Sink current: 4 mA maximum
Source Current: 4 mA maximum
4.7.10. Peripherals Used in the Reference Design
The list of peripherals that are demonstrated in the reference design is as follows:
.... Fans and Blowers (GPIO, PWM)
.... Temperature sensors (GPIO and I 2 C)
.... Infra-red sensors for remote controls (dedicated I/O)
.... Keypad for user inputs (GPIO)
.... Power monitor circuitry (dedicated power sensor signal)
.... In-Circuit Emulator (JTAG)
.... RS-232 (UART)
4.7.11. Fans and Blowers
Fan and blowers are used to regulate the temperature within the projector housing.
Simple units are only electrically connected to an appropriate power source. However,
more sophisticated operation can be achieved by varying the voltage to the fan.
The TI reference design contains an example of how to use a PWM signal from the
DDP2000 to pulse width modulate the fan input power. With this technique the average
input voltage to the fan can be regulated to be between 0% and 100% of the available
power.
Also, in this example, an output of the fan which indicates the fan is not rotating is routed
to a GPIO line.
4.7.12. Temperature Sensors
Temperature sensors can be located in key locations inside the projector and provide
feedback to the processor or the user. The system designer can choose to connect these
sensors via GPIO or I2C
In the reference design, TI has chosen a bimetal switch to indicate a lamp over
temperature condition to the DDP2000 via a GPIO signal.
4.7.13. Infra-red Sensors
The DDP2000 ASIC has two ports dedicated to IR sensor controls. Serial data from each
of the IR ports is routed to the DDP2000 ASIC.
4.7.14. Keypad for user inputs (GPIO)
In the TI reference design 6 GPIO signals are used to monitor the keypad.
4.7.15. ARM In-Circuit Emulator
In the reference design a 20 pin connector is provided for the ARM in-circuit emulator.
This is useful for software integration but is not expected to be on the product design.
Please see the TI reference design for connectivity.
4.7.16. ARM Embedded Trace
In the reference design a 38 pin connector is provided for the ARM Embedded Trace
function. This is useful for software integration but is not expected to be on the product
design. Please see the TI reference design for connectivity.
4.7.17. RS-232
In the TI reference design, one of the two UARTs from the DDP2000 is used as an RS-232
port. This usage requires a level shifter, TI has chosen a Max3232 for the reference
design, as well as a standard 9 pin serial connector.
Figure 1. Input Board
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S-Video CVBS
I
A
udio
Processor
Audio
OAudio I
Temp
GMT
G76
GMT
G768
Temp
DMD DMD Power Fan Blower Fan
BUFFER
XTAL
32.768K
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