Unitron U-2200 User manual

U 2200
U 2200
U-2200
U-2200
U-2200

Digitalizzazione di
Tiziano Garuti
www.1000bit.net
CONTENTS
CHAPTER 1INTRODUCTION ....•.......•..•.. PAGE 1
CHAPTER 2INSTALLATION
...........•...... PAGE 6
CHAPTER 3U·2200 OPERATION
..........••.... PAGE 8
CHAPTER 4VIDEO
..•••••..•...••...••..... PAGE 17
CHAPTER 5INPUT/OUTPUT
••••••......••..... PAGE 24
APPENDIX ••••••••••.•.•.••.••••.•••...• PAGE 33

UNITRON 2200 PERSONAL COMPUTER
The U·2200 is a CP/M~ compatible microcomputer. This manual covers
the infonnation on the config.n8tion. installation and operation. The bibliography
in APPENDIX Alists several references which may aid you in use of various
la~ages and operating systems.
CHAPTER 1
INTRODUCTION:
The U-2200 system has two major parts: Computer chassis and detached
keyboard. Acoiled cable connects between them.
In this manual all descriptions of direction are based on your facing the
machine, in fiG. '·1.
FIG. ,.,
On the front of the chassis, as shown in fiG. 1-2, there are apower indicator
and akeyboard connector.
FIG. 1-2
Front P8ne4
I

The rear panel has several connectors (Fig. 1-3) for Disk Drives, Video
Monitor, Cassette Recorder and Joy stick. required
to make afunctional computer. It also has 5extention slots compatible
with Apple
II peripherals. These slots are numbered #1, #3, #4, #5 and #7.
The chassis contains the computerboard and power supply. Open the cover
of chassis. and you will see the power supply on the ri~t side above the computer·
board. The power supply is ahigh frequency switching mode and proYides four
DC Voltages: +5V, +12V, -5V, -12V. The source of power can be either 110V
AC or 220V AC, switch selectable (FIG. 1-4). The output of power supply connects
to the computerboard via a G-pin connector. The connector pinout is shown in
Fig.ne 1-5.
FIG. 1-4
,...-------------------_.----------------------_ ~
1GND +12V -5V -12V +5V +5V:
, ,
~ - ----- --.--------------- -------- -- -. -_._~
GAME TAPE TAPE
I/O OUT IN
.[][].
220V 110V
VIDEO DRIVE
1
::[J]
DRIVE
2
FIG,1-6 Computerboard
VIDEO DISPLAY:
Display type: Memory mapped display
Displaymode: Text, Low-resolution Graphics, High.Resolution Graphics.
Text capacity:
960 characters (24 lines, 40 columns)
Character type: 5x7
dot matrix
Character_set: Upper/Lower case ASCII
Character modes: Nonnal, Inverse, Flashing
Graphics capacity: 1920 blocks (Low-Resolution)
in a 40 by 4S array.
53760 dots (High·Resolution)
in a2S0 by 192 array.
FIG. 1-5 Power Pinout
COMPUTERBOARD:
The U·2200
is asingle board computer. The computerboard (Fig. 1-6)
includes the 6502 and Z·80 microprocessors, RAM (Random Access Memory),
ROM (Read only Memory). IC's (Integrated Circuits) and other components
2
In the center of rear side of the computerboard there is ametal connector
marked "VIDEO". This connector allows you to attach a-rable between
the U.2200
and aclosed-<:ircuit video monitor. It
is afemale RCA phono jack. On the right
rear conner, there
is a 4·pin.connector (ie. auxiliary video connector) for an RF
"?odulator that can connect to either TV set or video mointor. The U-2200 has
Video soft-switch functions. If you have an SO-<:olumn card plugged in slot #3,
you can plug the output of an SO-<:olumn video into a2-pin Connector marked
"SO-<:ol input" giving you automatic video switching.
3

THE CASSETTE INTERFACE:
On the right of the rear edge of computerboard are two small black packages
labeled "Tape in" and "Tape out".
These are miniature earphone jacks into which you can plug two cables,
one for recording and the other for play back, which has apair of miniature
earphone plugs on each end. The other end of this cable can be connected to a
standard cassette tape recorder so that your U-2200 can save information on
audio cassette tape and read it back again_
THE DISK DRIVE CONNECTORS:
The U-2200 computerboard includes the disk controller's functions which
made by the advanced technology of PAL@ sequencer, so you can directly
connect two drives. The connectors are located at the rear left of the computer-
board. This controller lin dedicated slot #61 can drive two 5%" floppy disk drives.
If you wish to use more than two disk drives, plug extra disk interface cards in
extention slots and connect drives as you need.
THE GAME I/O CONNECTOR:
To the right of cassette connectors is a16-pin socket for game I/O. The
purpose of the Game I/O connector is to connect special input and outpUt devices
to enhance the effect of programs, especially in game programs. This connector
allows you to connect three one-bit inputs, four one·bit outputs, adata strobe,
and four analog inputs, all of which can be managed by your programs.
KEYBOARD:
The U·22OO has adetached keyboard which connects to the computerboard
with acoiled cable by a15·pin female connector. Most of your contact with
U·2200 will be through the keyboard. In the keyboard case there is an 8ohm
speaker controlled by asoft-switch. This soft·switch is associated with memory
location number 49200. Any reference to this address lor the equivalent address
-16336 or hexadecimal SC030HI will cause the speaker to emit aclick.
4
Keyboard
Number of Keys: 72
Coding: Upper/Lower case ASCII
Output: Seven bits plus strobe
Power requirements: +5V at 300 MA
Special key: Numeric Keypad and
function keys
FIG. '-7 Keyboard
VIDEO MONITOR
To operate the U-2200 system, you will also need avideo monitor or a
TV se~. If you do not have amonitor and your TV set does not have avideo input,
you Will need an RF modu!ator to modulates the video output signal on astandard
!V channel frequency for display on aTV receiver. Remember, when atelevision
IS u~d, the quality of the display will not be as good as the display on avideo
monitor.
5

CHAPTER 2
INSTALLATION:
There are four connections you must make. They are power. video outPUt,
keYboard, and disk drive. They are normally made on the computer rear panel.
The power supply
is 110/220V AC selectable. check your power source
and set the switch to suit. The power receptacle
is located in the upper right corner.
Insert the end
of the supplied power cord into this connector.
Video
output is provided at either the RCA connector or the 4-pin connector
for RF modulator. If anormal video monitor is being used, it can connect to
the RCA connector or the video CM,ltput of an RF modulator. If you use a ·TV
set, connect it to the RF output of an RF modulator.
The keyboard has acoiled cable ended with a15·pin O·type connector.
Plug this connector
to the male connector on the front panel.
On
the left rear of the computerboard are two 20-pin connectors for disk
drives. Connect
your master drive in the connector labeled "drive 1".
If the 80<:01umn card is used. plug it into slot #3, and the video output
of the 8O<:0lumn card connects to the 2-pin connector on the riltlt of slot #7.
The U·2200 provides an auto-switching function between 80/40 character Text
display.
If aprinter is used, plug the printer interface card into slot #1. Other cards
can be plugged into any
empty slots according to their instruction manuals.
GETTING STARTED
The U-2200
is adual processor computer system. Both the 6502 and Z-80
microprocessors are supported for full, compatible operation
in one computer.
Turn
the power' on after set-up. You will hear a "beep" from the speaker.
The screen
will show the message in FIG. 2-1.
6
UNIT RON DUAL PROCESSORS COMPUTER SYSTEM
WITH AUTO·BOOTING CP/M.
CONNECT
DISK DRIVE IN DRIVE 1CONNECTOR
AND INSERT
CP/M SYSTEM DISKETIE.
PRESS ANY
KEY TO START!
FIG. 2·'
If there i, no response or something strange happens, please turn the power
off and check
the following:
1: Keyboard connector and its direction.
2: Power connector and power source switch.
3: Video connector and 80<:01umn video if installed.
4: Peripheral cards
in slots.
5: Disk drive connections.
make sure every connection
is correct, then turn the power on again. If it still
does not work, press "control-reset"
or check the connections again.
Once the correct message appears on
the screen, insert the CP/M system
diskette into drive 1and press any key
to boot CP/M.
If amessage appears as FIG. 2-2, it means th'at the computer can not find
the disk controller. You can press any key to try again.
···CAN NOT FIND DISK CONTROLLER.
PRESS ANY
KEY TO RETRY
FIG. 2-2
The U-2200 has one
ROM on the computerboard. This ROM is a boater.
It boots the system from diskette.
The U·2200 has 24K
ROM space split into two banks, switched by soft-
switches. Referercing
the address $COAO will switch to bank 1, address $COAF
to bank O. You can add a ROM CARD for your applicatons.
7

CHAPTER 3
U-2200 OPERATION
The U-2200 is adual processor computer. Both the 6502 and Z-80
microprocessors are supported for full, compatible operation
in one computer.
All circuitry except the power supply is located on asingle computerboard.
~
•w•
0•0
•a•
•
~
a"
0•a
•w•
••a
~
~
awz
•aaa
SO·COLUMN a•;; u
MEMORY
TIMING
System timing is derived from the 14.318 MHZ crystal located at Al on
the computerboard.
Memory
in U-2200 consists of Random Access Memory (RAM), Read-only
Memory (ROM), and I/O locations. The memory map is shown as Fig. 3·2. The
RAM memory range $DOOO·$FFFF can be accessed like alan!J.lage carel. ROM
space is 24K and is split into 2banks. Softswitches are used to select the Bank
oor Bank 1 ROM area. (Table 3·21. Power-on initialization is in bank O.
VI EO
VIDEO
~
ADDRESSING
>TIMING
SIGNALS
"8O{40 COLUMN
~
~
0
•
•
w
~
VIDEO DATA
0
~
'---
VIDEO
tRAM H
RAM64K
MUX
ADDRESSING
LANGUAGE CARD
r-
CONTROL
KEYBOARD I--
ROM
I--
ZOO
6502
I--
ANALOG
PERIPHERAL I/O
12
~
•
-uw
w
~
~
"•
>w
w0
~
•"•
•a
•w
U"0
a0
Table 3·' TimingSignllb
Master oscillator output. Used to derive other timing signals.
7.159MHz timing signal.
1.023 MHZ phase 0system clock. Complement to ;1. Sometimes
referred
to as;2 in other literature.
1.023
MHZ phase 1system clock.
General purpose timing signal. Twice the fre(JJency of the system
clocks.
but asvmmetrical.
DESCRIPTION
~1
03
The video cootrol and addressing signals are also generated by this circuitry. Video
generation consists
of 192 scan lines on the video screen. These are grouped into
24 lines of eight scan lines each. Fifteen synchronization signals are used. They
consist of
"H" (Horizontal) and "V" (Vertical) groups of signals. The va throu!tl
V4 signals are used to define the vertical line position on the screen. The Va
through Vc signals are used to define the vertical scan line position within the
vertical screen line.
SIGNAL
14M
7M
i>O
FIG.3·' System Block Diagram
89

$6000 ..........••.....•••......•••••.................••..
~ HGR2
$4 .....•••...••••...••......•••....................••.
$FFFF '.' .
$DFFF
~~~ .....•..... ~~~ ~~O .
$0000 ~?~ ~?~ ~~ ~~?~ _
$Cooo ..................•.................. I~~ .
$2000 .....•.....••.....•••......•......... ~~~~ .........••
SOBFF ...........•.......•.......•.•...................••
$0800 .....••......•••....•••.•....•••..... ~~~~~ .......••.
$0400 ......•.•....•.......•......••....... ~~~~' .........••
ROMl SELECT 1
28
ROM2 SELECT
2
27
BANKO!BANKl 3
26
A'2
A7
•
25
vee
A6
5 2.
A8
A5
6
23
A.
A'
All
A3
7 22
DE
A2
8
21
AID
A' •
20
eE
10 I.
AD
11
'8
07
00
06
01
12 17 05
13 16
02
"
15
D.
GNO 03
booter ROM. aligmented at the bottom. which will boot CP/M. It will also accept
the
ROM CARD to use the 24K ROM space. The socket pinout is shown in Fig
3-5. Table 3-6 is the description of the signals.
RAM
ROM
BANK 1
ROM
BANKO
ADDRESS
Table
3·2 Soft Switch Address for ROM Selection
FIG. 3-2 System Memory Map
$0200 ......••......•......••......••.................•.••
STACK
SOl00
..............•..... _ ••.•....••.. _ _.
SYSTEM
USE
$0000 , " .
FIG. 3-5
Description
Table 3-6
Active Lo when the address is $FOOO-$FFFF of BANK 1.
Active Lo when the address is SDOOO-5EFFF of both
banks.
Active
Lo when the address is SFOOO·SFFFF of bank O.
The Booter ROM is enabled by this two signals.
Hi when in Bank O.
Lo when is Bank 1.
Address Bus.
Data Bus.
CE,
DE
BANK O/BANK 1
ROM1 SELECT
ROM2 SELECT
AO·A12
00·07
Signals
$COAO
BANK 1
SCOAF
BANKO
Address
LANGUAGE CARD AREA:
The upper
16K of RAM appears as aLanguage card. Soft switches are used
to enable and disable
ROM and RAM in this address range and are effective for
whichever bank of
ROM is selected. The architecture is such that there are two
4K block of RAM in the SD~-$DFFF memory range.
The system uses
eig,t 4164 dynamic RAM's located in positions E4-El'.
In location F8. there is 28-pin socket for ROM space. This will accept the 24-pin
6502
The 6502 is adynamic microprocessor operating at 1.023 MHz clock rate.
It uses the address and data busses only when the tflJ signal is high or active. When
¢O is low, the microprocessor is doing internal operations and does not need the
address and data busses.
10
11

Z-80
The l-BO microprocessor is located on the computer board and is buffered
to the address and data busses. The Z·80 is configured to allow direct execution
of 8080 and l-BO programs and operate under the CP/M operating system. The
computer supports a56K CP/M confi!J.Iration.
TIMING
ADDRESS BUS INTERFACE
The Z·BO address bus interface is constructed such that the memory conflicts
that exist between the 6502 based system and conventions used by the Z·80
microprocessor and
CP/M are resolved. Table 3·7 shows how memory appears
to the Z·80 versus normal 6502 configJration.
Tlible
3--7
PERIPHERAL I/O
Note
that the Z-80 can address cootigJous memory from $OOOO·$DFFF
without accessing the 6502's Zero page of memory or the peripheral I/O memory
area.
Along
the rear side of the computerboard are five peripheral I/O connectors.
These connectors are used for peripheral interface boards designed for the U-2200
or the Apple II Computer. Peripheral Board I/O space has been set aside for use
with each
of the five slots and there is also a2K common area for use by any
of the boards installed.
,The 2-80 is svr:chronized and phase locked to the 6502 clocks. During
the, video refresh period,
411, the 7 MHZ clock is divided into three half clock
perrods
of 135 nanoseconds. The first half·dock is high the second is low and
the third
is high. At the end of the third half clock the sig'nal goes low and re~ains
low until the start of the next tP1. Thus, the Z·80 clock is low during all of tfAJ
and asmall part of ,1. This timing scheme creates an effective 2-80 clock rate
of 2.041 MHZ.
Each type. of ~achi~e cycle contains one memory access period during
¢(J. The. read/wr~te signal IS synchronized ensuring that the write can only go
tow during the time the 2-80 clock is high. Because all address transitions from
t~e Z·80 occur when the clock is high, they must all occur during ¢l while the
Video update access is occurring. Thus, each ¢(J has stable addresses on the bus
for
the entire duration of the cycle.
CONTROL
The Z-80.
is contr~lIed by write commands to the area of memory that
normally contains aperipheral ROM. It is nec:essay to use write commands to
ensure that the 6502 will not perform two accesses in succession which would
prevent switching back
to the 6502. •
When the U·2200 power
is turned on, the RESET signal forces the Z.80
to
the off state. The RESET signal is synchronized to the system clock to ensure
~at awrite operation cannot be interrupted. The Z-80 is immediately placed
In the WAIT mode and remains in this mode until activated.
Upon receipt of awrite to the SC2oo-SC2FF area the Z-80 is enabled
The Z·80 remains
in the wait mode until one memory dycle occurs with z-aO
address infonnaton on the bus. At this point the Z-80 is allowed to run with
no further wait cycles required. Receipt
of another write to the $C200.$C2FF
area
of memory, by the Z-80. will return the Z·80 to the WAIT mode.
2-80 address
$0000 -$OFFF
$1000 -$1FFF
$2000 - $2FFF
$3000 - $3FFF
$4000 -$4FFF
$5000 -S5FFF
$6000 - $6FFF
$7000 - $7FFF
$8000 - $8FFF
$9000 - $9FFF
$AOOO - $AFFF
$BOoo - $8 FFF
$COOO -$CFF F
$0000 - $OFFF
$EOOO - SE FF F
SFOOO -$FFFF
6502 address
$1000 - $1 FFF
$2000 -$2FFF
$3000 - $3FFF
$4000 - $4FFF
$5000 - $5FFF
$6000 - $6FFF
$7000 - S7FFF
$8000 -$8FFF
$9000 - $9FFF
$AOoo - $AFFF
$8000 -$8FFF
$0000 - $OFFF
$EOOO - $EFFF
$FOOO-$FFFF
$COOO -$CFFF
SOOOO -SOFFF
12 13

Each of the slots is numbered. They are #1, #3, #4, #5 and #7. Each of
the five 5O-pin connectors is individually selected by control circuitry. Table
3·8 provides detail on the signals available
at these connectors. The pinout is
shown in FIG. 3-6.
I/O SELECT This signal
is normally high. It becomes low during
q,o when areference is make to SCnXX, where 'n' is
the slot number.
29
PIN
2-17
18
SIGNAL
AO·A15
RIW
Table 3-8 peripheral I/O signal descriptions
DESCRIPTION
The buffered address bus. The address on these pins
becomes valid through ¢(J.
Buffered ReadflNrite signal. This signal become valid
the same time the address bus does, and goes high during
aread cycle and tow during awrite cycle.
30
31
32
33
34
RES
-12V
-5V
Non.Maskable Interrupt. When this line is pulled low
the U-2200 begins an. interrupt cycle.
Interrupt Request. When this line
is pulled low the
U-2200 begins an interrupt cycle if 6502's interrupt
disable (I) flag
is not set.
When this line is pUlled low the 6502 begins aRESET
cycle.
This line
is ainput signal from peripheral cards. When
this line
is pulled low the ROM address range of $0000-
$FFFF is disabled on the slots.
-12 volt powtlr supply, 0.5 Amps is available for all
peripheral slots.
-5 volt power supply, 0.5 Amps is available for all
peripheral slots.
I/O STROBE Normally high, this line goes low during ¢(J when
the
address bJs contains an address between $caoo and
$CFFF.
50 +12V
42-49 DO·D7
40 '"
~~
41 DEViCE
SELECT
Phase 0clock.
This signal becomes active -low, on aconnector when
the address bus holds an address between SCOnO and
$cOnF, where
'n' is the slot number plus $B.
Buffered bidirectional data bus. The data on these lines
become valid
300 nsec into ¢(J on awrite cycle, and
should be stable no less
_~an 100 nsec before the end
of q,o on aread cycle.
+12 volot power supply,
'2:.5 Amps is available for all
peripheral slots.
7
MHZ clock.
Asymmetrical 2
MHZ clock.
Phase 1clock.
When this line is pulled low, all $COXX-C7XX address
decoding
is inhibited.
7M
OJ
,11
USER 1
36
37
38
39
Daisy-<:hain interrupt output to lower priority devices.
This pin
is usually connected to pin 28 (lNT IN).
Daisy chain
DMA output to lower priority devices.
This pin
is usually connected to pin 27 (DMA IN).
+5V volt power supply. 3Amps
is available for use
at the peripheral slots.
System electrical ground.
Daisy-<:hain DMA input from hiltler priority devices.
Usually connected
to pin 24.
The
6502's RDY input. This signal is going low during
1/11 halts the 6502 with the address bus holding the address
of the current location being fetched.
Pulling this line low disables the 6502's address bus
and halts
the 6502. The line is held high by a 1Kohm
resistor to +5V.
DMA OUT
ROY
INTOUT
GROUND
DMAIN
+5V
21
20
24
25
22
26
27
23
28
INT IN Daisy-<:hain interrupt input from higher priority devices.
Usually connected
to pin 23 (INT OUT).
14
IS