Vector Graphic VECTOR 1 MOTHERBOARD User manual

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U)iS=I) mAnUAL

REPAIR AGREEMENT
The Motherboard sold hereunder is sold lias is
lt
, with all faults and
without any warranty, either expressed or implied, including any
implied warranty of fitness for intended use or merchantability.
However, the above notwithstanding, VECI'OR GRAPHIC, INC., will, for a
period of ninety (90) days following delivery to customer, repair or
replace any Motherboard that is found to contain defects -in materials
or workmanship, provided:
1. Such defect in material or workmanship existed at the time
the Motherboard left the VECTOR GRAPHIC, INC., factory;
2. VECTOR GRAPHIC, INC., is given notice of the precise
defect claimed within ten (10) days after its discovery;
3. The Mbtherboard is promptly returned to VECTOR GRAPHIC,
INC., at customer's expense, for examination by VECTOR GRAPHIC, INC.,
to confirm the alleged defect, and for subsequent repair or
replacement if found to be in order.
Repair, replacement or correction of any defects in material or
workmanship which are discovered after expiration of the period set
forth above will be performed by VECTOR GRAPHIC, INC., at Buyer's
expense, provided the Motherboard is returned, also at Buyer's
expense, to VECTOR GRAPHIC, INC., for such repair, replacement or
correction. In ~rforming any repair, replacement or correction after
expiration of the period set forth above, Buyer will be charged in
addition to the cost of parts the then-current VECTOR GRAPHIC, INC.,
repair rate. At the present time tpe applicable rate is $35.00 for
the first hour, and $18.00 per hour for every hour of work required
thereafter. Prior to commencing any repair, replacement or correction
of defects in material or ~rkmanship discovered after expiration of
the period for no-cost-to-Buyer repairs, VECTOR GRAPHIC, INC., will
subnit to Buyer a written estimate of the ex~cted charges, and VECTOR
GRAPHIC, INC., will not commence repair until such time as the written
estimate of charges has been returned by Buyer to VECTOR GRAPHIC,
INC., signed by duly authorized representative authorizing VECTOR
GRAPHIC, INC., to commence with the repair work involved. VECTOR
GRAPHIC, INC., shall have no obligation to repair, replace or correct
any Motherboard until the written estimate has been returned with
approval to proceed, and VECTOR GRAPHIC, INC., may at its option also
require prepayment of the estimated repair charges prior to commencing
work.
Repair Agreement void if the enclosed card is not returned to VECTOR
GRAPHIC, INC. within ten (10) days of end consumer purchase.

SUBJECT
PARTS LIST
FEATURES
PARTS LAYOUT DRAWING
S-100 BUS LISTING
WARRANTY
VECTOR 1 MOrHERBOARD
TABLE OF CONTENTS
PARI'S LIST
PAGE
BELOW
1
1
2
(]rY.
1
2
1
1
1
41
41
DESCRIPI'ION
PRINTED CIRCUIT BOARD
820 OHM 1 WATl' RESISTORS (STRIPES OF GRAY, RED, BRCWN)
100 ~ 2 WATl' RESISTORS (STRIPES OF :BRa'JN, BLACK, BRCMN)
7805/340T-5 REGULATOR
*6- 32X3/8 SCRE.W, NUT AND LOCKWASHER
330 OHM 1/4 WATl' RESISTORS (STRIPES OF ORANGE, ORANGE, BRCWN)
470 OHM 1/4 WATT RESISTORS (STRIPES OF YELLCW, VIOLET, :BR.CMN)

MOrHERBOARD USERS MANUAL
THE VECTOR 1 MOTHERBOARD HAS 18 SLOTS, IS BASED ON THE POPULAR S-100 BUS
STRUCTURE AND IS DESIGNED TO PROVIDE A NUMBER OF FEATURES NOT PREVIOUSLY
AVAILABLE.
IN ACCORDANCE WITH VECTOR GRAPHIC INC.'S COMMITMENT TO HIGH PERFORMANCE
STANDARDS AND TOP QUALITY PRODUCTS, OUR MOl'HERBOARDS ARE NOil SUPPLIED w-rTH BUS
TERMINATORS. WITH THE INCREASED USE OF LCltJ EaVER SCHDrrKY TTL AND ITS REDUCED
NOISE IMMUNITY, BUS TERMINATION BECOMES A DESIRABLE FEATURE. Nor TO BE CONFUSED
WITH SO CALLED "ACTIVE" TERMINATORS, FULL TIME TERMINATION IS PROVIDED.
FEATURES
MOST :EQPULAR "ALTAIR/IMSAI" S-100 BUS STRUcrtJRE
CAN BE USED 'IO RETROFIT YOUR SECTIONED ALTAIR MOI'HERBOARD
:EOSITIONS FOR 18 .125" X 0.25" 100 PIN EDGE CONNECTORS
ACCEPl'S EITHER SOLDER PINS OR WIRE WRAP PINS
MOST :EQPULAR 0.25" CENTER 'IO CENTER SPACING BE~EN PIN ROilS
0.75" CENTER 'ID CENTER SPACING BE'IWEEN CONNECIDRS
EXTRA HEAVY 0.93" WARP RESISTANT, AEROSPACE QUALITY G-10 E:EQXY BOARD
FULL GROUNDPLANE REDUCES mISE CN BUS LINES
PLATED THROUGH HOLES FOR MORE RELIABLE CONNECTIONS
TRACES CN BPl.CK OF BOARD CNLY
LESS RISK OF SHORTS FROM CONDUCTIVE ITEM BEING INADVERTENTLY DROPPED DURING
OPERATION
MUCH EASIER'ID TROUBLE SHOOT
REDUCED CAPACITANCE BE'IWEEN TRACES
SOLDER MASKED ro REDUCE RISK OF SOLDER BRIDGES DURING ASSEMBLY
BUS TERMINATION
l?C:WER RATING: 20 A FOR +8 VOLT TRACE; 25 A FOR +16V TRACES
BOARD SIZE IS" X 8.5"
PAGE

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OPTIONAllYOlTAGE
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MOI'HERBOARD USERS MANUAL
BUS TERMINATION
THE TERMINA'IDRS PROVIDED ARE 330 OHM RJLL-UP (TO +5V) AND 470 OHM RJLL-DOWN (TO
GNU) •
TABLE 1
LINES TERMINATED
24 - 2
25 - 1
29 - AS
30 - A4
31 - A3
32 -Al5
33 -Al2
34 - A9
35 - 001
36 - DOO
37 - AlO
38 - 004
39 - DOS
40 - 006
41 -012
42 -013
43 -017
47 - SMEMR
49 - CLK
54 -EXT CLR
68 - MWRITE
76 - PSYNC
77 - BNR
78 -IDBIN
79 - AO
80 -Al
81 -A2
82 - A6
83 - A7
84 -A8
85 -AI3
86 - A14
87 - All
88 - 002
89 -D03
90 - 007
91 -014
92 -DIS
93 -016
94 - 011
95 -010
PAGE 3

48 49
o0o
98 99
- ---- ......... -----,---- ---
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-~~~~-------------~
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2 3
o0
00
52 53
-
48 49
0·.
. ..-
98 99 ....
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f
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GND
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--~--_ .... ----.--...- ..... -~_ ..... ---
••••••
3 4
'-0
- 0 0
53 54
PAGE 4

S-100 BUS
STATUS BUFFER DISABLE
COMMAND/CONTROL BUFFER DISABLE
INPUT TO MEMORY PROTECT CIRCUITRY ON MEMORY BOARD
INDICATES MACHINE IS IN SINGE STEP MODE
ADDRESS BUFFER DISABLE
DATA OUT (FROM CPU) BUFFER DISABLE
PHASE TWO CLOCK TTL LEVELS
PHASE
ONE CLOCK TTL LEVELS
HOLD ACKNOWLEDGE. BUFFERED 8080 OUTPUT
UNREGULATED INPUT TO +5V REGULATORS
UNREGULATED INPUT TO +12V REGULATORS
ANDED WITH PRDY AND GOES TO 8080 RDY
VECTORED INTERRUPT REQUEST 0
VECTORED INTERRUPT REQUEST 1
YECTORED INTERRUPT REQUEST 2
VECTORED INTERRUPT REQUEST 3
VECTORED INTERRUPT REQUEST 4
VECTORED INTERRUPT REQUEST 5
VECTORED INTERRUPT REQUEST 6
VECTORED INTERRUPT REQUEST 7
XRDY
'1710
VII
VI2
'1713
'1714
VIS
VI6
'1717
XRDY2
6.
1. +8V
2. +16V
3.
4.
5.
7.
8.
9.
10.
II.
12.
13.
14.
15.
16.
17.
18. STA DSB
19. cJc DSB
20", UNPROT
21. SS
22. ADD DSB
23. DO DSB
24" if/2
25" ifll
26" PHLDA
PAGE 5

27.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
42.
43.
44.
45.
46.
47.
48.
49.
50.
, 51.
52.
54.
PWAIT
PINTE
A5
A4
A3
A15
A12
A9
DOl
DOO
AIO
D04
DOS
D06
DI2
DI3
DI7
SMI
SOUT
SINP
SMEMR
SHLTA
CLOCK
GND
+8V
-16V
SSW DSB
EXT CLR
WAIT ACKNOWLEDGE, BUFFERED 8080 OUTPUT
INTERRUPT ENABLE, BUFFERED
8080 OUTPUT
BUFFERED ADDRESS
LINE S (32)
BUFFERED ADDRESS LINE 4 (16)
BUFFERED ADDRESS LINE 3 (8)
BUFFERED ADDRESS LINE 15 (32768)
BUFFERED ADDRESS LINE 12 (4096)
BUFFERED ADDRESS LINE 1 (2)
BUFFERED DATA OUT LINE 1
BUFFERED DATA OUT LINE a
BUFFERED- ADDRESS LINE 10 (1024)
BUFFERED DATA OUT LINE 4
BUFFERED DATA OUT LINE 5
BUFFERED
DATA OUT LINE 6
DATA INPUT LINE 2
DATA INPUT LINE 3
DATA INPUT LINE 7
LATCHED 8080 MI STATUS
LATCHED
8080 OUT STATUS
LATCHED 8080 INP STATUS
LATCHED
8080 MEMR STATUS
LATCHED 8080 HLTA STATUS
2
MHZ CLOCK, CRYSTAL CONTROLLED
LOGIC
AND POWER GROUND RETURN
UNREGULATED INPUT
TO +5V REGULATORS
UNREGULATED INPUT
TO NEGATIVE REGULATORS
SENSE SWITCH DISABLE
CLEAR SIGNAL
FOR I/O DEVICES
PAGE 6

55. RTe
56. STSTB
'57. DIGI
FRDY
01.
62.
63.
64.
65.
66.
48K REFRESH
67.
PRANTOM
68. MWRT
69.
PS
70. PROT
71.
RUN
72. PRDY
73"
PTI'fT
74. PHOLD
75.
PRESET
76.
PSYNC
77.
PWR
18 ..
PDBIN
19.
AO
80.
Al
81.
A!
82.
A6
REAL TIME CLOCK OR 48K FAST RESET
STROBE SIGNAL (BY 8224 CLOCK CHIP 8800B Dlc BOARD)
ENABLE SIGNAL FOR CPU DI DRIVERS 8800B
880013 FRONT PANEL READY SIGNAL
WRITE ENABLE SIGNAL FOR MEMORY
INDICATES IF
ADDRESSED MEMORY
IS
PROTECTED
HiPUT
TO
MEMORY
PROTECT
CIRCUITRY
ON MEMORY
BOARD
INDICATES
MACHINE
IS
IN RUN
MODE
AND ED
WITH X"~DY AND
GOES
TO
8080
RDY
HTPUT TO
8080 INTERRUPT REQUEST
INPUT
TO 8080
HOLD
REQUEST
CLEAR SIGNAL
FOR CPU
BUFFERED
8080
SYNC SIGNAL
BUFFERED 8080 WRITE
ENABLE SIGNAL
BUFFERED
8080 BDIN SIGNAL
BUFFERED ADDRESS
LINE
a
(1)
BUFFERED ADDRESS LINE 1
(2)
BUFFERED ADDRESS
LINE
2
(4)
BUFFERED ADDRESS
LINE 6
(64)
PAGE
7

83. Ai BUFFERED ADDRESS
LINE i (128 )
84. A8
BUFFERED
ADDRESS
LINE
8
(256)
85. A13 BUFFERED AnnRES S
LINE 13
(8192)
86. A14 BUFFERED
ADDRESS
LHTE
14
(16384)
87. All
BUFFERED
ADDRES S LINE
11
(2048)
88. DOZ
BUFFERED
DATA
OUT
LINE
2
89. D03 BUFFERED
DATA
OU~ LINE
3-
90. DOi BUFFERED
DATA
OUT
LINE
7
91.
1'14 DATA INPUT
LINE
4
92. DIS DATA INPUT LINE
5
93. D16
DATA INPUT
LINE 6
94. DIl DATA
INPUT
LINE
1
95.
DIO
DATA INPUT.
LINE a
96.
SINTA LATCHED 8080
INTA STATUS
97- sUO
LATCHED 8080
ilO STATUS
98.
SSTACK
LATCHED 8080 STACK
STATUS
99.
PO'C
La
DURING
POWER UP, RESET
100.
GND
LOGIC
AND
FmlER GROUND RETURN
Q • PHI
PAGE 8