Vector graphic 48k dynamic memory board User manual

Y8K

Dynamic

Memory

Board

-----,

I

.~

(!

.,~Ci:O=t

~=tAi'l-iC

inc.

DYNAMIC MEMORY BOARD

Revision

3

February

7,

1979

:opyright

1979

Vector

Graphic

Inc.

Copyright

1979

by

Vector

Graphic

Inc.

Revision

Numbers

The

revision

number

and

date

of

release

of

each

page

!1erein

at

the

bottom

of

each

page.

The

revision

number

and

date

of

on

t

he

Title

page

corresponds

to

that

of

the

page

most

r

revi

sed.

Revision

3 -

2/7/78

REPAIR

AGREEMDIT

The

48K

Dynamic

RAM

Board

sold

hereunder

is

sold

"as

is",

with

all

faults

and

without

any

warranty,

either

expressed

or

implied,

including

any

implied

warranty

of

fitness

for

intended

use

or

merchantability.

However,

the

above

notwithstanding,

VECTOR

GRAPHIC,

INC.,

will,

for

a

period

of

ninety

(90)

days

following

delivery

to

customer,

repair

or

replace

any

48K

Dynamic

RAM

Board

that

is

found

to

contain

defects

in

materials

or

workmanship,

provided:

1.

Such

defect

in

material

or

workmanship

existed

at

the

time

the

48K

Dynamic

RAM

Board

left

the

VECTOR

GRAPHIC,

INC.,

factory;

2.

VECTOR GRAPHIC,

INC.,

is

given

notice

of

the

precise

defect

claimed

within

ten

(10)

days

after

its

discoverYi

3.

The

48K

Dynamic

RAM

Board

is

promptly

returned

to

VECTOR

GRAPHIC,

INC.,

at

customer's

expense,

for

examination

by

VECTOR

GRAPHIC,

INC.,

to

confirm

the

alleged

defect,

and

for

subsequent

repair

or

replacement

if

found

to

be

in

order.

Repair,

replacement

or

correction

of

any

defects

1n

material

or

workmanship

which

are

discovered

after

expiration

of

the

period

set

forth

above

will

be

performed

by

VECTOR GRAPHIC,

INC.,

at

Buyer's

expense,

provided

the

48K

Dynamic

RAM

Board

is

returned,

also

at

Buyer's

expense,

to

VECTOR

GRAPHIC,

INC.,

for

such

repair,

replacement

or

correction.

In

performing

any

repair,

replacement

or

correction

after

expiration

of

the

period

set

forth

above,

Buyer

will

be

charged

in

addition

to

the

cost

of

parts

the

then-current

VECTOR GRAPHIC,

INC.,

repair

rate.

At

the

present

time

the

applicable

rate

is

$35.00

for

the

first

hour,

and

$18.00

per

hour

for

every

hour

of

work

required

thereafter.

Prior

to

commencing

any

repair,

replacement

or

correction

of

defects

in

material

or

workmanship

discovered

after

expiration

of

the

period

for

no-cost-to-Buyer

repairs,

v~CTOR

GRAPHIC,

INC.,

will

submit

to

Buyer

a

written

estimate

of

the

expected

charges,

and

VEc'rOR GRAPW'::,

INC.,

will

not

commence

repa.ir

until

such

time

as

the

written

estirn:::lce

of

charges

has

been

returned

by

Buyer

to

VECTOR

GRAPHIC,·

INC.,

sj

gned

by

duly

authorized

representative

authorizing

VECTOR

GRAPHIC,

INC.,

to

commence

with

the

repair

work

involved.

VECTOR GRAPHIC,

INC.

I

shall

have

no

obligation

to

repair,

replace

or

correct

any

48K

Dynamic

RAM

Board

until

the

written

estimate

has

been

returned

with

approval

to

proceed,

and

VECTOR

GRAPHIC,

INC.

I may

at

its

option

also

require

prepayment

of

the

estimated

repair

charges

prior

to

commencing

work.

Repair

Agreement

void

if

the

enclosed

card

is

not

returned

to

VECTOR

GRAPHIC,

INC.

wi

thin

ten

(10)

days

of

end

consumer

purchase.

Vector

Graphic

48K

Dynamic

RAM

Rnn~~

TABLE OF CONTENTS

Section

rrable

of

Contents.

.............................

1.

Introduction

•.

1.1

1.2

Description

of

the

Board

•••

this

Manual.

••.•

1

••••

2

. 2

••

2

II.

Theory

of

Operation

.................................

3

2.1

2.2

The

Circuitry

•••..••.••.••••.

48K

Board

Refresh

Feature

of

the

Z-80

Board

•..

••

3

. • •4

III.

User's

Guicle...................................

.6

IV.

V.

VI.

3.1

3.2

3.3

3.4

3.5

Modifications

to

the

48K

Board

Z-80

Board

•••••.•.••..••

The

3.1.

1

3.1.

2

READY

Refresh

Signal.

Reset

Circuitry.

Li

ne

•••••••

Using

D~lA

.......

II

......

Address

of

the

Board.

Memory

Test.

.........

Spec:.fications

.•••••

Memory

Chip

Locations

•.

Schematic

•••.••••••••••

nevision

2

1/

12

/78

and

the

.6

'7

.8

• • • 8

.8

..10

.11

••

12

1

Vector

Graphic

48K

Dynamic

R.AN

Board

2

I.

INTRODUCTION

!~_l_~Description

of

the

Board

The

Vector

Graphic

48K

Dynamic

Memory

Board

provides

49,152

8-bit

bytes

of

random

access

memory,

using

24

16K

dynamic

memory

chips.

It

can

be

used

in

ANY

S-lOO

bus

computer

using

a

Z-80

CPU

board.

(Minor

modifications

may

be

necessary.

See

Section

III,

"User's

Guide",

below.).

It

occupies

the

lower

48K

of

memory,

i.e.

beginning

at

OOOOH.

The

Vector

Graphic

48R

Dynamic

Memory

Board

is

clearly

a

Lreakthrough

in

cost

effectiveness.

This

is

accomplished

by

cumbining

compact

inexpensive

dynamic

memory

chips

wi

th

the

use

of

the

refresh

provisions

of

the

Z-80

CPU.

The

most

recent

static

RAM

boards

cost

considerably

more,

take

up

more

space,

and

require-more

power.

Other

dynamic

memory

boards

use

complex

support

logic

on

the

board,

rather

than

the

built

in

features

of

the

Z-80.

In

3ddition

to

the

above

features,

the

Vector

Graphic

Dynamic

Memory

Board

has

proven

to

be

remarkably

reliable.

Considerable

attention

was

given

during

design

of

the

board

to

the

elimination

of

noise.

It

features

a

gridded

ground

plane

designed

to

reduce

noise.

Accepted

design

practice

was

observed

in

structuring

grounds,

power

supply,

und

bypass.

1.2

Description

of

the

Manual

This

manual

provides

a

general

description

of

the

Vectcr

Graphic

Dynamic

Memory

Board,

a

more

detailed

discussion

of

the

theory

of

operation,

and

information

on

how

to

use

and

test

the

board.

Since

the

board

is

not

sold

as

a

kit,

assembly

information

and

parts

list

are

not

included.

ru;vision

1 -

1/3/7tl

3

II.

THEORY

OF OPERATION

2.1

The

48K

Board

Circuitry

'i'

h

eVe

c

tor

G

rap

h i c 4 8 K DYn

ami

c

Me

In 0 r y

Boa

r d

use

s

the

ref

res

h

provisions

of

the

Z-80

CPU

board,

which

greatly

simplifies

the

support

logic

circuitry

on

the

board.

1\

Inemory

reference

cycle

beC]ins

with

the

CPU

board

sending

the

address

over

AO-AIS.

Each

of

the

memory

chips

contains

16K

bits,

so

14

address

bits

must

be

supplied

to

the

chips.

This

is

done

by

time

multiplexing

7

address

inputs.

Initially

the

low

order

7

addresses

arr~

applied

to

the

chip

address

inputs

by

U39.

After

the

address

lines

have

had

time

to

settle,

the

CPU

board

issues

a

memory

read

signal

on

SMEMR

or

a

write

signal

in

MWRITE.

This

signal

propagates

d,)wn a

chain

of

inverters

in

U13

to

initiate

a

timing

sequence

which

does

the

following

things

in

order:

1.

Generates

a

low

going

RAS

strobe

for

the

appropriate

memory

block

which

is

selected

by

U35

and

~ates

Ull

and

U23.

This

strobe

latches

the

address

bits

internally

in

the

memory

chips.

2.

Disables

U39,

a

tri

state

driver.

3.

Enables

U38,

applying

the

high

order

7

address

lines

to

the

chips.

-

4.

Generates

a

low

going

CAS

strobe

which

latches

the

addresses

in

the

memory

chips

and

initiates

a

timing

sequence

in

the

chip

to

enable

the

output

drivers

if

it

is

a

read

cycle,

or

to

write

the

data

into

the

selected

memory

location

if

it

is

a

write

cycle.

If

the

cycle

is

a

read

cycle

or

Ml

cycle,

the

logic

associated

with

U43

enables

the

bus

driver

U41

to

place

the

memory

data

on

the

Dl

bus

to

be

read

by

the

CPU.

If

the

cycle

is

a

write

cycle,

data

on

the

DO

bus

is

buffered

by

U40

and

made

available

at

the

data

input

i)

in

of

the

ch

ips.

The

74

LS244

chips

have

Schmi

t t t r

i9ge

r i

npu

ts

to

discriminate

a(Jainst

noi~:e.

The

principal

diff:ccence

br",tween

,;tdtic

dnd

dynamic

memory

is

th(:

nee

d

tor

e f

res

h

the

d a t a s

tor

e

din

a d y n a

IT,

i c

HI

e

In

0 r y . T

his

is

lwcessary

because

each

bi

t

of

da

ta

is

represen

ted

by

an

elec

t

ric

charge

stored

on

a

capacitor

in

each

memory

"cell".

This

charge

will

gradually

leak

away

due

to

the

finite

insulation

resistance

of

the

dielectric.

In

order

to

restore

the

amplitude

of

the

charge,

it

must

be

periodically

read

out,

amplified,

and

written

back

in

the

same

location.

This

is

accomplished,

thanks

to

the

ingenuity

of

the

l:hip

designers,

by

executing

a m

only

memory

cycle

for

each

bf

the

128

row

addresse~;

within

a 2

millisecona

interval.

In

other

dynamic

](C'vision

- J

1l/7B

Vector

Graphic

4~K

Dynamic

PAM

RORrd

4

mel1lory

boards,

this

is

done

using

counters,

multiplexers

and

complicated

priority

resolving

circuitry

to

interleave

refresh

cycles

with

CPU

access

cycles.

2.2

The

Refresh

Feature

of

the

Z-80

Board

Fortunately,

the

designers

of

the

Z-80

provided

for

this

requirement

by

including

a 7

bit

refresh

counter

in

the

chip

which

is

incremented

every

Ml

cycle

and

by

designing

the

chip

to

output

the

count

on

the

address

bus

during

every

Ml

cycle

at

a

point

in

time

when

the

address

bus

is

idle.

The

Vector

Graphic

Z-80

board

outputs

a

RFSH

signal

on

66

of

the

bus

to

indicate

that

a

ref

resh

cyc

le

must

be

initiated.

The

timing

of

this

signal

is

modified

by

U24

and

reclocked

by

the

system

clock

to

satisfy

the

timing

requirements

of

the

memory

chips.

The

output

of

U23

8

is

combined

in

Ull

to

0enerate

a

RAS

strobe

which

is

applied

to

all

chips

during

the

refresh

cycle.

There

are

several

conditions

under

which

the

normal

refresh

sequence

will

be

interrupted

which

could

result

in

loss

of

memory

data.

1.

if

the

CPU

is

held

in

a

wait

state

for

2

mS

or

longer.

2.

if

a

DMA

dev

ice

takes

control

of

the

bus

f.or

more

than

2

mS

without

generating

the

necessary

refresh

signals.

1.

if

the

CPU

is

held

in

a

reset

condition

for

more

than

2 mS.

Condition

1

would

not

occur

in

a

Vector

Graphic

computer,

but

can

occu-

in

a

system

with

a

front

panel

where

the

READY

line

is

used

to

HI.

L'l'

prog

ram

exec

ut

ion.

The

re

are

othe

r

ways

in

wh i

ch

th

is

can

occur

since

the

READY

line

is

a

popular

way

of

suspending

CPU

operaticn.

Caution

should

be

exercised

with

PROM

programming

boards,

which

typically

hold

the

CPU

in

a

wait

state

of

600

micro-seconds

during

a

programming

pulse.

See

Section

III,

"User's

Guide,"

for

information

on

handling

this

problem

with

PROM

programmers.

Other

common

uses

of

the

READY

line

are

to

synchronize

disk

transfers

and

to

prevent

video

display

glitching.

These

last

two

are

usually

not

a

problem

due

to

the

relatively

short

wait

period,

on

the

order

of

a few

microseconds.

Condition

2

does

not

occur

in

a

Vector

Graphic

computer

since

none

of

Lhe

boards

use

DMA.

If

you

are

usin(j

DMA

alone]

with

the

4<3K

board,

the

DMA

must

not

interrupt

the

CPU

for

longer

than

2 ms

wi

thout

(jenerating

the

necessary

refresh

signals.

Condi~ion

3

has

been

eliminated

by

providing

additional

circuitry

on

the

memory

board

to

generate

a

short

reset

pulse

synchronized

with

a

Ml

cycle.

This

consists

of

an

RC

network

C8,

R12,

Rll,

to

condition

the

PReSET

signal

connected

to

the

front

panel

reset

5witch.

Grounding

PRESET

allows

Ul

to

be

set

by

the

cycle

(memory

l~vision

1 -

1/]/78

Vector

Graphic

48K

Dynamic

RAH

GOoLJ 5

cycles

can

not

be

interrupted

without

loss

of

data).

Ul

triggers

U2

generating

a

200

micro-second

pulse

to

pull

unused

bus

line

55

low

through

the

open

collector

inverters

in

U14.

If

you

purchased

the

48K

board

as

a

separate

board,

not

as

part

of

a

complete

Vector

Graphic

computer,

you

will

have

to

make

certain

minor

modifications

to

your

Z-80

CPU

board

so

that

the

Reset

circuit

responds

to

the

signal

coming

from

the

48K

board

on

55.

These

modifications

are

described

in

the

User's

Guide

(Section

III

of

this

manual.)

Vector

Graphic

computers

shipped

with

the

48K

board

will

have

the

modifications

made

at

the

factory.

HeV1sion

1

1/3/7B

vector

Graphic

48K

U:z,'namic

R.r~;"l

L'

;:~,J

6

III.

USER'S

GUIDE

3.1

Modifications

to

the

48K

Board

and

Z-80

Board

'rhis

section

is

concerned

with

making

modifications

to

the

jumpers

on

the

48K

board

and

CPU

board

in

order

to

use

the

48K

board

in

existing

systems.

If

your

system

is

a

Vector

Graphic

computer

such

as

the

HZ,

MEMORITE,

or

Vector

3,

which

was

shipped

with

the

48K

bo~[d,

no

changes

are

required

to

either

board.

1.

REFRESH SIGNAL

Jumpers

can

be

ins

taIled

to

prov

ide

the

proper

RFSII

signal,

making

use

of

the

signal

presently

coming

from

your

CPU.

This

is

to

ensure

that

a

refresh

cycle

is

generated

during

every

instruction

fetch

cycle.

Without

this

signal,

operation

is

not

possible.

2.

RESET

CIRCUITRY

Modifications

can

be

made

to

the

reset

circuit

of

the

CPU

board

so

that

it

responds

to

the

short

reset

pulse

generated

by

the

48K

RAM

board

on

55

rather

than

the

PRESET

signal

on

75.

This

modification

is

optional.

It

is

to

prevent

the

CPU

from

being

held

in

a

reset

state

for

longer

than

2

milliseconds

which

would

result

in

loss

of

memory

data,

since

the

memory

is

not

being

refreshed

while

the

CPU

is

in

a

reset

state.

'rtw

ubove

two

1tlod

if

ications

an:

discussed

in

deta

il

be

low:

3.1.1

Refresh

Signal

--------~~--~~--

1 [

you

a t-e

us

Ing

tlJe

48E

boarrl

~J

i

th

a

non-Vectol"

Graphic

CPU

board,

refer

to

the

manual

for

your

CPO

board

to

determine

if

the

polarity

a

no

connec

t

ion

0 f

the

"RfS'H

signal

are

correct.

Th

is

signal

is

generated

by

28

of

the

Z-80

CPU

chip

and

should

be

buffered

onto

66

of

the

bus

using

a

non-inverting

buffer

of

the

8097

or

74367

type.

If

this

is

not

the

case,

it

is

necessary

to

modify

the

jumper

arrangement

on

the

4BK

board.

Area

C

on

the

board

allows

for

inverting

the

polarity

of

the"R'i?'STi

signal

if

it

is

inverted

on

the

CPU

bo~rd.

Cut

the

trace

between

pad

2

and

pa~

1

and

connect

a

j

ulI!I:>cr

be

tween

pad

3

and

pad

1.

I f

the

~

s

ig

na

1

is

broug

h t

to

98

on

the

bus

instead

of

66,

a

pad

is

provided

Gn

the

48K

board.

Cut

the

trace

in

arc'a

t\

to

(;6

and

install

a

jumper

to

98.

}~~~.2

___

Reset

Circuitry

The

purpose

of

this

modification

is

to

allow

the

short

(about

200

microseconds)

pulse

generated

by

the

48K

board

on

55

(previously

unused)

to

reset

the

CPU,

rather

than

using

the

'R~SET

signal

Revision

1 -

1/3/78

Vector

Graphic

48K

Dynamic

hA:'·;

L'Jol..J

7

generated

on

75

by

tie

Reset

switch.

The

signal

on

55

is

activated

by

the

front

panel

Reset

switch.

As

described

below,

there

are

two

different

~Grsions

of

this

modification:

Non-Vector

Graphic

Z-80

Boards

and

Vector

Graphic

Revision

1

Z-80

Boards

The

modification

described

below

is

applicable

to

all

existing

computer

systems,

including

systems

using

the

Vector

Graphic

Revision

I

Z-80

Board

(which

includes

all

existing

Vector

Graphic

computers

shipped

with

static

RAI"!

boards.)

A

typical

Reset

circuit

on

a

Z-80

CPU

board

and

the

necessary

modifications

are

shown

below:

COMPUTER

RESET

SW

ITCH {

+5V

\...---4

....

-------I

...

Ta z-

80

CH

I P

c+

~~~~~~~;~TIC

I25 -100

mfd

_

TYPI

CAL

-

ORIGINAL CIRCUIT

--,

*

S

--

....

I----I.~JO

z-

80

JUMPER

C~IP

INSTALLED

MOuIFIED

CIRCUIT

kemove

the

Resistor

R

and

Capacitor

C

from

the

board.

Then

connect

a

jumper

from

55

to

the

pad

previously

connected

to

the

+

end

of

the

capacitor.

Vector

Graphic

Z-89

Boards

This

version

of

the

modification

is

relevent

to

any

existing

computer,

including

Vector

Graphic

computers,

using

a

Vector

Graphic

Z-80

CPU

board.

Install

a

jumper

between

55

and

the

junction

of

the

220

ohm

and

180

ohm

resistor

connected

to

the

emitter

of

the

2N3643

transistor.

This

junction

will

be

found

near

the

upper

right-hand

corner

of

the

schematic.

Pads

are

provided

on

Revision

2

of

the

2-80

board,

but

are

not

provided

on

Revision

1.

Then,

remove

the

100

ohm

resistor

and

the

capacitor

which

are

connected

to

75.

Hevision

3 -

2/7/78

Vector

Grnvhic

48K

Dynamic

R~M

~01~~

8

3.2

The

READY

Line

Ie

the

CPU

is

held

in

a

wait

state

for

2

mS

or

longer,

the

normal

reEr.esh

sequence

will

be

interrupted

which

could

result

in

the

loss

o[

memory

data.

Since

computers

with

a

front

panel

use

the

READY

line

to

HALT

program

operation,

if

your

computer

has

a

front

panel,

you

may

NOT

use

the

front

panel

when

the

48K

Board

is

being

used.

If

you

do,

the

system

will

bomb.

Caution

should

also

be

exercised

with

PROM

programming

boards,

which

typically

hold

the

CPU

in

a

wait

state

of

600

micro-seconds

during

a

programming

pulse.

After

every

byte

programmed,

a

software

loop

should

execute

128

instructions

to

ensure

refresh.

A

typical

loop

is

as

follows:

LOOP

PUSH

MVI

DJNZ

POP

B

13

,

80H

LOOP

B

Other

common

uses

of

the

READY

line

are

to

synchronize

disk

transfers

and

to

vrevent

video

display

glitching.

These

last

two

are

usually

not

a

problem

due

to

the

relatively

short

wait

period,

on

the

order

of

a

few

microseconds.

3.3

Usi

DMA

If

you

are

using

DMA

along

with

the

48K

board,

the

DMA

must

not

i n t

err

up

t

the

CPU

for

10

ng e r t

han

2

T,l

S

wit

h 0 u t

yen

era

t i

fI

9

the

Il':.:cessary

refresh

signals.

3.4

Address

of

the

Board

The

48K

RAM

board

is

designed

to

occupy

the

lOVler

48K

of

address

space.

No

provision

has

been

made

to

change

this.

For

this

reason,

you

will

not

find

any

reE0rences

in

this

manual

to

the

nlethod

of

specifying

the

address

of

the

board.

3.5

Memory

test

Tllis

~3ection

is

relevent

if

you

are

usin(J

a

Vector

Graphic

computer

I

or.

at

least

a

Vector

Graphic

12K

PROM/RAM

board

in

addition

to

the

4BK

board.

The

48K

board

can

be

tested

using

the

Vector

Graphic

Extended

Mor.itor

T

command.

Install

the

board

in

your

system

and

turn

the

;;ystem

on.

TYfJe T

0000

COOO.

After

a

few

seconds

COOO

XX

C3

should

appear

on

the

terminal

indicating

that

location

COOO

(the

first

PROM

Revision

1 -

1/3/78

Vector

Graphic

48K

Dynamic

Fc'l.r1

L~~,LJ

9

location)

could

not

be

written

to.

The

test

will

automatically

repeat,

and

no

addresses

other

than

COOO

should

be

printed

out.

Depress

the

RESET

key

on

the

front

panel

to

terminate

the

test.

11.

,!lore

thorough

test

can

be

made

using

the

MDIAG

program

supplied

on

the

Vector

MZ

system

diskette.

Refer

to

Appendix

J

of

the

MZ

User's

Manual.

1

Ii

/...,0

Vecto~

Graphic

4SK

Dynamic

p~~

~~~r~

Buffering:

Access

Time:

Power

Consumption:

Phantom:

DMA:

Availability:

Revision

I -

1/3/78

SPECIFICATIONS

49,152

8-bit

bytes

Buffered

data

input

and

output

Compatible

with

Z-SO

at

4MHZ

without

wait

states

O.25A

of

+SV

and

O.20A

of

+16V,

typical

Ouput

buffer

disable

compatible

with

Vector

Graphic

PROM/RAM

(Reset

and

Go)

Board

Must

not

interrup~3the

CPU

for

longer

than

2XIO

seconds

without

generating

the

necessary

refresh

siqnals

Shipped

assembled,

tested,

burned

in,

and

guaranteed

1

year;

no

kits

10

Vector

Graphic

4BK

Dynamic

RAM

Board

11

D7

D6

D5

04

D3

02

01

00

U3

Ul0

0-3FFF

U15

U22

4000-7FFF

U26

U33

8000-BFFF

48K

DYNAMIC

MEMO~Y

CHIP

LOCATIONS

Rpvision

1 -

1/3/78

D

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Vector Graphic 48K Dynamic Memory Board User manual

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