VME VMIVME-DR11W-A User manual

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VMIVME-DR11 W-A
VMEbus-TO-DR11 W INTERFACE
INSTRUCTION MANUAL
DOCUMENT NO. 500-000121-000 E
Revised 08 December 1993
VME MICROSYSTEMS INTERNATIONAL CORPORATION
12090 SOUTH MEMORIAL PARKWAY
HUNTSVILLE, AL
35803-3308
[phone]
1-800-322-3616
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NOTICE
The information in this document has been carefully checked and is
believed to be entirely reliable. While all reasonable efforts to ensure accuracy
have beentaken inthe preparationof this manual, VMlC assumes no responsibility
resulting from omissions or errors in this manual, or from the use of information
contained herein.
VMlC reserves the right to make any changes, without notice, to this or
any of VMIC's productsto improvereliability, performance, function, or design.
VMlC does not assume any liability arising out of the application or use
of any product or circuit described herein; nor does VMlC convey any license
under its patent rights or the rights
of others.
VME Microsystems International Corporation
All Rights Reserved
Thisdocument shall not be duplicated, nor its contents usedfor any
purpose, unless granted express written permission from VMIC.
Copyright O September 1989 by
VME Microsystems lnternatlonal Corporation
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CABLE REQUIREMENTS:
The VMIVME-DR11W-A requires that the following cabling guidelines be
followedfor properoperation anddata integrity:
1. Flat-cablewith an overall shield or ground plane (or superiorcable) must
be used. Mass-terminatedstandard flat-cable willcause data errors.
2. The cable shield must be grounded at both ends of the cable if a
shielded cable
is used. The cable grounds should have low impedance
at highfrequencies.
3. Macrolink interfaces for the ConcurrentIPerkin-Elmer require a pinout
reversal on the cables. When ordering specify macrolink cables.
DR11 W COMPATIBILITY:
The VMIVME-DR11W-A is pinout compatible with DR11-W and DRVl1-B
type devices, with the exception of Function
1 now being a defined bit on the
VMIVME-DR1
1 W-A Board. It is not pinout compatible with DR11-B type devices
anddamage may result
if it iscabled directlyto a DR11-B type device.
Bit
6 (LONGWORD) of the Address Modifier Register (AMR) must be
maintainedto the proper state to assure proper operation of the associated
8-, 16-,
or 32-bit transfers. Referto Section
4.4.4.
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RECORDOF REVISIONS
REVISION
LElTER DATE PAGES INVOLVED
Releaseper ECO
Changeper ECO
Changeper ECO
Cover, pages
iii, vi, viii, Sections 2,
and 6, andAppendix A
CorrectTable 4.5-1
ME MICROSYSTEMS INT'L CORP, I
CHANGE NUMBER
1 REVLTR I PAGE NO.
2090 South Memorial Parkway
luntsville, AL 35803-3308-(205)8806444
E
DOC. NO. 500000121-000
iii
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VMlC
SAFETY SUMMARY
THE FOLLOWING GENERAL SAFETY PRECAUTIONS MUST BE OBSERVED DURING ALL
PHASES OF THE OPERATION, SERVICE, AND REPAIR OF THlS PRODUCT. FAILURE TO
COMPLY WlTH THESE PRECAUTIONS OR WlTH SPECIFIC WARNINGS ELSEWHERE IN THlS
MANUAL VIOLATES SAFETY STANDARDS OF DESIGN, MANUFACTURE, AND INTENDED USE
OF THlS PRODUCT. VME MICROSYSTEMS INTERNATIONAL CORPORATION ASSUMES NO
LIABILITY FOR THE CUSTOMER'S FAILURETO COMPLY WlTH THESE REQUIREMENTS.
GROUND THE SYSTEM
To minimize shock hazard, the chassis and system cabinet must be connected to an
electrical ground. A three-conductor AC power cable should be used. The power
cable must either be plugged into an approved three-contact electrical outlet or used
with a three-contact to two-contact adapter with the grounding wire (green) firmly
connectedto an electricalground (safety ground) at the power outlet.
DO NOT OPERATE IN AN EXPLOSIVEATMOSPHERE
Do not operate the system inthe presence of flammable gases or fumes. Operationof
any electrical system insuch an environment constitutesa definite safety hazard.
KEEPAWAY FROM LIVE CIRCUITS
Operating personnel must not remove product covers. Component replacement and
internal adjustments must be made by qualified maintenance personnel. Do not
replace components with power cable connected. Under certain conditions,
dangerous voltages may exist even with the power cable removed. To avoid injuries,
always disconnect power and discharge circuits beforetouching them.
DO NOT SERVICE OR ADJUST ALONE
Do not attempt internal service or adjustment unless another person, capable of
renderingfirst aid and resuscitation, is present.
DO NOT SUBSTITUTE PARTS OR MODlFV SYSTEM
Because of the danger of introducingadditional hazards, do not install substitute Darts
or perform any unauthorized modification to the product. Return the product to
VME
Microsystems International Corporation for sewice and repair to ensure that safetv
features are maintained.
DANGEROUS PROCEDURE WARNINGS
Warnings, such as the example below, precede only potentially dangerous
procedures throughout this manual. Instructions contained in the warnings must be
followed.
DANGEROUS VOLTAGES, CAPABLE OF CAUSING DEATH, ARE PRESENT IN THlS SYSTEM.
USE EXTREME CAUTION WHEN HANDLING,TESTING, AND ADJUSTING.
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SAFETY SYMBOLS
Gs
Instructionmanualsymbol: the productis markedwith this symbol when
it is necessary for the user to refer to the instructionmanual inorder to
protectagainstdamage
to thesystem.
Indicatesdangerous voltage (terminals fed from the interior by voltage
exceeding
1000 volts areso marked).
Protectiveconductor terminal. For protectionagainst electrical shock in
case of a fault. Usedwith field wirina terminals to indicate the terminal
which mustbeconnectedto groundbeforeoperatingequipment.
1 WARNING 1
*t*..***t*.*t**f
* CAUTION ;
***..*rr****+*.
NOTE:
Low-noise or noiseless, clean ground (earth) terminal. Usedfor a signal
common, as well as providingprotectionagainst electricalshock incaseof
a fault. Beforeoperating the equipment, terminalmarkedwith this symbol
must be connectedto ground in the manner described inthe installation
(operation)manual.
Frame or chassis terminal. A connectionto the frame (chassis) of the
equipmentwhichnormallyincludesallexposedmetalstructures.
Alternatingcurrent(power line).
Directcurrent (power line).
Alternatingor directcurrent(power line).
The WARNING sign denotes a hazard. It calls attentionto
a procedure, a
practice, a condition, or the like, which, if not correctly performed or
adheredto, couldresultininjury
or deathto personnel.
The CAUTION sign denotes a hazard. It calls attentionto an operating a
procedure, a practice, a condition, or the like, which, if not correctly
performedor adhered to. could result indamage to or destructionof partor
allofthe system.
The NOTE sign denotes important information. It calls attention to a
procedure, a practice, a conditionor the like, whichisessential
to highlight.
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VMIVME-DR11 W-A
VMEbus-TO-DR11 W INTERFACE
TABLE OF CONTENTS
SECTION 1 . INTRODUCTION
INTRODUCTION .......................................................................................... 1-1
FUNCTIONALDESCRIPTION
..................................................................... -1
............................................................................................. COMPATIBILITY 1-5
REFERENCE MATERIALLIST
.................................................................... 1-6
SECTION 2 .
PHYSICAL DESCRIPTION AND SPECIFICATIONS
SECTION
3 . THEORY OF OPERATION
BLOCK DIAGRAMS ....................................................................................... 3-1
OPERATIONALOVERVIEW
......................................................................... 3-1
TRANSFER PROTOCOL
.............................................................................. 3-1
DATATRANSFER DESCRIPTION
............................................................. 3-11
VME-TO-VME LINK
..................................................................................... 3-12
USER INTERFACE SIGNAL FUNCTIONDESCRIPTION
...................... 3-12
SECTION 4 . PROGRAMMING
4.1 PROGRAMMINGOVERVIEW ...................................................................... 4-1
4.2 PROGRAMMINGTHE SCB68430 DMAl
................................................... 4-1
.................................... 4.2.1 ChannelStatus RegisterlchannelError Register 4-1
4.2.1.1 CSR Bit Definitions
........................................................................................ 4-1
4.2.1.2 CER Bit Definitions........................................................................................4-7
4.2.2 DeviceControlRegister(DCR)/OperationControl Register (OCR)
...... 4-7
4.2.2.1 DCR Bit Definitions
........................................................................................ 4-7
. .
4.2.2.2 OCR Bit Defin~t~ons ........................................................................................ 4-8
4.2.3 Sequence Control Register (SCR) ............................................................. 4-8
4.2.4 ChannelControl Register (CCR) ................................................................ 4-8
.................................................. 4.2.5 MemoryTransfer Count (MTC) Registers 4-9
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TABLE OF CONTENTS (Continued)
SECTION 4 . PROGRAMMING (Concluded)
mz2
Me.moryAddress Counter(MAC) Registers .............................................. 4-10
DMA InterruptVector Register (DIVR)
....................................................... 4-10
Channel Priority Register (CPR)
................................................................. 4-10
PROGRAMMINGTHE MC68153BIM
........................................................ 4-10
Error InterruptControl Register (EICR)
Attention lnterruptControl Register (AICR)
DMA InterruptControl Register (DICR)
..................................................... 4-11
Enor lnterruptVector Register(EIVR)
Attention InterruptVector Register (AIVR)
............................................... 4-13
PROGRAMMINGTHE ON-BOARD REGISTERS
..................................... 4-13
BoardControl Register (BCR)
..................................................................... 4-29
BCRH (BCR High) Bit Descriptions
............................................................ 4-29
BCRL (BCR Low) Bit Descriptions
.............................................................. 4-30
VMIVME-DR11W-A
I10 Data Register (IODR) HighILow ........................ 4-31
ExtendedMemoryAddress Register (EMAR)
........................................... 4-32
Address Modifier Register(AMR)
................................................................ 4-32
MasterControlRegister (MCR)
................................................................... 4-34
Board Status Register (BSR)
....................................................................... 4-44
Set Cycle Req (SCRQ)
................................................................................. 4-47
Load Input Data Register (LDIDR)
.............................................................. 4-47
VMIVME-DR11W-A 32-Bit Output Data Register (ODR)
......................... 4-49
VMIVME-DR11W-A 32-Bit Input Data Register (IDR)
.............................. 4-49
SEQUENCEOF REGISTER LOADING
..................................................... 4-55
SAMPLE SOFTWARE LISTINGS
............................................................... 4-56
SECTION
5 . CONFIGURATION AND INSTALLATION
..................................................................... UNPACKING PROCEDURES 5-1
......................................................................... PHYSICAL INSTALLATION 5-1
JUMPER INSTALLATIONS
.......................................................................... 5-1
................................................................................................... Busy Polarity 5-3
............................................................................. VMEbus PriorityJumpers 5-3
.....................................................................................BoardBase Address 5-3
LWORD*ControlJumper
............................................................................. 5-6
Enable Other Board Ready Jumper
........................................................... 5-6
Cyde Request Jumpers
................................................................................ 5-7
............................................................................ Busy Delay Clock Jumper 5-8
...................................................................................................... Busy Delay 5-9
................................................................................ADDRESS MODIFIERS 5-9
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TABLE OF CONTENTS (Continued)
m
SECTION 5 . CONFIGURATION AND INSTALLATION (Concluded)
5.5 VO CABLES .................................................................................................... 5-10
5.5.1 User InterfaceCables
................................................................................ 5-10
5.5.2 Macrolink Pin Number Reversal
................................................................. 5-10
5.5.3 Pin Number Reversal Through Bulkhead Connector
............................. 5-12
5.6 CABLECONNECTOR
................................................................................ 5-12
5.7 USER CONNECTOR PIN ASSIGNMENTS
.............................................. 5-12
5.8 INSTALLATION
.............................................................................................. 5-12
SECTION 6 . MAINTENANCE WARRANTY
MAINTENANCE ............................................................................................. 6-1
MAINTENANCEPRINTS..............................................................................6-1
WARRANTY
.................................................................................................... 6-1
OUT-OF-WARRANTYREPAIR POLICY.....................................................6-2
Repair Category
............................................................................................. 6-3
. .
Repair Pr~c~ng ................................................................................................. 6-3
Payment
........................................................................................................... 6-3
Shipping Charges
......................................................................................... 6-4
Shipping Instructions
.................................................................................... 6-4
Warranty on Repairs
...................................................................................... 6-4
Exclusions ....................................................................................................... 6-4
LIST OF FIGURES
PrintedCircuit Assembly Photograph ........................................................ 1-2
VMIVME-DR1
1 W-A Connection-to-User Device ..................................... 1-3
VMIVME-DR11W-A CPU-to-CPULink
...................................................... 1-4
........................................ VMIVME-DR11W-A FunctionalBlock Diagram 3-2
InterfaceInterconnectionfor Two VMIVME-DR11W-As in Back-to-Back
Configuration
.................................................................................................. 3-3
InterfaceConnectionto
a DRV11-WA ...................................................... 3-4
TiminglHandshake Sequencing 32-Bit DataTransfers from the
VMIVME-DR1
1 W-A to the User Device ..................................................... 3-5
Back-to-Back32-Bit DMA Transfers Configuration(Interprocessor
Mode)
............................................................................................................... 3-6
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TABLE OF CONTENTS (Continued)
Diagramfor 32-Bit DataTransfers from the User Deviceto the
VMIVME-DR11W-A
........................................................................................ 3-7
TimingJHandshake Sequencing 16-Bit DataTransfers from the
VMIVME-DR1
1 W-A to the User Device ..................................................... 3-8
Back-to-Back16-Bit DMA TransferConfiguration(Interprocessor
Mode)
............................................................................................................... 3-9
Diagram for 16-Bit DataTransfers from the UserDeviceto the
VMIVME-DR11W-A
........................................................................................ 3-10
DMA Transmit (XMT) ProgramControlled Receive (RCV),
WraparoundTest Mode Program Functional Flow Diagram,
Longword
........................................................................................................ 4-37
DMA Transmit (XMT), Program ControlledReceive (RCV),
Wraparound Test Mode, Program FunctionalFlow Diagram,
Longword(Continued)
.................................................................................. 4-38
Input Data Formats WITHOUTWord Swap
.............................................. 4-40
InputDataFormats WITHWord Swap
....................................................... 4-40
DMA Receive (RCV), ProgramControlledTransmit (XMT)
Wraparound Test Mode Program
. FunctionalFlow Diagram .
. .
Longword ....................................................................................................... 4-41
4.4.5-28 DMA Receive(RCV). Proaram ControlledTransmit IXMT)
Wraparound ~est
ode Frogram. FunctionalFlow ~iagkm.
Longword(Continued)
.................................................................................. 4-42
................................................................. 4.4.5.3 16-BitVO DataRegisterFormats 4-45
...........................................
4.4.5.4 Output DataRegister WlTHOUTWordSwap 4-45
...................................................
4.4.5.5 Output Data Register WITHWord Swap 4-45
4.4.7-1 DMA Transmit Test Using Set Cycle Req Command. Functional
Flow Diagram
................................................................................................. 4-48
4.4.8.1 LDlDR Command Format WITHOUTWord Swap. 32-Bit
...................... 4-50
4.4.8.2 LDIDR Command Format WITHWordSwap, 32-Bit
............................... 4-50
4.4.8.1A 16-Bit LDlDR Bit ProgramFunctionalFlow Diagram
.............................. 4-51
4.4.8.1 B 16-BitLDlDR Bit Program FunctionalFlow Diagram (Continued)
........ 4-52
..............................
4.4.8.2A 32-Bit LDlDR Bit ProgramFunctionalFlow Diagram 4-53
4.4.8.28 32-Bit LDlDR Bit Program FunctionalFlow Diagram (Continued)
........ 4-54
5.3.1 VMIVME-DR11W-A ConfigurationInformation
......................................... 5-2
5.3.1-1 Busy Signal Polarity Selection, Busy L Must Be Selectedfor Back-
...............................
to-Back Operationof Two VMIVME-DR11W Boards 5-3
................... 5.3.2.1 Jumper Installationfor Selection of VMEbus Priority Level 5-4
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TABLE OF CONTENTS (Continues
Board Base Address Jumpers ..................................................................... 5-5
LWD Jumper
................................................................................................... 5-6
.......................................................................
Other BoardREADYJumper 5-7
Cycle RequestJumper
.................................................................................. 5-8
Busy Delay Clock Jumper
............................................................................ 5-8
BUSY DELAY Jumper
.................................................................................. 5-9
System InterconnectionPictorialDiagram
................................................ 51
J IST OF TABLES
5le
VMIVME-DRl1W-A Compatible Host Computer InterfaceSources .... 1-5
VMIVME-DR11W-A RegisterAddress Map
............................................... 4-2
....................................
DMA Interface(SCB68430)Register Bi Formats 4-3
.......................... Bus Interrupt Module (MC68153) Register Bit Formats 4-12
On-BoardRegister
Bit Formats .................................................................... 4-14
Address Modifier Codes
............................................................................... 4-33
Registerlnitialization Sequence for Transmitting
a 4 K Word Block
StartingDataAddress$40000
.................................................................... 4-57
Register lnitialization Sequence for Transmittinga Second4
K Word
BlockStarting DataAddress $20000
......................................................... 4-58
RegisterInitializationSequencefor Receivinga 4
K Word Block
StatingDataAddress $40000
.................................................................... 4-59
Register lnitialization Sequencefor Receiving a Second 4
K Word
BlockStarting DataAddress $20000
......................................................... 4-60
Connector PinAssignments
........................................................................ 5-13
APPENDICES
A Assembly Drawing. Parts List. and Schematic
B Integrated Circuit Specifications
C Sample Software Listings
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SECTION 1
INTRODUCTION
INTRODUCTION
The VMIVME-DR11W-A is a high performance VMEbus 32-bit Direct
Memory Access (DMA) interfacethat forms a 16-bit parallel interface between the
VMEbus and Digital Equipment Corporation (DEC) DR11-W and DRV11-WA type
devices, and with the DR11W CPU links. A photographof the VMIVME-DR11W-A
printedcircuit assembly is shown in Figure 1.l-1. VMIVME-DRl1W-A features are
as follows:
a. DR11
W and DRVl1-WA compatible 110 connection
b. 32-bit DMA datatransfers
c. 32-bit addressing
d. VMEbus (IEEEPI01
4) compatible
e. Software-selectablebyte andword swapping
f. Watchdogtimers preventtransfer lockout on VMEbus andcables
g. FrontpanelFailLED
h. Supports off-line Built-in-Testplus single board loopback testing (with
test cable)
i. MeetsVMEbus Spec. C.1 - compatibleaddress pipelining
j Fully programmable operation (includes selection of 16- or 32-bit
transfer, burst mode, etc.)
k. Fully programmable interruptvectors and levels
I. ProgrammableVMEbus address modifiers
m. Jumper-selectableVME standardshort 110 address space for on-board
registers
n. Softwarecompatiblewith VMIC's DR11Wand DR11W-485 boards
o. Two VMIVME-DR11W-As form a VMEbus-to-VMEbuslink
FUNCTIONALDESCRIPTION
The VMIVME-DRl1W-A provides a high performance, 16-bit DMA Link
between the VMEbus and DEC DRll-W compatible devices. The VMIVME-
DR11W-A interfaces may also be connected back-to-backto form a VMEbus-to-
VMEbus DMA Link (see Figures1.2-1 and 1.2-2).
The VMIVME-DR11W-A incorporates a SCB68430 DMA controllerdevice
to perform its DMA transfers, a MC68153 Bus InterrupterModule (BIM)to implement
a VMEbus interrupter(for the attention and DMA completion interrupts), and it also
contains logic to allow the VMIVME-DR11W-Ato generate an attention interrupt to
the externaldevice.
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VMEbus
I DATA CONTROL
DRllW
COMPATIBLE
PERIPHERAL
MDRl1 W-AlF1.2-1
Figure 1.2-1. VMIVME-DR1 t W-A Connection-to-UserDevice
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COMPATIBILITY
VMIVME-DR11W compatibility interfacesfor the computerslistedinTable
1.3-1are available from the companies indicatedfor each computer.
Table 1.3-1. VMIVME-DR11W-A CompatibleHostComputer Interface Sources
COMPUTER COMPANY PHONENUMBER
CONCURRENT1
I
Macrolink** 1 [phone]
PERKIN-ELMER
DECVAX, PDP-11
LSI-11
HARRIS
I
Harris
H60-HI00
I
DigitalEquipmentCorp.
-
'Not directly VMIVME-DR11Wcompatible - requiressimple modificationof MPCl Model 8020 IOP
interfaceboard (contact Encorefor VMIVME-DR11W modificationkit). VMlC has a 32-bit Encore
HSD-to-VMEbusinterface.
"Macrolink interfaces require a cable pinout reversal. When ordering cables specify the macrolink
1-800-DIGITAL
ContinentalBlvd.
Merrirnack, NH 03054
ENCORE CONCEPT
32 Series*
IBMPCIAT
cables.
"'Requires Omnicompinterprocessorlink driver with softstart.
NOTICE
THE INFORMATION IN TABLE 1.3-1 IS OFFERED AS A HELPFUL SUGGESTION. IT IS
INTENDEDAS A GUIDE. VMlC DOES NOTGUARANTEEFAVORABLERESULTSNOR DOES IT
ASSUME ANY LIABILITY IN CONNECTION WlTH ITS USE. NO STATEMENT OR
Encore
OrnnicompGraphics***
..... . ... ~ ~ .....
RECOMMENDATIONISINTENDED BY VMlC FOR THE USE OFTHESE PRODUCTS. BEFORE
USING THE PRODUCTS LISTED. THE USER SHALL DETERMINE THE SUITABILITY OF THE
[phone]
[phone]
Houston,
TX
PRODUCT(S) FOR HIS INTENDED USE, AND THE USER ASSUMES ALL RISK AND LIABILITY
INCONNECTIONWlTHTHEIR USE.
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REFERENCEMATERIAL LIST
The reader should refer to "The VMEbus Specification" for a detailed
explanationof VMEbus. "The VMEbus Specification is available from the following
source:
VITA
VMEbus InternationalTrade Association
10229
N. Scottsdale Road
Scottsdale,
AZ 85253
[phone]
Additional informationconcerningthe DR11
W protocoliscontained inthe
"DR11
-W Direct Memory Interface Module (No. EK-DR1 1 W-UG-002)". This
document isavailablefrom the followingsource:
DigitalEquipmentCorporation
146 Main St.
Maynard, MA 01754-2751
[phone]
Specific information concerning the SCB68430 may be obtained from the
following source:
Signetics Corporation
811 E. Arques Ave.
P.O. Box 3409
Sunnyvale,CA 94088-3409
[phone]
A detailed specification is providedinAppendix 6.
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SECTION 2
PHYSICAL DESCRIPTION AND SPECIFICATIONS
REFER TO 800-000121-000 SPECIFICATION
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SECTION 3
THEORY OF OPERATION
BLOCK DIAGRAMS
As shown in the functional block diagram (see Figure 3.1-1) and in the
interconnection diagrams (Figures 3.1-2 and 3.1-3) the VMIVME-DR11W-A
interface provides for the exchange of program controlled interrupts and status as
well as two 16-bit data buses with handshake signals. The function of these
interface signals are described in Section 3.4. The handshake sequencing of the
signals are depictedin Figures 3.1-4, 3.1-5, and 3.1-6 for the 32-bit transfer mode,
and in Figures 3.1-7, 3.1-8, and 3.1-9 for the 16-bittransfer mode.
Although the VMIVME-DR11W-A interface was developed for
interconnection to DR11-W compatible devices, it also performs DMA transfers in
conjunction with the DRV-11WA interface (see Figure 3.1-3).
OPERATIONAL OVERVIEW
The VMIVME-DR11W-A has two modes of operation,
INTERPROCESSOR LlNK MODE (back-to-backconfiguration), and EXTERNAL
DEVICE MODE. Inthe INTERPROCESSOR LlNK MODE, the VMIVME-DR11W-A
communicates with another DR11-W compatible computer interface. In the
EXTERNAL DEVICE MODE, the VMIVME-DR11W-A communicates with a user's
device such as a disk drive system, tape drive, etc.
To operate in either mode, a transfer protocol (see Section 3.3) must be
established. Once this isdetermined, the VMIVME-DRI
1 W-A may be programmed
as detailed in Section 4.1. One difference in the operation of this device versus
other DR11-W implementations is that the bus transfer type (wordlbyte and
direction) is determinedbeforethe start of any datatransfers and not on a cycle-by-
cycle basis.
When two DR11W compatible boards are connected back-to-back the
two cables are crossed over so that one boarddrives a control signal andthe other
boardreceivesit. Thus, there is no need for a "master/slave mode".
3.3 TRANSFER PROTOCOL
In order for DMA transfersto take place the DMA interfaces must be set
up at bothends of the link. Therefore,
if a CPU on one bus wants to transferdata, a
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