XDS Sigma 9 User manual

XIDlS SIGMA 9 COMPUTER
Xerox Data Systems
Reference Manual

XoS SIGMA
9 INSTRUCTION
LIST (MNEMONICS)
Mnemonic Code
Instruction Name
~age
Mnemonic
~ode
Instruction Name
Page
AD 10 Add
Doubleward 60 LCF 70 Load Conditions ond Floating Control
55
AH 50
Add Halfword '
60
LCFI
02
Load Conditions and Floating Control Immediate 54
AI 20
Add Immediate
59
LCH
5A Load Complement Halfword
48
AIO
6E Acknowledge Input/Output Interrupt
120 LCW
3A Load Complement Word
48
AND
4B AND Word 68
LD 12
Load'Doubleword
48
ANLZ
44
Analyze
57 LH 52 Load Halfword
47
AW 30
Add Word 60
LI 22 Load Immediate 47
AWM
66 Add Word to Memory 64 LM 2A Lood
Multiple
54
LMS
2D Load Memory Status 51
BAL
6A Branch and link 101 LPSD
OE
Load Program Status Doubleword 103
BCR 68 Branch
on Conditions Reset 100
LRA 2C
Load Rea I Address 50
BCS
69 Branch on Conditions Set
100 LRP
2F Load Register Pointer 106
BDR 64
Branch on Decrementing Register 101
LS 4A Load Selective
53
BIR
65 Branch on Incrementing Register
JOO
LW
32
Load Word
47
CAll 04
Call 1 102
MBS 61 Move Byte String
86
CAL2 05 Call 2 102
CAL3
06 Call 3 102
MH
57
Multiply Halfword
62
CAL4 07 Call 4 102
MI 23 Multiply Immedi-ate
62
CB
71 Compare Byte 66
MMC 6F Move
to Memory Control 106
CBS 60
Compare Byte String 87
MSP 13 Modify Stack Pointer
98
CD 11 Compare Doubleword
67
MTB 73 Modify and Test Byte
64
CH
51 Compare Halfword
66
MTH
53
Modify and Test Halfword
64
MTW 33 Modify and Test Word 65
CI
21 Compare Immediate 66
MW
37
, M~ltiply Word
63
CLM 19 Compare
with Limits in Memory
68
CLR
39 Compare with Limits in Register 67
OR 49 OR Word
68
CS
45 Compare Selective
67
CVA
29 Convert by Addition 72
PACK 76
Pack Decimal Digits 83
CVS 28
Convert by Subtraction
73
PLM OA
Pull Multiple
97
CW 31
Compare Word 67
PLW 08
Pull Word
96
DA 79 Decimal Add
81
POLP 4F Poll Processor 120
POLR 4F Poll
and Reset Processor 120
DC 7D Decimal Compare
82
PSM OB
Push Multiple
96
DD 7A Decimal
Divide 82
DH 56
Divide Halfword 63
PSW 09 Push Word 95
• DL
7E
Decimal Load 80
RD
6C Read Direct
108
DM 7B
Decimal Multiply 81
RIO 4F Reset
Input/Output
120
DS 78
Decimal Subtract 81
DSA 7C
Decimal Shift Arithmetic
82
S 25 Shift
69
DST'
7F Decimal Store 81
SD 18 Subtract Doubleword
61
DW 36
Divide Word
63
SF 24 Shift Floating
71
EBS 63
Edit Byte String
89
SH
58 Subtract Ralfword
61
EOR 48 Exclusive OR Word
68
SIO 4C Start Input/Output
114
EXU 67
Execute
99
STB
75 Store Byte
55
STCF
74
Store Conditions and Floating Control 56
FAL
ID Floating Add Lang 77
STD 15 Store Doubleword
56
STH 55
Store Ha Ifword
55
FAS
3D Floating Add Short 77 STM
2B Store Multiple
56
FDL
IE
Floating Divide Long 78
STS
47
Store ,Selective 56
FDS 3E Floating Divide Short
78
STW
~5
Store Word
55
FML IF
Floating Multlply Long 77
SW
38
Subtract Word
61
FMS 3F
Floating Multiply Short 77
FSL lC Floating SiJbtract Long 77
FSS 3C
Floating Subtract Short 77 TBS
41
Translate Byte String
87
TDV 4E Test Device
118
HIO 4F Halt Input/Output
119
TIO 4D Test Input/Output
117
HBS 40 Translate and Test Byte String
88
lNT 6B
Interpret
58
UNPK 77 Unpack Decimal Digits
84
LAD
1B
Load Absolute Doubleword 50
LAH 5B Load Absolute Halfword
48 WAIT
2E
Wait
108
LAS 26 Load and Set
51 WD 6D Write Direct
110
LAW 3B
Load Absolute Word
49
LB 72 Load Byte
47
XPSD OF
Exchange Program Status Doubleword 103
LCD lA
Load Complement Doubleword
49 XW 46 Exchange Word
55

Price: $6.50
XDS SIGMA 9 COMPUTER
REFERENCE MANUAL
FIRST EDITION
90 17 33A
October 1970
Xerox Data Systems/701 South Aviation Boulevard/EI Segundo, California 90245
© 1970, Xerox Data Systems, Inc. Printed in U.S.A.

ii
RELATED PUBLICATIONS
Title
XDS Sigma Glossary of Computer Terminology
XDS Symbol/Meta-Symbol Reference Manual (Sigma 5/7 Computers)
XDS Macro-Symbol Reference Manual (Sigma 5/7 Computers)
Publ ication No.
90 09 57
90 0952
90 15 78

l.
2.
CONTENTS
SIGMA 9 SYSTEM
Introduction 1
General Characteristics 1
General-Purpose Features 3
Input/Output Capabi I ities
4
Time-Sharing Features
4
Real- Time Features 5
Multiusage Features
6
Multiprocessor Features
6
Multiprocessor Interlock 6
Homespace
6
Multiport Memory System 6
Manual Partitioning Capabi lity
7
Multiprocessor Control Function
7
Shared Input/Output 7
SIGMA 9 SYSTEM ORGANIZA nON
8
Central Processing Un it
8
General Registers 8
Memory Control Storage
8
Computer Modes
11
Information Format
11
Information Boundaries
12
Instruction Register
12
Main Memory
13
Memory Unit
13
Virtual and Real Memory
14
Homespace
14
Memory Reference Address
14
Types of Addressing
17
Address Modification Examples
20
Memory Address Control
22
Program Status Doubleword
26
Interrupt System 28
Internal Interrupts
29
ExternaI Interrupts
30
States of an Interrupt Level 30
Control of the Interrupt System 32
Time of Interrupt Occurrences_
32
Single-Instruction Interrupts
32
Trap System
__ 33
Trap
33
T rap Entry Sequence
_______ 33
Trap Masks 33
Trap Condition Code
33
Trap Addressing 33
Nonallowed Operation Trap 35
Unimplemented Instruction Trap 36
Push-Down Stack Limit Trap 37
Fixed-Point Overflow Trap
37
Floating-Point Arithmetic Fault Trap 38
Decimal Arithmetic Fault Trap 39
CALL Instruction Trap 39
Processor Detected Fau Its 39
Trap ConditIons During HAnti cipateJl Operations _ 42
Register Altered Bit 42
3. INSTRUCTION REPERTOIRE
44
Load/Store Instructions __________ _
Analyze/Interpret Instructions ________ _
Fixed-Point Arithmetic Instructions _____ _
Comparison
Instructions __________ _
Logical Instructions ____________ _
Shift Instructions~ ____________ _
Floating-Point Shift __________ _
Zoned Decimal Numbers ________ _
Decimal Accumulator __________ _
Decimal Instruction Format ________ _
Illegal Digit and Sign Detection _____ _
Overflow Detection __________ _
Decimal Instruction Nomenclature _____ _
Condition Code Settings _________ _
Byte-String Instructions __________ _
Push-Down
Instructions __________ _
Stack Pointer Doubleword (SPD) _____ _
Push-Down
Condition Code Settings ____ _
Execute/Branch Instructions ________ _
Branches in Real
Extended Addressing
Mode ______________ __
99
Nonallowed Operation Trap During Execution
of Branch Instruction _________ 99
CALL Instructions _________ 101
Control Instructions 102
Program Status Doubleword ______ 102
Loading the Memory Map __ 106
Loading the Access Protection Controls 107
Loading the Memory Write Protection
Locks _______________ 107
Interruption of MMC 108
Read Direct - Internal Computer Control
(Mode 0) ____________ 109
Read Direct, Interrupt Control
(Mode 1) _________________ _ 109
Write Direct - Internal Computer Control
(Mode 0) ____________ 110
Write Direct, Interrupt Control
(Mode 1) ____________________ 112
Input/Output Instructions 113
I/O Addresses 113
Processor Addresses
(Bits 19-23)
___________ 113
Device Controller Addresses
(Bits
24-31)--- __________ 113
I/O Unit Address Assignment 113
I/O Status Response 114
Status Information for SIO 114
General Registers _____________ 116
iii

4. INPUT/OUTPUT OPERATIONS
122 ControI Codes
138
Special Code Properties
138
Operational Command Doublewords
123
XDS Standard 8-Bit Computer· Codes (EBCDIC) __ 139
Order
123 XDS Standard 7-Bit Communi cation Codes
Memory
Byte Address 123 (USASCII) 139
Flags 123 XDS Standard Symbol-Code Correspondences __ 140
Byte Count 125 Hexadecimal Arithmetic 144
Control Command Doublewords 125
Addition Table 144
Multiplication Table 144
Table of Powers of Sixteen 10
145
5.
OPERATOR CONTROLS 127 Table of Powers
of Ten16 145
Hexadecimal-Decimal Integer Conversion Table_146
Processor ControI Pane I 127 Hexadecimal-Decimal Fraction Conversion
Table_152
ControI Mode 127 Table of Powers
of Two 156
POWER
·128 Mathematical Constants 156
MEMORY CLEAR
128
SYS RESET
128
I/O RESET
128
B.
SIGMA 9 INSTRUCTION LIST 157
LOAD
128
UNIT
ADDRESS 128
SENSE
128
NOT NORMAL 128
C.
INSTRUCTION TIMING 158
HALT
128
WAIT
129 Timing Considerations 158
RUN
129 Effects of Memory Interference 158
Program Status Doubleword 129 Effects of Indexing
158
INSERT
130 Effects of Indi rect Addressi ng 158
CPU RESET
130
INTERRUPT
130
ADDRESS STOP 130
D.
SYSTEM RELIABILITY AND MAINTAINABILITY 166
SELECT ADDRESS
131
DISPLA Y (switch) 131
System Maintainabi Iity Features 166
INSTR ADDR 131
CPU Features 167
DISPLAY (Indicator) 132 Main Memory Features
169
DISPLAY FORMAT
132
FORMAT SEL
132
Multiplexor Input/Output Processor
(MIOP) Features
169
DATA
132
STORE
132
High-Speed RAD I/O Processor (HSRIOP)
Features 170
COMPUTE
132
Maintenance Controls 133
Alarm
133
Margins
133
E.
GLOSSARY OF SYMBOLIC TERMS 171
PHASES
133
CLOCK MODE
133
SNAP
133
ILLUSTRATIONS
MEMORY MODE
134
OVERRIDE MODE
134 SIGMA 9 Computer System
vi
134
SCAN
l.
A Typical SIGMA 9 System 9
EXT DIO
135
2. Central Processing Unit
10
Operating Procedures 135 3. Information Boundaries
12
Loading Operation
135
4. Addressing Logic
16
Fetchi ng and Storing Procedure 137 5. Index Displacement
AI ignment (Real and
Virtual Addressing Modes) 21
6. Index Displacement
AI ignment {Real Extended
Addressing}
22
APPENDIXES
7. Generation of Actual Memory Addresses,
Virtual Addressing (SIGMA 9 Mode)
23
8. Generation of Effective Virtual Address,
Real
A.
REFERE NCE TABLES
138
Extended Addressi ng 24
9. Interrupt Priority Chain
29
XDS Standard Symbols and Codes
138
10. Operational States of an Interrupt Level 31
XDS Standard Character Sets
138
11. Processor Control Panel 127
iv

TABLES
8.
Status Word 1
53
9.
Status Word 2 53
1.
Homespace Layout
15
10. ANAL
YZE Table for SIGMA 9
Operation
2.
Computer Operating and Addressing Modes ___ 28 Codes
58
3. SIGMA 9 Interrupt Locations 29 11.
Floating-Point Number Representation
74
4.
Summary of SIGMA 9 Trap Locations
34
12. Condition Code Settings for
Floating-Point
5.
TCe Setting for Instruction Exception Instructions 76
Trap
(X
I
4D') 41
13. Status Response for
I/O Instructions 115
6.
Registers Changed at Time of a Trap Due to 14. Program Status Doubleword
(PSD)
an Operand Access 42 Indi
cation
129
7.
Status Word 0 52
C-l.
Basic Instruction Timing
J58
v

1. SIGMA 9 SYSTEM
INTRODUCTION
The XDS SIGMA 9 Computer System is a high-speed,
general-purpose digital computer system. It is designed
for a
variety of scientific, business data processing, and
time-sharing applications. A basic system includes a
central prbcessing unit (CPU), a main memory subsystem,
and an independent input/output subsystem .. Each major
system
element performs asynchronously with respect to
other elements.
The basic system can be
readi Iy expanded to accommodate
the user1s requirements. Main memory has addressing space
for four million words. Memory access paths can be in-
creased from the basic two ports to a maximum of 12 ports.
Input/output capability can be increased by adding more
input/output processors (lOPs), device controllers, and I/O
devices.
The CPU has a large instruction set that includes floating-
point and decimal instructions. A special feature called
1I100k-ahead
ll
enables the CPU to overlap instruction exe-
cution with memory accessing, thereby reducing program
execution time. A large main memory of up to 524,288
(512K) words
is provided. The memory consists of up to
16 modular units of 32,768 (32K) words each. The number
of ports in each memory unit can be expanded to allow
independent access to memory by up to 12 processors - either
CPUs or lOPs. Each bank operates asynchronously, and
address interleaving can be provided between adjacent
banks. This multibanK, multiaccess memory subsystem with
interleaving achieves system performance far in excess of
single memory bank designs. The SIGMA 9 system can in-
clude up to 11 independent I/O processors (limited only by
port expansion
capability) of two types -multiplexor I/O
processors and high-speed RAD I/O processors -which can
transfer data at rates up to three million bytes per second,
concurrent with CPU instruction execution.
The SIGMA 9 computer design is compatible with the
SIGMA 7 computer, so that SIGMA 7 programs will run
on SIGMA 9. Therefore, comprehensive, modular
soft-
ware, requiring no reprogramming is avai lable, including
operating systems, assemblers, compilers, mathematical
and uti Iity routines.
Reliabi lity, maintainabi lity, and avai labi lity have been
significantly improved over previous SIGMA computers.
A
partitioning feature, for example, permits faulty units or
an
entire subsystem, consisting of a CPU, memory un it,
lOP, and attached peripherals to be isolated from the sys-
tem for diagnosis and repair whi Ie the primary system
continues
operation.
This manual describes the general characteristics and
features, system organ ization, instruction set, I/O oper-
ations, operator controls, and timing of the system.
GENERAL CHARACTERISTICS
A SIGMA 9 computer system has features and operating
characteristics that permit efficient functioning in general-
purpose, multiprocessing, time-sharing, real-time, and
multiusage environments:
• Word-oriented memory (32-bit word plus parity bit)
which
can be addressed and a Itered as byte (8-bit),
halfword (2-byte), word (4-byte), and doubleword
(8-byte)
quantities.
• Memory expandable from 131,072 (l28K) to 524,288
(512K) words in blocks of 16,384 (16K), 32,768 (32K),
and 65,536 (64K) words. Expansion proceeds in 32K
blocks
from 128K to 256K, and in 64K blocks from
256K to 512K (where K = 1024 words).
• Direct addressing capability (real extended mode) of
entire memory.
• Indirect addressing with or without post-indexing.
• Displacement index registers, automati ca lIy self-
adjusting for all data sizes.
• Immediate operand instructions, for greater storage
effi ciency and increased speed.
• 16 general-purpose registers, expandable to 64 (in
blocks
of 16) reduce data transfer to and from reg-
isters in a multiusage environment.
• Hardware memory mapping, which virtually elimi-
nates memory fragmentation and provides dynamic
program
relocation.
• Four modes of memory access protection for system
and information security and protection.
• Memory write protection preventing inadvertent
destruction of critical areas of memory.
• Watchdog timer to assure nonstop operation.
• Real-time priority interrupt system with automatic
identification and priority assignment, fast response
time, and up to 238 levels that can be individually
armed, enabled, and triggered by program control.
• Instructions with long execution times can be in-
terrupted to guarantee response to interrupts.
• Automatic traps for error or fault conditions, with
masking
capabi lity and maximum recoverabi lity,
under program contro I.
• Power fail-safe for automatic, safe shutdown in
event of power fai lure.
SIGMA 9 System

•
•
•
Multiple interval timers with a choice of resolutions
for
independent time bases.
Privi leged instruction logic for program integrity
in multiusage environments.
Complete instruction set that includes:
• Byte, halfword, word, and doubleword
operations.
• Use of all memory-referencing instructions for
register-to-register operations, with or with-
out indirect addressing and post-indexing, and
within normal instruction format.
• Multiple register operations.
• Fixed-point integer arithmetic operations in
halfword, word, and doubleword modes.
• Floating-point hardware operations in short
and long formats with significance, zero, and
normalization control and checking, all
•
un der fu II program contro I.
Full complement of logical operations (AND,
OR, exclusive OR).
• Comparison
operations, including compare
between limits (with limits in memory or in
registers).
• Call instructions that permit up to 64 dyn-
amically variable, user-defined instructions,
and allow a program access to operating
system functions without operating system
intervention.
• Decimal hardware operations, including arith-
metic, edit, and pack/unpack.
• Push-down stack operations (hardware im-
plemented) of single or multiple words, with
automatic limit checking, for dynamic space
allocation, subroutine communication, and
recursive routine capabi lity.
• Automatic conversion operations, including
binary/BCD and any other weighted-number
systems.
•
Analyze instruction that facilitates effective
address computati on.
• Interpret instruction that increases speed of
interpretive programs.
• Shift operations (left and right) of word or
doubleword, including logical, circular,
arithmetic, searching shift, and floating-
point modes.
2
General Characteristics
•
•
Built-in reliabi lity and maintainabi lity features
that include:
•
Diagnostic programs with capabilities for: sys-
tem verification and testing to determine the
faulty unit; unit functional testing to deter-
mine the specific function of a unit that is
faulty; and fault location diagnosing to analyze
what physical component is malfunctioning.
• Extensive error logging. When a fault is de-
tected, system status and fault information are
available for program retrieval and logging for
subsequent analysis.
• Full parity checking on all data and addresses
communicated in either direction on busses be-
tween memory units and processors, providing
fau
It detection and location capabi lity to per-
mit the operating system or diagnostic program
to
quickly determine a faulty unit.
• Address stop feature that permits operator or
maintenance personnel to:
Stop on
any instruction address.
Stop on
any memory reference address.
Stop when
any word in a selected page
of memory is referenced.
• Programmable "snapshot" registers that enable
diagnostic routines to compare contents of a
snapshot
register with known correct informa-
tion, thus accurately determining system fault
conditions.
• CPU traps, which provide for detection of a
variety of CPU and system fault conditions,
designed to enable a high degree of system
recoverability.
• Partitioning features that enable system recon-
figuration. SIGMA 9 un its can be partitioned
from the system by selectively disabling them
from busses. Thus, faulty units or an entire
subsystem, consisting of a CPU, memory unit,
input/output processor (lOP), and attached
peripherals, can be isolated from the oper-
ational system to enable diagnosis and repair
of a faulty unit while the primary system con-
tinues operation.
Independently operating I/O system with the fol-
lowing features:
• Direct input/output of a full word, without
use
of a channel.
• Up to eleven I/O processors (restricted only
by port limitations).
• Multiplexor I/O processors (MIOP) with dual
channel capability, providing forsimultaneous

•
•
operation of up to 24 devices on one channel,
and concurrently, simultaneous operation of
eight devices on the other channel.
• High-speed Rapid Access Data I/O processor
(HSRIOP) for use with XDS high-speed RAD
storage units, allowing data transfer rates of
up to three million bytes per second.
• Both data and command chaining, for gather-
read and scatter-write operations.
• Up to 32,000 output control signals and in-
put test signals.
Comprehensive
array of modular software that is
program compatible with XDS SIGMA 5, 6, and 7
computers:
• Expands in capability and speed as system
grows.
• Operating systems: Batch Processing Monitor
(BPM), Batch Time-Sharing Monitor (BTM),
Real-Time Batch Monitor (RBM), Universal
Time-Sharing System (UTS),
and Xerox Oper-
ating System (XOS).
• General-Purpose Compilers: Extended XDS
FORTRAN IV, XDS FORTRAN IV-H, BASIC,
and FLAG.
• Assemblers: Symbol, Macro-Symbol, and
Meta-Symbo I.
• Library: Mathematical, utility, and input/
output programs.
• Business software: Data Management System
(DMS-l), Generalized Sort and Merge, XDS
ANS COBOL, Manage, Terminal-Oriented
Manage, and 1401 Simulator.
• Application software: Functional Mathemati-
cal Programming System (FMPS), FMPS
Matrix Generator/Report Writer (GAMMA 3),
Simulation Language
(S L-1), Circuit Analysis
Systems (CIRC-AC, CIRC-DC),
and Graphic
Display Library (GDL-l).
Standard and special-purpose peripheral equip-
ment including:
• Rapid Access Data (RAD) files: Capacities to
6.2 million bytes per unit; transfer rates of
three mill ion bytes per second; average access
times from 17
mi IIiseconds.
• Magnetic tape units: 7-track and 9-track
systems, IBM-compatible; high-speed units
operating at 150 inches per second with trans-
fer rates up to 120,000 bytes per second; and
other units operating at 75 inches per second
with transfer rates up to 60,000 bytes per
second
and at 37.5 inches per second with
transfer
rates up to 20,800 bytes per second.
• Displays: Graphic display has standard char-
acter generator, vector generator, and c lose-
ups, as well as iight pen, and alphanumeric/
function keyboard.
• Card equipment: Reading speeds up to 1500
cards per minute; punching speeds up to 300
cards per minute; intermixed binary and
EBCDIC card codes.
• Line printers: Fully buffered with. speeds up
to 1,500 lines per minute; 132 print positions
with
64 characters.
• Keyboard/printers: 10 characters per second;
also
available with paper tape reader (20char-
acters per second) and punch (l0 characters
per second).
• Paper tape equipment; Readers with speeds up
to 300 characters per second; punches with
speeds
up to 120 characters per second.
• Graph plotters: Digital incremental, provid-
ing drift-free plotting in two axes in up to
300 steps per second at speeds from 30 milli-
meters to 3 inches per second.
• Data communications equipment: Complete
line
of character-oriented and message-
oriented equipment to connect remote user
terminals (including remote batch) to
the
computer system via common carrier lines
and local terminals directly.
GENERAL-PURPOSE FEATURES
General-purpose computing applications are characterized
by emphasis on computation and internal data handling.
Many operations
are performed in floating-point format and
on strings of characters. Other typical characteristics
include decimal arithmetic operations, binary to decimal
number conversion (for printing or display),
and consider-
able input/output at standard speeds. The SIGMA 9 com-
puter system includes the following general-purpose
features.
Floating-Point Hardware. Floating-point instructions are
available in both short J32-bit) and long (64-bit) formats.
Under program
control, the user may select optional zero
checking, normalization, and significance checking (which
causes a
trap when a post-operation shift of more than two
hexadecimal places occurs in the fraction of a f/oating-
point number). Significance checking permits use of the
short floating-point format for high processing speed and
storage economy and of the long format when loss of
signifi cance is detected.
Genera I-Purpose Features 3

Decimal Arithmetic Hardware. Decimal arithmetic
instructions operate on up to 31 digits plus sign. This in-
struction set includes pack/unpack instructions for con-
verting to/from the packed format of two digits per byte,
and a genera Ii zed edit instruction for zero suppression,
check protection, and formatting, with punctuation to
display or print it.
Indirect Addressing. Indirect addressing faci litates table
linkages and permits keeping data sections of a program
separate from procedure sections for ease of maintenance.
Displacement indexing. Indexing by means of a "floating"
displacement permits accessing a desired unit of data
without considering its size. The index registers automati-
ca lIy al ign themselves appropriately; thus, the same index
register may be used on arrays with different data sizes.
For example, in a matrix multipl ication of any array of full
word, single-precision, fixed-point numbers, the results
may be
stored in a second array as double-precision numbers,
using
the same index quantity for both arrays. If an index
register contains the value of k, then the user always ac-
cesses the kth element, whether it is a byte, halfword,
word, or doubleword. Incrementing by various
quantities
according to data size is not required; instead, incrementing
is always by units in a continuous array table regardless of
the size of data element used.
Instruction
Set. More than 100 major instructions permit
short, highly optimized programs to be written, which are
rapidly assembled and minimize both program space and
execution time.
Translate Instruction. The Translate instruction permits
rapid translation between any two 8-bit codes; thus data
from a variety of input sources can be handled and recon-
verted easi Iy for output.
Conversion Instructions. Two generalized conversion in-
structions provide for bidirectional conversions between
internal binary and any other weighted number system, in-
cluding BCD.
Call Instructions. These four instructions permit handling
up to 64 user-defined subroutines, as if they were built-in
machine instructions, and gaining access to specified op-
erating system services without requiring its intervention.
Interpret Instruction. The Interpret instruction simplifies
and speeds interpretive operations such as compilation,
thus reducing space and time requirements for compi lers and
other interpretive systems.
Four-Bit
Condition Code. This simpl ifies the checking of
results by automatically providing information on almost
every instruction execution, including indicators for over-
flow, underflow, zero, minus, and pi us, as appropriate,
without requiring an extra instruction execution.
4 Input/Output Capabi lities/fime-Sharing Features
INPUT jOUTPUT CAPABILITIES
Multiplexing Input/Output Processor (MIOP). Once
initialized, I/o processors operate independently of the
CPU, leaving it free to provide faster response to system
needs. The MIOP requires minimal
interaction with the
CPU by using channel command doublewords, which per-
mit both command chaining and data chaining without in-
tervening CPU control. I/O equipment speeds range from
slow rates involving human
interaction (teletypewriter, for
example) to transfer
rates of rotating memory devices of
up to one million bytes per second. Many devices can be
operated simultaneousIy.
Direct Data Input/Output (DIO). DIO facilitates in-line
program control of asynchronous or special-purpose devices.
With this feature information can be transmitted directly to
or from general-purpose registers so that an I/O channel
need not be used for relatively infrequent transmissions.
High-Speed RAD Input/Output Processor (HSRIOP). This
feature
is simi lar to multiplexing input/output except that
one RAD per channel controller is operating at a time.
This
high-speed channel contains the buffering and priority
logic sufficient to sustain transfer rates up to three million
bytes per second. In a typical time-sharing application,
this enables a program swap into or out of main memory in
less than 40 milliseconds.
TIME-SHARING FEATURES
Time-sharing is the ability of a system to share its total
capacities among many users at the same time. Each user
can be performing a different task (requiring a different
share of the available resources) and may be on-line in an
interactive, "conversational" mode with the computer.
Other users may be entering work to be processed that
requires on Iy final output.
The SIGMA 9 system provides the time-sharing computer
features
described below.
Rapid
Context Saving. When changing from one user to
another, the operating environment can be switched
quickly and easily. Stack-manipulating instructions per-
mit storing in a push-down stack of 1 to 16 general-purpose
registers by a single instruction. Stack status is updated
automatically and information in the stack can be retrieved
when needed (also, by a single instruction). The current
program status doubleword (PSD), which contains the entire
description of the current user's environment and mode of
operation, can be stored anywhere in memory and a new
PSD loaded, all with a single instruction.
Multiple Register Blocks. The optional avai labi lity of up
to four blocks of 16 general-purpose registers improves re-
sponse time by reducing the need to store and load register
blocks. A
distinct block can be assigned for different func-
tions as needed; the program status doubleword automati-
cally selects the applicable register block.

User Protection. The slave mode feature restricts each
user to his own set of instructions whi Ie reserving to the
operating system certain "privileged" {master mode) instruc-
tions that could destroy another user's program if used in-
correctly. Also, a memory access-protection system pre-
vents a user From accessing any storage areas other than
those assigned to him. It permits
him to access certain
areas for reading only, such as those containing public sub-
routines, while preventing him from reading, writing, or
accessing instructions-in areas
set aside for other users.
Storage Management. SIGMA 9 memory
is available in
sizes
from 128K (l31,072)words to 512K (524,288) words to
provide the capacity needed while assuring the potential
for expansion. To make efficient use of available memory,
the memory map hardware permits storing a user's program
in fragments as small as a page of 512 words wherever
space is avai lable; yet a II fragments appear as a singIe,
contiguous block of storage at execution time. The memory
map also
automatically handles dynamic program relocation
so that the program appears to be stored in a standard way
at execution time, even though it may actua lIy be stored
in a different set of locations each time it is brought into
memory. The memory map
for SIGMA 9 can operate in a
compatible SIGMA 7 mode in addition to providing
the
ability to locate any 128K-word (131,072) virtual program
in
the SIGMA 9's logical addressing space of four million
words. Thus,
the system can always address a virtual
memory
of 128K words regardless of physical memory size.
Input/Output CapabiIity. Time-sharing input/output re-
quirements are handled by the same general-purpose input/
output capabilities described under "General-purpose
Features II.
Nonstop Operation. A IIwatchdog II timer assures that the
system continues to operate even in case of halts or delays
due to failure
of special I/O devices. Multiple real-time
clocks with varying resolutions permit independent time
bases for flexible
allocation of time slices to each user.
REAL-TIME FEATURES
Real-time applications are characterized by a need for
(1) hardware that provides qu ick response to an externa I
environment, (2) speed great enough to keep up with the
real-time process itself, and (3) sufficient input/output
flexibi lity to handle a wide varietyof data types at varying
speeds. The SIGMA 9 system includes provisions for
the
following real-time computing features.
Multilevel, True Priority Interrupt System. The real-time-
oriented SIGMA 9 system provides quick response to inter-
rupts by means of up to 224 external interrupt levels. The
source
of each interrupt is automatically identified and
responded to according to its priority. (This function must
be programmed.)
For further flexibi lity, each level can be
individually disarmed (to discontinue input acceptance) and
disabled (to defer responses). Use of the disarm/disable fea-
ture makes programmed dynamic reassignment of priorities
quick
and easy, even while a real-time process is in
progress. In establishing a configuration for the system,
each group of up to 16 interrupt levels can have its prior-
ity assigned in different ways to meet the specific needs
of a problem; the way interrupt levels are programmed is
not affected by the priority assignment.
Programs
that deal with interrupts from specially designed
equipment sometimes must be
checked out before the equip-
ment is actually available. To permit simulating this spe-
cia I equipment, any SIGMA 9 interrupt level can be
IItriggered
ll
by the CPU through execution of a single in-
struction. This capability is also useful in establishing a
hierarchy
of responses. For example, in responding to a
high-priority interrupt, after the urgent processing is com-
pleted, it may be desirable to assign a lower priority to
the remaining portion so that the interrupt routine is free
to respond to
other critical stimuli. The interrupt routine
can accomplish this by triggering a lower-priority level,
which processes the remaining data only after other inter-
rupts have been handled.
Certain instructions (READ DIRECT and WRITE DIRECT,
described in Chapter 3) allow the program to completely
interrogate the condition of the interrupt system at any time
and
to restore that system at a later time.
Nonstop Operation. When connected to special devices
(on a ready/resume basis), the computer can sometimes
become
excessively delayed if the special device does not
respond
quickly. A built-in watchdog timer assures that
the SIGMA 9 computer cannot be delayed for an excessive
length
of time.
Real-Time Clocks. Many
real-time functions must be timed
to
occur at specific instants. Other timing information is
also needed -for example, elapsed time since a given
event / or the current time of day. SIGMA 9 can contain
up to four real-time clocks with varying degrees of re-
solution to meet these needs. These clocks a Iso allow
easy handling of separate time bases and relative time
priorities.
Rapid
Context Switching. When responding to a new set of
interrupt-initiated circumstances, a computer system must
preserve
the current operating environment/for continuance
later, while setting up the new environment. This changing
of environments must be done quickly, with a minimum of
1I0verhead
ll
time costs. In the SIGMA 9 system/ each one
of up to four blocks of general-purpose arithmetic registers
can, if desired, be assigned to a specific environment. All
relevant "information about the current environment (instruc-
tion address,
current general register block, memory-
protection
key/etc.) is kept in a 64-bit program status
doubleword (PSD). A
single instruction stores the current
PSD anywhere in memory and loads a new one from memory
to establish a new
environment/which includes informatic:>n
identifying a new block of general-purpose registers. A
SIGMA 9 system
can thus preserve and change its operating
environment completely through the execution of a single
instruction.
Rea 1- Ti me Features 5

SIGMA 9 Computer System
vi

Memory Protection. Both foreground (real-time) and
background programs can be run concurrently in a SIGMA 9
system
because a foreground program is protected against
destruction by an unchecked background program. Under
operating system control, the memory access-protection
feature prevents accessing memory for specified combina-
tions of reading, writing, and instruction acquisition.
Variable Precision Arithmetic. Much of the data encoun-
tered in real-time systems are 16 bits or less. To process
this
data efficiently, SIGMA 9provides halfword arithmetic
operations in addition to fullword operations. Doubleword
arithmetic operations (for extended precision) are also
included.
Direct Data Input/Output. For handling asynchronous I/O,
a 32-bit word can be transferred directly to or from a
general-purpose register so that an I/O channel need not
be occupied with relatively infrequent and nonperiodic
transm iss ions.
MULTI USAGE FEATURES
As implemented in the SIGMA 9 system, IImultiusage
ll
com-
bines two or more computer application areas. The most
difficult general computing problem is the real-time appli-
cation because of its severe requirements. Similarly,
the most difficult multiusage problem is a time-sharing
application that includes one or more real-time processes.
Because
the SIGMA 9 system has been designed on a real-
time base, it is uniquely qualified for a mixtureof applica-
tions in a multiusage environment. Many hardware features
that prove valuable for certain application areas are equally
useful in others, although in different ways. This multiple
capability makes SIGMA 9 particularly effective in mu Iti-
usage applications. The major SIGMA 9 multiusage com-
puter features are described below.
Priority Interrupt. In a multiusage environment, many ele-
ments operate asynchronously. Thus, having a true priority
interrupt system (as in SIGMA 9) is especially important.
With it
the computer system corresponds quickIy, and in
proper order, to the many demands being made upon it,
without the high overhead costs of complicated programming
lengthy execution time, and extensive storage allocations.
Quick Response. The many features that combine to pro-
duce a quick-response system (multiple register blocks,
rapid context saving, multiple push-pull operations) bene-
fit all users because more of the machine's power is avai 1-
able at any instant for useful work.
Memory
Protection. The memory protection features not
only protect each user from every other user, they also
guarantee the integrity of programs essential to critical
real-time appl ications.
Input/Output. Because of its wide range of capacities and
speeds, the SIGMA 9 I/O system simultaneouslysatisfiesthe
needs of many different application areas economically,
both in terms of equipment and programming.
6
Multiusage/Multiprocessing Features
Instruction
Set. The large SIGMA 9 instruction set
provides the computational and data-handling capabilities
required for widely differing application areas; therefore,
each user IS program length and running time is decreased,
and the speed of obtaining results is increased.
MULTIPROCESSING FEATURES
SIGMA 9 is designed to function as a shared-memory
multiprocessor system. It can contain up to four central
processing units and up to n input/output processors
(the
sum of both types of processors is restricted by the
maximum memory port limitation of 12). All processors in
a
SIGMA 9 system address memory uniformly.
This
section describes the major features of SIGMA 9 that
wi" allow growth from a monoprocessor to a multipro-
cessor system.
MULTIPROCESSOR INTERLOCK
In a multiprocessor system, the central processing units
(CPUs)
often need exclusive control of a system resource.
This resource may be a region of memory, a particular
peripheral device or, in some cases, a specific software
process. SIGMA 9 has a special instruction to provide this
required multiprocessor interlock. The special instruction,
LOAD AND SET, unconditionally sets a 111" bit in the sign
position
of the referenced memory location during the re-
store cycle of the memory operation. If this bit had been
previously set by another processor, the interlock is said
to be IIset" and the testing program proceeds to another task.
On the other hand, if the sign bit of the tested location is
a zero, the resource is allocated to the testing processor,
and simultaneously the interlock is set for any other
processor.
HOMESPACE
Since all processors in a multiprocessor system address
memory
ina un iform manner, it is necessary to reta ina pr i-
vate memory that is un ique to each processor for its trap
and interrupt locations, I/O communication locations, etc.
This private memory is called Homespace and consists of
1,024 words for each CPU. Each Homespace region begins
with
real address zero. The implicitly assigned trap loca-
tions, interrupt locations, and lOP commun ica tion loca-
tions, plus the 16 locations that are reserved for the regis-
ters, occupy the first 320 locations of Homespace. The
remaining words in
the Homespace region can be used as
private, independent storage by the CPU.
MUL TIPORT MEMORY SYSTEM
SIGMA 9 has growth capabi Iity of up to 12 ports per mem-
ory
unit. A basic memory unit consists of two banks of
16K words each, in which each bank can be concurrently
operating when addressed by two of the possible 12 ports.

This system architecture allows flexibi lity in growth patterns
and provides large amounts of memory bandwi dth, essentiaI
to multiprocessor systems.
MANUAL PARTITIONING CAPABILITY
SIGMA 9 has manual partitioning capability for all system
units. Thus, besides its primary
advantage of increased
throughput capabi lity, a secondary advantage of a multi-
processor system is its fai I-soft abi lity. Any SIGMA 9 unit
can be partitioned by selectively disabling, it from the
system busses. Faulty units are thus isolated from the oper-
ational system. Reenabling the connection allows repaired
units to be returned to service.
MULTIPROCESSOR CONTROL FUNCTION
A multiprocessor control function is providedon a II multipro-
cessor systems. This function provides three basic features:
1. Control of the External Direct Input/Output bus
(External DIO), used for controlling system
2.
maintenance and special purpose units such as
AID converters.
Central control of system partitioning.
3. Interprocessor interrupt connection, a !lowing
one processor to directly signal another pro-
cessor that an action is to be taken.
SHAREDINPUT/OUPUT
Provisions have been made in a SIGMA 9 mul tiprocessor
system for
any CPU to direct I/O actions to any I/O pro-
cessor. This is, any CPU can issue an SIO, no, TDV,
or HIO instruction to
begin, stop, or test any I/O pro-
cess. However, the end-action sequence of the I/O
process is directed at one of the possible four CPUs.
This feature (accomplished by setting a pair of config-
uration control switches) allows dedicating I/O end-
action tasks to a single processor and avoids conflict
resolution problems.
Multiprocessing Features 7

2. SIGMA 9 SYSTEM ORGANIZATION
The primary elements of a basic SIGMA 9 computer
system, as illustrated in Figure 1, are central processor
units, memory units, and input/output processors. These
elements permit the total computer system to be viewed
as a group of program-control I ed subsystems commun i-
cati ng wi th a common memory. Each subsystem operates
asynchronously and semi-independently, automatically
overlapping the operation of the other subsystems for
greater speed (when circumstances permit). A CPU sub-
system primarily performs overall control and data re-
duction tasks while each lOP (MIOP or HSRIOP)
subsystem performs the tasks associated wi th the exchange
of digital information between the main memory and
selected peripheral devices. A basic system may be
expanded by increasing the number of memory units (up
to 16), increasing the number of lOPs (up to 11, in-
cluding MIOPs and HSRIOPs), or by increasing the num-
ber of central processors (up to 4).
CENTRAL PROCESSING UNIT
This section describes the organization and operation of the
SIGMA 9 central processing unit in terms of instruction
and data formats, information processing, and program
control. Basically, a SIGMA 9 CPU consists of a fast
memory
and an arithmetic and control unit as illustrated
in Figure 2.
GENERAL REGISTERS
An integrated-circuit memory, consisting of sixteen 32-bit
general-purpose registers, is used within the SIGMA 9
CPU. These 16 registers of fast memory are referred to as
a
register block. A SIGMA 9 system may contain up to
4
register blocks. A 4-bit control field (called the reg-
ister block pointer) in the Program Status Doubleword (PSD)
selects the block currently available to a program. The
16
general registers selected by the register block pointer
are referred to as the current register block. The register
block pointer can be changed when the computer is in the
master or master-protected mode.
Each
general register in the current register block is identi-
fied by a 4-bit code in the range 0000 through 1111
(0 through 15 in decimal, or X'O' through X' F' in hexa-
decimal notation). Any general register may be used as a
fixed-point accumulator, floating-point accumulator,
temporary data storage location, or to contain control in-
formation such as a data address, count, pointer, etc.
General registers 1 through 7 may be used as index regis-
ters, and registers 12 through 15 may be used as a decimal
accumulator capable of containing a decimal number of
31 digits plus sign. Registers 12 through 15 are always
used when a dec imal instruction is executed.
8 SIGMA 9 System Organization
MEMORY CONTROL STORAGE
The CPU has three high-speed integrated-circuit memories
for
storage of a memory map, memory access protection
codes associated with the memory map, and memory write-
protection codes. This storage can be changed when the
computer is in the master or master-protected mode.
Memory
Map. Two terms are essential to a proper under-
standing of the memory mapping concept: virtual address
and actual address.
A
virtual address is a value pertaining to the logical space
used by a machine-level program, and which designates
the location of an instruction, the location of an element
of data, or the location of a data address (indirect address).
It may also be an explicit quantity. Normally, virtual
addresses are derived from programmer-supplied labels
through an assembly (or compilation) process followed by a
loading process. Virtual addresses may also be computed
during a program's execution. Thus, virtual addresses in-
clude all instruction addresses, data addresses, indirect
addresses, and addresses used as counts within a stored pro-
gram, as well as those addresses computed by the program.
An
actual address is a value used within the memory unit
(memory address register) to access a specific memory
location for storage or retrieval of information, as required
by the execution sequence of an instruction. Thus, actual
addresses are fixed and dependent on the wired-in hard-
ware. (See "Main Memory" for further details.)
The memory map feature provides for dynamic program
relocation into discontinuous segments of memory. When
the memory map is in effect, any program may be broken
into 512-word pages and distributed throughout memory in
whatever pages of space are available. Thus the memory
map transforms virtual addresses, as seen by the individual
program, into actua I addresses, as seen by the memory
system.
When
the memory map is not in effect, as determined by
the memory map control bit in the program status double-
word, all virtual address values above 15 are used by the
memory as actual addresses. Virtual addresses in the range
o through 15 are always used by the CPU as general register
addresses rather than as memory addresses. Thus, for exam-
ple, if an instruction uses a virtual address of 5 as the
address where a result is to be stored, the result is stored
in
general register 5 in the current register block instead
of in memory location 5.
When the computer is operating with memory map, virtual
addresses in the range 0 through 15 are still used as general
regi ster addresses. However, all vi rtual addresses above 15
are transformed into actual addresses, by replacing the high-
order portion of the virtual address with a value obtained
from the memory map. (The memory map replacement pro-
cess is described in the section "Memory Address Control II • )

Memory Unit
• 32,768 words
.900 ns
• Dual banks
• Up to 12 ports
tMemory bus
Processor bus
Memory Unit
• 32,768 words
• 900 ns
• Dual banks
• Up to 12 ports
j
r---------,
I Memory Unit I
I I
I • 32,768 words I
I • 900
ns I
: • Dual banks :
1 •
Up to 12 ports 1
L. ________ ...I
j j J
Memory bus
Memory bus
1
Separate memory bus ~ .
, ,Ir , 1 ,
MIOP I
~-....&. ...... ------.... r-------,
CPU 1 MIOP I r
l
-HS"Ri'O'P'
8 sub-
channels
8 sub- I8 sub- I8 sub- i
channels I channels I channels 1
(option) I (option) I :
• Decimal arithmetic unit
• Memory protect
• Memory map
I 1 ____ 1 • Memory
access protect
I At
Chan- 1
Channe t
nel B I • 2 register blocks
• 2 clocks
'---r-----~----- --I'" -..J • Power
fail-safe
t 4 byte interfa ce j
option •
Floating-point arithmetic
I/O bus
1
.-- ~--1
• Multi- 1
: device 1
1
controller •
Io __ .- __ J
j~
,..._.:.~ __ ... . __ 1 __ .,
1
1/0 device
l
• • I/O device 1
I 1 1
• ." " "I 1
I a • I 15 I
.. -----1 • _____ ....
• External interface
• 8 interrupt levels
I/O bus
.. __ 1 __ , . __ ~ __ ....
: Single .: Single :
I device • 1 device •
~~j~~~ ~:~I~~:~
• I/O devi ce I I I/O devi ce·1
L- _____ .I .... ____ ....
.. __ i __ ...,
I Removable •
• disk
unit I
I I
I • 2 spi nd Ies I
L. _____ ~
Figure 1. A Typical SIGMA 9 System
1 1
1 1
" " .
I •
1 1
1 1 • •
• RAD I
1 I
1 I
: 1
.... ---r---
J
To associated I/O
device controllers
If
r--~--'
• Disk unit I
I controlI
er I
I •
I • 4 byte I
• lOP I
• 1
1 1
1 1
L _____ J
j~
I/O bus
L-~Jte~~eJ
r-- --...,
I Removable I
r-----...,
17212 storage! ...
I disk unit •
I I
I • 2 spindles I
L _____ -I
I unit •
.. ----- ....
r-----'
I 7212 ~ ..
• I
L _____ .J
Central Processing Unit 9

CPU FAST MEMORY
ARITHMETIC AND CONTROL UNIT
GENERAL REGISTER BLOCK (TYPICAL)
INSTRUCTION REGISTER
aI I
I
::::::::::::::::::::::
.:.' .:.:.:.:: ... : .. ::.:)t::::::· .::::::::::,.,:::;::, :,,:,::::::':' .:.:':'::'::'::':::':::'::'::"::::"::':.:::·1
1 {:tttt, :::::::}::,:::::::::,::,,:::::,: ,:::::::::::}::::}}:::,::} .
2 r::::I::::: :{:'::::::.:.::::\::::::\/:?: ... :::::::::'::::::::::::::;:;:;:;:;:;:;:;:;:;:;::::: :tI::::::::It·::1
t················· :-:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:-:.:.:.:-:.: ':':':':':':':""1
3 1:::::::::::::::::::1:11::: .':::':::::':::::::::::::::::::. :':-'-:':-:"':""':'::':::',::':':::'::::':':':' ':::r:::r::;
4 1:::::::::::::::I:I:::::::::t::::::::::: ::::::::::::::::::: :::::::,.:':'::r:::::::'::::;::.:?::::!:!:::!} :::::I::::::I
5 1:::::::::I::r:::I:::::::::::::::::::::::::::::::::::::::::: ::::::::}~::: f't:::t::}::::::':::: i::::::: I:::::]
6 1:::::::::::::::::::tf:tII:::::::::::::::::::t:::::::::::::::::::::::::::::::::::::I::::::::::::::::::::::::::::II::::tl
7 II::::i::::::::I:I::::i:i(:::::it:t::i:::::i:::i{:::::::::i::t:t::I::::: J:::::::j::::!j@t::::::::::::1 ~
8~1 ______________ ~
9~1 ______________ ~
10~1 ________________ ~
11 ~I ________________ ~
12~1 ________________ ~
13~1 ________________ ~
14 ~I __________________ ~
15
MEMORY CONTROL STORAGE
Memory Map
1-256 13-bit page addresses -I
Memory Access Protection
II I I III 1IIIIII1 ~ ~"'-+-'-II"""""""I II
1-- 256 2-bit access codes --I
Memory Write Protection
It IllllllllllllsffiIIJ
1----- 256 2-bit write locks --I
10 Central Processing Unit
Index
Registers
o Indirect Address Flag
o
III IIII I Operation Code Field
1 7
DIIJ General Register Designator
8 11
OJ] Index Register Designator
12 14
Reference Address Field
I1111111111111111111
15 31
........ -- ...
Memory
I
31-digit
Decimal
Accumu-
lator
I/O Processors I
I I
I
Read/Write Direct
I •
.------------,1 Interrupts
I I
Priority Interrupt System I Write Direct
I
PROGRAM STATUS DOUBLEWORD
OJ]] Condition Code
o 3
[ill Floating-point Mode Control
5 7
o Master/Slave Mode Control
8
oMemory Map Control
9
[I] Arithmetic Trap Masks
1011
DASCII Control
12
Instruction
r-r-,...,...,...,..-r-r""T"'"'1I'"""T'"",....,...,...,..-r-r-, Addre ss
IJ I II II II I II " \I II or
15 31 Extended
OJ Write Key
3435
OJ] Interrupt Inhibits
37 39
o Mode Altered Control
40
III I II IExtension Address
42 47
Displacement
IIIIIIII1 Trapped Status Field
48 55
IllJJ Register Block Pointer
56 59
oRegister Altered
60
I
Figure 2. Central Processing Unit

Memory Access Protection. When the computer is operating
in the slave or master-protected mode with the memory map,
the access-protecti on codes determine whether or not the
program may access instructions from, read from, or write
into specific regions of the virtual address continuum (vir-
tual memory). If the slave or master-protected mode pro-
gram attempts to access a region of virtual memory that is
so
protected, a trap occurs. (The access-protecti on codes
are described in the section "Memory Address Control ".)
Memory Write Protection. The memory write-protection
feature operates independently of the memory map and
access protection. The memory write-protec'tion feature
includes the necessary integrated-circuit memory for the
memory write locks. These locks operate in conjunction
with a 2-bit field, called the write key, in the program
status
doubleword. The locks and the key determine
whether any program may alter any word located within the
first 128K words of main memory. The write key can be
changed when the computer is in the master or master-
protected mode. (The functions of the locks and key are
described in the section "Memory Address Control".)
COMPUTER MODES
A SIGMA 9 computer operates in either master, slave, or
master-protected mode. The mode of operation is deter-
mined by three control bits in the program status double-
word. (See" Program Status Doubleword".)
MASTER MODE
In this mode, the cpu. can perform all of its control func-
tions and can modify any part of the system. The only re-
strictions placed upon the CPUls operation in this mode is
that imposed by the write locks on certain protected parts
of memory. The Mode Altered control bit (PSD bit po-
sition 40) must also be zero for the computer to operate
in a SIGMA 7-compatible master mode. It is assumed that
there is a resident operating system (operating in the master
mode)
that controls and supports the operation of other pro-
grams (which may be in the master, slave, or master-
protected mode).
SLAVE MODE
The slave mode of operation is the problem-solving mode of
the computer. In this mode, access protection codes apply
to the slave mode program if mapping is in effect, and all
"privileged" operations are prohibited. Privileged opera-
tions are those relating to input/output and to changes in
the basic control state of the computer. All privileged
operations are performed in the master or master-protected
mode by a group of privileged instructions. Any attempt by
a program to execute a privileged instruction while the
computer is in the slave mode results in a trap. The master/
slave mode control bit can be changed when the computer
is in the master or master-protected mode. However, a
slave mode program can gain direct access to certain ex-
ecutive program operations by means of CALL instructions
without requi ri ng executive program intervention. The
operations available through CALL instructions are estab-
Iished by the resident operating system.
MASTER-PROTECTED MODE
The master-protected mode of operation is a modification of
the master mode designed to provide additional protection
for programs that operate in the master mode. The master-
protected mode can only occur when the CPU is operating
in the master mode with the memory map in effect. In this
mode, a trap will occur to the memory protection violation
trap (Homespace location X1 40
1, with CC4 = 1), as
it does
in
all mapped slave programs, ifa program makes a reference
to a virtual page to which access is prohibited by the cur-
rent setti ng of the access protection codes.
INFORMATION FORMAT
Nomenclature associated with digital information within the
SIGMA 9 computer system is based on functional and/or
physical attributes. A "word" of digital information may
be either an instruction word or a data word.
The
basic element of SIGMA 9 information is a 32-bit word,
in which the bit positions are numbered from 0 through 31,
as follows:
A
SIGMA 9 word can be divided into two 16-bit parts
(halfwords) in which the bit positions are numbered from
othrough 15, as follows: '
A SIGMA 9 word can also be divided into four 8-bit parts
(bytes) in which the bit positions are numbered from
othrough 7, as follows:
Byte 1 Byte 2
234567012345
Two SIGMA 9 words can be combined to form a 64-bit
element (a doubleword) in which the bit positions are
numbered from 0 through 63, as follows:
Central Processing Unit 11

For fixed-point binary arithmetic, each element of
information represents numerical data as a signed integer
(bit 0 represents the sign, remaining bits represent the mag-
nitude, and the binary point is assumed to be just to the
right of the least significant or rightmost bit). Negative
values are represented in two's complement form. Other
formats required for floating-point and decimal instructions
are described in Chapter 3.
INFORMATION BOUNDARIES
SIGMA 9 instructions assume that bytes, halfwords, and
doublewords are located in main memory according to the
following boundary conventions:
1. A byte is located in bit positions 0 through 7,
8 through 15, 16 through 23, or 24 through 31 of a
word.
2. A halfword is located in bit positions 0 through 15
or 16 through 31 of a word.
3. A doubleword is located so that bits 0 through 31 are
contained within an even-numbered word, and bits 32
through 63 are contained with in the next consecutive
(odd-numbered) word.
The various information boundaries are illustrated in
Figure 3.
INSTRUCTION REGISTER
The instruction register contains the instruction that is cur-
rently be ing executed by the CPU. The format and fields
of the two general types of instructions (immediate operand
and memory-reference) are described below.
MEMORY-REFERENCING INSTRUCTIONS
Most SIGMA 9 CPU instructions make reference to an
operand located in main memory. The format for this type
of instruction is
i Doubleword
I
•
I Word
(even address) Word (odd address)
!
i Halfword 0 Halfword 1 Halfword 0 Halfword 1
I
!Byte 01 Byte 1 Byte
21 Byte 3 Byte 0 IByte 1 Byte 21 Byte 3
Bits
o
1-7
8-11
Description
This bit position indicates whether indirect ad-
dressing is to be performed. Indirect addressing
(one level only) is performed if this bit position
contains a 1 and is not performed if this bit posi-
tion contains a O.
Operation Code. This 7-bit field contains the
code that des ignates the operation to be performed.
See the inside front and back covers as well as
Append ix B for complete Iistings of operation codes.
R field. For most instructions this 4-bit field des-
ignates one of 16 general registers of the current
register block as an operand source, result destina-
tion, or both.
12-14 X field. Th is 3-bit field designates anyone of
general registers 1-7 of the current register block
as an index register. If X is equal to 0, indexing
will not be performed; hence, register 0 cannot be
used as an index register. (See "Address Modifi-
cation Exampl es II for a more complete description
of the SIGMA 9 indexing process.)
15-31
Reference Address. This 17-bit field normally
contains the reference address of the instruction
operand. Depending on the type of addressing
(real, real extended, or virtual) and address mod i-
fication (direct/indirect or indexing) required,
the reference address is transl ated into an effec-
tive virtual address. (See "Memory Reference
Addresses" for further details.)
IMMEDIATE OPERAND INSTRUCTIONS
Some SIGMA 9 CPU instructions are of the immediate
operand type, which is particularly efficient because the
required operand is contained within the instruction word.
Hence, memory reference, indirect addressing, and index-
ing are not required.
Doubleword 1
I
I
.
Word (even address) Word (odd address) I
I
Halfword 0 Halfword 1 Halfword 0 Halfword 1 :
I
Byte 0 1Byte 1 Byte
2\ Byte 3 Byte 0 IByte 1 Byte
21 Byte 3!
Figure 3. Information Boundaries
12
Central Processing Unit