Yamaha YMF795 User manual

YMF795
APL-2
Automobile sound Player-2
YAMAHA CORPORATION
YMF795 CATALOG
CATALOG No.:LSI-4MF795A20
2005. 11
Outline
YMF795 is a sound source LSI to reproduce high quality melody and effect sound for in-car product. Yamaha's original
FM synthesizer embedded as a sound source can create various timbres, and also a sequencer embedded can
simultaneously generate up to four sounds with four different timbres without giving load to the controller.
Serial port is prepared as a controller interface, and no restriction of data capacity is present because melody data is
reproduced in real-time through FIFO.
A built-in amplifier to drive the dynamic speaker with 500mW power allows connecting a speaker directly.
This LSI is equipped with an analog-output pin also for the earphone jack.
In addition, supporting the standby mode can reduce the consumption current to 1 µA during the standby.
Features
YAMAHA's original FM sound source function
Built-in sequencer
Capable of producing up to 4 different sounds simultaneously (4 independent timbres available).
500mW output speaker amplifier
Sound quality correcting equalizer circuit
Serial interface
Arbitrary frequency of input clock from 2.685 MHz to 27.853 MHz in 55.93 kHz steps, as well as 2.688, 8.4, 12.6, 14.4,
19.2, 19.68, 19.8, and 27.82 MHz clock inputs
Analog output for earphone
Power-down mode (Typ. 1µA or less)
Supply voltage (Digital and Analog): 3.3V±10 %
24-pin SSOP. The plating of pins is lead-free. (YMF795-EZ)

YMF795
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Contents
■General Description of YMF795 .................................................................................................................. 3
■Block Description ......................................................................................................................................... 4
■Pin Configuration..........................................................................................................................................5
■Pin Description .............................................................................................................................................6
■Block Diagram.............................................................................................................................................. 7
■Register Map.................................................................................................................................................8
■Explanation of Registers............................................................................................................................... 9
□Musical score data register ....................................................................................................................9
□Timbre data register.............................................................................................................................14
□Other control data ................................................................................................................................ 17
■Power-down control division diagram........................................................................................................21
■Explanation of each bit ............................................................................................................................... 21
■On Reset .....................................................................................................................................................24
■Settings and Procedure required for a piece generation..............................................................................24
■Clock Frequency Setting............................................................................................................................. 24
■On Interrupt Sequence ................................................................................................................................ 25
■State Transition........................................................................................................................................... 26
■Operation in FIFO empty condition............................................................................................................28
■Reproduction method assuming occurrence of empty state........................................................................ 28
■Example of peripheral circuit......................................................................................................................29
(1) Circuit diagram and wiring diagram when two power supplies are used:............................................... 30
(2) Circuit diagram and wiring diagram when one power supply and one voltage regulator IC are used: ... 31
■Volume level Adjustment in monophonic sound and 4-sound generation ................................................. 33
■Sound Quality Correction Circuit ...............................................................................................................35
■Serial I/F Specifications..............................................................................................................................37
■Electrical Characteristics ............................................................................................................................38
■General description of FM sound generator ...............................................................................................43
■External dimensions....................................................................................................................................44

YMF795
-3-
■General Description of YMF795
YMF795 is controlled through the serial interface.
Internal configuration the LSI has is shown below.
Data inputted to the serial interface is converted into the parallel data and transferred to each function block according
to its index address.
The musical score data is stored in the 32-word FIFO first and then transferred to the sequencer which interprets data
to control sound generation of the FM synthesizer.
The timbre register is where up to 8 timbre data can be stored.
And, as the sequencer controlling register, registers for start/stop and tempo are provided.
In order to have sound generate, the following controls must be performed to this LSI.
1) Initial status setting (cancellation of power-down, clock selection, etc).
2) Timbre data setting.
3) Writing of the musical score data into FIFO before starting the sequence.
4) To write the next musical score data write before the FIFO becomes empty, and to receive the interrupt signal
from FIFO during reproduction.
(For the details, refer to “Settings and procedure required for a piece generation” (P.24).
Serial
interface
FIFO
32word
/IRQ Sequencer FM
Synthesizer
D/A +
Volume AMP
Timbre
register
Musical score
dat
a
Tempo
START/STOP
Timbre allocation
Timbre Data
Volume, power management, etc.
SDIN
SYNC
SCLK
SPOUT
HPOUT

YMF795
-4-
■Block Description
1) Serial interface block
The block receives serial data and then identifies its Index data to send control data to each function block.
2) FIFO block
FIFO temporarily stores musical score data. Musical score data up to 32 can be stored. The musical score data are
processed in the sequencer when they are generated as sounds and those processed are deleted one after another.
When the amount of remaining data amount in FIFO reaches the value or less of register setting (IRQ point), it
outputs an interrupt signal to the outside to request the subsequent musical score data.
3) Sequencer block
When the sequencer receives the START command, it sequentially starts reading the musical score data which have
been stored in FIFO. The processed musical score data are deleted.
4) Timbre register block
The block stores timbre data in this register which can set up to 8 timbres. Settings of this register must be completed
before sound generation. The register is initialized by hardware reset; however, in the following operations, contents
of a register are not cleared, and the value written last is held.
• Software reset (CLR bit of Index32h)
• During power-down mode, and after its cancellation.
5) FM synthesizer block
The block synthesizes and generates timbres according to settings. Four sounds can be generated at the same time.
6) D/A, volume, and amplifier blocks
The output from the synthesizer is D/A-converted, and volume processing is performed. After that, the data is
output from the speaker or the earphone output pin.

YMF795
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■Pin Configuration
< 24-pin SSOP TOP VIEW >
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK_I
<NC>
SDIN
SYNC
SCLK
<NC>
AVSS
VREF
HPOUT
EQ1
EQ2
E
Q
3
TESTO
/RST
/TESTI
/IRQ
DVDD
DVSS
SPOUT2
SPOUT1
SPVSS
SPVSS
AVDD
AVDD

YMF795
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■Pin Description
No. Pin I/O Function
1 CLK_I Ish Clock input pin
2 <NC> -
Be sure to use in no-connection.
The pin is nowhere connected in the chip.
3 SDIN I Serial I/F data input
4 SYNC I Serial I/F synchronous signal input
5 SCLK Ish Serial I/F bit clock input
6 <NC> -
Be sure to use in no-connection.
The pin is nowhere connected in the chip.
7 AVSS - Analog ground
8 VREF A
Analog reference voltage pin
Connect a 0.1 µF capacitor between this pin and analog ground pin.
9 HPOUT AO Analog output pin for earphone
10 EQ1 AO Equalizer pin 1
11 EQ2 AI Equalizer pin 2
12 EQ3 AO Equalizer pin 3
13
14
AVDD -
Analog power supply (+3.3V)
Connect 0.1 µF and 4.7 µF capacitors between this pin and analog ground pin
15
16 SPVSS - Analog ground exclusively used for speaker
17 SPOUT1 AO Speaker output pin 1
18 SPOUT2 AO Speaker output pin 2
19 DVSS - Digital ground
20 DVDD -
Digital power supply (+3.3 V)
Connect 0.1 µF and 4.7 µF capacitors between this pin and digital ground pin.
21 /IRQ O Interrupt signal output
22 /TESTI I LSI test input pin (Be sure to connect to DVDD.)
23 /RST I Hardware reset pin
24 TESTO O LSI TEST output pin (Be sure to use in no-connection)
Note : Ish = Schmitt input pin AI = Analog input pin A0 = Analog output pin

YMF795
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■Block Diagram
Concerning AIN signal inputted into equalizer circuit
It is possible to make the analog mixing between synthesizer output and other analog
source in the equalizer circuit and output the resulting sound through the speaker.
SYNC
SDIN
SCLK
CLK_I
/RST
/IRQ
EQ1
VREF
Serial
I/F
DVDD DVSS
FMVOL
32-step
Power down
Control
Register FM
Synthesizer
Simultaneous
sound generation
4-tone
DAC
AMP
AVDD AVSS
Timing Generator
HPOUT
HPVOL
32-step
FIFO
16b×32w
EQ2
EQ3
VREF
CR circuit for EQ
SPVSS
SPVOL
32-step
AIN *
Se
q
uencer
+ −
VREF
SPOUT1
SPOUT2

YMF795
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■Register Map
Index b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Description
BL1 BL0 NT3 NT2 NT1 NT0 CH1 CH0 VIB TI3 TI2 TI1 TI0 TK2 TK1 TK0 Note data$00h
0 0 1 1 0 0 CH1 CH0 VCHE TI3 TI2 TI1 TI0 VCH2 VCH1 VCH0 Rest data
ML2 ML1 ML0 VIB EGT SUS RR3 RR2 RR1 RR0 DR3 DR2 DR1 DR0 AR3 AR2$10 - 2Fh
AR1 AR0 SL3 SL2 SL1 SL0 TL5 TL4 TL3 TL2 TL1 TL0 WAV FL2 FL1 FL0
Timbre data
(for 1 Operator)
$30h 0 V32 V31 V30 0 V22 V21 V20 0 V12 V11 V10 0 V02 V01 V00 Timbre allocation data
$31h 0 0 0 0 0 0 0 0 T7 T6 T5 T4 T3 T2 T1 T0 Tempo data
$32h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR ST FM Control
$33h 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKSEL CLK_I select
$34h 0 0 0 0 0 0 0 0 0 0 IRQE IRQ Point IRQ Control
$35h 0 0 0 0 0 0 0 0 0 0 0 V4 V3 V2 V1 V0 Speaker Volume
$36h 0 0 0 0 0 0 0 0 0 0 0 V4 V3 V2 V1 V0 FM Volume
$37h 0 0 0 0 0 0 0 0 0 0 0 V4 V3 V2 V1 V0 HPOUT Volume
$38h 0 0 0 0 0 0 0 0 0 0 0 AP4 AP3 AP2 AP1 DP Power Management
$39h 0 0 0 0 0 0 0 CLKSET CLK_I Select
$40 - EFh Reserved (access prohibited) Reserved
$F0 - FFh For LSI TEST(access prohibited) LSI TEST
Note : Access to the spaces of “Reserved” and “For LSI TEST” in the above table is prohibited.
Be sure to write “0” to the empty bit, although writing “1” there will not affect the LSI operation.

YMF795
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■Explanation of Registers
The YMF795 has three types of control registers: musical score data, timbre data, and other control data.
□Musical score data register
$00h Musical score data
The musical score data are written into the 32-word FIFO. There are two types of musical score data: note
data and rest data.
Note data Default: 0000h
Index B15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
$00h BL1 BL0 NT3 NT2 NT1 NT0 CH1 CH0 VIB TI3 TI2 TI1 TI0 TK2 TK1 TK0
BL1 – BL0 : Octave block setting
Three octave blocks are available for sound range setting. The setting range is 1 to 3. Do not set “0.”
In addition, the sound generation range is affected by the coefficient called “Multiple (multiplying factor for sound
generation frequency).”
By combining the octave block and Multiple settings, sounds can be generated in the range as listed in the table blow.
Since the setting range of “Multiple” coefficient is 0 to 7, actually, sounds wider than those given in the table below can
be generated.
Multiple = 1 (x1) Multiple = 2 (x2) Multiple = 4 (x4)
BL[1:0] = 01b C#3 (139Hz)
D3 (147Hz)
D#3 (156Hz)
E3 (165Hz)
F3 (175Hz)
F#3 (185Hz)
G3 (196Hz)
G#3 (208Hz)
A3 (220Hz)
A#3 (233Hz)
B3 (247Hz)
C4 (262Hz)
C#4 (277Hz)
D4 (294Hz)
D#4 (311Hz)
E4 (330Hz)
F4 (349Hz)
F#4 (370Hz)
G4 (392Hz)
G#4 (415Hz)
A4 (440Hz)
A#4 (466Hz)
B4 (494Hz)
C5 (523Hz)
C#5 (554Hz)
D5 (587Hz)
D#5 (622Hz)
E5 (659Hz)
F5 (698Hz)
F#5 (740Hz)
G5 (784Hz)
G#5 (831Hz)
A5 (880Hz)
A#5 (932Hz)
B5 (988Hz)
C6 (1046Hz)
BL[1:0] = 10b C#4 (277Hz)
D4 (294Hz)
D#4 (311Hz)
E4 (330Hz)
F4 (349Hz)
F#4 (370Hz)
G4 (392Hz)
G#4 (415Hz)
A4 (440Hz)
A#4 (466Hz)
B4 (494Hz)
C5 (523Hz)
C#5 (554Hz)
D5 (587Hz)
D#5 (622Hz)
E5 (659Hz)
F5 (698Hz)
F#5 (740Hz)
G5 (784Hz)
G#5 (831Hz)
A5 (880Hz)
A#5 (932Hz)
B5 (988Hz)
C6 (1046Hz)
C#6 (1109Hz)
D6 (1175Hz)
D#6 (1245Hz)
E6 (1319Hz)
F6 (1397Hz)
F#6 (1480Hz)
G6 (1568Hz)
G#6 (1661Hz)
A6 (1760Hz)
A#6 (1865Hz)
B6 (1976Hz)
C7 (2093Hz)
BL[1:0] = 11b C#5 (554Hz)
D5 (587Hz)
D#5 (622Hz)
E5 (659Hz)
F5 (698Hz)
F#5 (740Hz)
G5 (784Hz)
G#5 (831Hz)
A5 (880Hz)
A#5 (932Hz)
B5 (988Hz)
C6 (1046Hz)
C#6 (1109Hz)
D6 (1175Hz)
D#6 (1245Hz)
E6 (1319Hz)
F6 (1397Hz)
F#6 (1480Hz)
G6 (1568Hz)
G#6 (1661Hz)
A6 (1760Hz)
A#6 (1865Hz)
B6 (1976Hz)
C7 (2093Hz)
C#7 (2217Hz)
D7 (2349Hz)
D#7 (2489Hz)
E7 (2637Hz)
F7 (2794Hz)
F#7 (2960Hz)
G7 (3136Hz)
G#7 (3322Hz)
A7 (3520Hz)
A#7 (3729Hz)
B7 (3951Hz)
C8 (4186Hz)

YMF795
-10-
NT3 - NT0 : Pitch setting
Four bits from NT3 to 0 are used to specify the pitch. The bit assignment is as follows.
NT[3:0] Pitch
0h Setting Prohibited
1h C#
2h D
3h D#
4h Setting Prohibited
5h E
6h F
7h F#
8h Setting Prohibited
9h G
Ah G#
Bh A
Ch Setting Prohibited
Dh A#
Eh B
Fh C
About “Setting Prohibited.”
Although LSI never hangs, unusual sound may be generated. Never set it.
CH1 - CH0 : Part setting
As the sound source section can simultaneously generate sounds in 4 parts, set the part of a note by using CH1 and 0
bits.
CH[1:0] Part setting
00b 0
01b 1
10b 2
11b 3
VIB : Vibrato setting
This bit is used to set ON/OFF of Vibrato function for each note: “0” for OFF and “1” for ON. The vibrato frequency
is 6.4 Hz and the modulation depth is ±13.47 cent.
Note that Vibrato function becomes OFF when VIB bit of timbre data ($10-2Fh) is “0.”

YMF795
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TI3 - TI0 : Interval setting
These bits are used to set the interval time before the processing of the next note and rest. The interval “48”
represents the time for the whole note.
TI[3:0] Interval
0h 0
1h 2
2h 3
3h 4
4h 6
5h 8
6h 9
7h 12
8h 18
9h 24
Ah 48
Bh 0
Ch 16
Dh 24
Eh 36
Fh 48
TK2 – TK0 : Note (sound length) designation
These 3 bits are used to designate the note (sound length). Depending on the value of interval setting (TI3 - 0), the
length varies as shown in the following table. The interval “48” represents the time for the whole note.
TI[3:0]=0toAh TI[3:0] =BtoFh
TK[2:0] 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
Sound
length 1 2 3 5 7 8 11 17 15 23 29 32 35 41 47 Tie, Slur

YMF795
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■Caution ■
When KEY is turned on again while release rate is not completely finished yet in the same channel, timbre may
change.
This happens in both sustained sound and decaying sound.
The reason why it happens is that both envelope and phase in the career side and modulator side of the FM sound
source deviate.
The hardware creating the phase and envelope of FM sound source starts its operation according to the following
two conditions.
- End of the release rate.
- Occurrence of Key ON.
Timbre data is created on the assumption that modulator, phase between careers, and envelope operate at the same
timing; therefore, timbre may vary when this condition is not met.
Description mentioned above is explained with the envelope waveform.
For example, assume that a timbre of which only release time differs between carrier and modulator is present. If
operation is in the state completely stopped, it shifts to the Attack rate in conjunction with KEY ON. If the
previous sound generation is being released and is not in a state completely stopped, the release settings is forcibly
hastened (8.94 ms) and a stopped state is shifted to the attack rate state. (Dotted line of A)
Although envelope indicated in a solid line changes to the attack rate state soon at the second KEY ON, shifting
to the attack rate state is not immediately performed because sound indicated in a dotted line is not completely
stopped. The release time is hastened to stop the state, and then the state stopped is shifted to the attack rate state.
The starting time deviation of both envelopes and phase caused by this deviation causes a change of timbre.
How to avoid this symptom:
Be sure to observe “Try to pronounce under the condition that the release is completely stopped.”
T
K
TI
A
T
K
Timbre varies.

YMF795
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Rest data Default: 0000h
Index b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
$00h 0 0 1 1 0 0 CH1 CH0 VCHE TI3 TI2 TI1 TI0 VCH2 VCH1VCH0
CH1 - CH0 : Part setting
Using CH1 or 0 bit, set the part of each rest.
CH[1:0] Part designation
00b 0
01b 1
10b 2
11b 3
TI3 - TI0 : Interval setting
These bits are used to set the interval time before the processing of the next note and rest.
The interval “48” represents the time for the whole note.
The following table is exactly the same as that for the note data.
TI [3:0] Interval
0h 3
1h 2
2h 3
3h 4
4h 6
5h 8
6h 9
7h 12
8h 18
9h 24
Ah 48
Bh 1
Ch 16
Dh 24
Eh 36
Fh 48
VCHE, VCH2 – VCH0 : Timbre change function
Although the maximum number of timbres that can be simultaneously used is four, the timbre can be changed during
sound reproduction by setting these bits. Set VCHE to “1” and set a timbre number by using VCH2 to VCH0.
Switching of timbre in rest data is made according to the designated time of the sequence data. After the next note to
generate, the timbre in a part specified by CH0 and CH1 will be changed.
Make the change of a timbre after sound generation of a part to change is completely stopped.
The state at which sound generation is completely stopped is not a state where TK (sound length) is ended but a state
where release time of envelope is completed.
Note that unusual sound may be instantaneously generated if switching the timbre while sound generation is not
completely stopped.
If the timbre allocation is changed by using this function, the $30h register itself will be rewritten.

YMF795
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□Timbre data register
$10 – 2Fh Timbre data
Eight timbre data can be registered into the register and four data out of them can be simultaneously reprodu
ced.
Timbre is made by setting both [parameters for the modulator] and [parameters for the carrier].
(For details of the modulator and the carrier, please refer to “General description of FM sound generator” (page 41)).
Index 10h, 11h …… 1st timbre_ timbre data for the modulator
Index 12h, 13h …… 1st timbre_ timbre data for the carrier
Index 14h, 15h …… 2nd timbre_ timbre data for the modulator
Index 16h, 17h …… 2nd timbre_ timbre data for the carrier
……………Omitted…………….
Index 2Ch, 2Dh …… 8th timbre_ timbre data for the modulator
Index 2Eh, 2Fh …… 8th timbre_ timbre data for the carrier
The following bit assignment is used for both modulator and carrier.
The setting must be completed before any sound is generated. Change of the timbre parameter during sound generation is
prohibited.
Timbre data Default: 0000h
Index B15 b14 b13 b12 B11 b10 B9 b8 b7 b6 b5 b4 b3 b2 b1 b0
EVEN ML2 ML1 ML0 VIB EGT SUS RR3 RR2 RR1 RR0 DR3 DR2 DR1 DR0 AR3 AR2
ODD AR1 AR0 SL3 SL2 SL1 SL0 TL5 TL4 TL3 TL2 TL1 TL0 WAV FL2 FL1 FL0
ML2 - ML0 : Multiple setting
“Multiple” is the multiplying factor for sound generating frequency. The output frequency is determined by the octave,
pitch, and multiple settings on the carrier side. Adjusting the Multiple on the Modulator side allows various timbre
creation.
ML [2:0] Multiplying factor
for frequency
0h X 1/2
1h X 1
2h X 2
3h X 3
4h X 4
5h X 5
6h X 6
7h X 7

YMF795
-15-
VIB : Vibrato
This bit is used to set ON/OFF of vibrato function. “0” for OFF, “1” for ON.
The vibrato frequency is 6.4 Hz and the modulation depth is ±13.47cent.
EGT : Envelope waveform type
This bit is used to select the type of the envelope waveform.
“0” for the decaying sound and “1” for the sustained sound.
Envelope waveforms shown below are for the decaying sound and sustained sound.
AR3 - AR0 : Attack Rate setting
“Attack Rate” is a time interval from the time sound starts generating (-48dB) to the time sound reaches at the
maximum volume (0dB). The table on the next page is shown as the time taken from -48dB to 0dB.
DR3 - DR0 : Decay Rate setting
“Decay Rate” is a time interval taken for decay from 0 dB to the time it reaches at the Sustain Level (SL). The table
on the next page is shown as the time taken from 0 dB to -48 dB.
RR3 - RR0 : Release Rate setting
Definition of the Release Rate differs between decaying sound and sustained sound.
• Decaying sound: Decaying time from the Sustain Level to the end of the sound generation. The sound decays taking
286 ms (time taken from 0 dB to -48 dB) after the end of the sound generation.
• Sustained sound: Decaying time from the end of the sound generation.
A
R
D
R
R
R
S
L
0dB
-
48dB
When SUS=ON
EGT=0 Decaying sound
Length of
Sound generated
A
R
D
R
R
R
S
L
0dB
-48dB
When SUS=ON
EGT=1 Sustained sound
Length of
Sound generated

YMF795
-16-
SL3 - SL0 : Sustain level setting
The Sustain Level, in the case of decaying sound, is the transition level from the Decay Rate to the Release Rate, and
in the case of sustained sound, is a level held.
SL SL3 SL2 SL1 SL0
Weighted bit (dB) -24 -12 -6 -3
AR[3:0]
DR[3:0]
RR[3:0]
Attack rate
-48 to 0dB (ms)
Decay Rate,
Release Rate
0 to -48dB (ms)
Fh 0 2.23
Eh 4.65 8.94
Dh 9.30 17.88
Ch 18.59 35.76
Bh 37.19 71.52
Ah 74.38 143.04
9h 148.76 286.07
8h 297.51 572.14
7h 595.03 1144.25
6h 1190.05 2288.56
5h 2380.10 4577.12
4h 4760.21 9154.25
3h 9520.42 18308.50
2h 19040.84 36617.00
1h ∞∞
0h ∞∞
TL5 - TL0 : Total level setting
This function is used to set the envelope level.
TL TL5 TL4 TL3 TL2 TL1 TL0
Weighted bit (dB) -24 -12 -6 -3 -1.5 -0.75
SUS : Sustain On/OFF setting
“0” : OFF
“1” : ON The Release Rate changes to “6” (2.29s) when the sound length comes to the end.
WAV : Waveform selection
The modulator and carrier can generate a sine wave; however, can generate a half-wave rectified waveform by setting
this bit. Setting this bit allows creation using wider timbres.
“0” : Sine wave
“1” : Half-wave rectified waveform of a sine wave.
FL2 - FL0 : Feed-back setting
This function is available only for the operator of Modulator. These bits specify the feedback modulation depth.
Be sure to set “0” to the operator of the carrier side. This is effective function for generating the strings timbres.
FL[2:0] 0 1 2 3 4 5 6 7
Modulation rate 0 π/16 π/ 8 π/ 4 π/ 2 π2π4π
WAV=0 WAV=1

YMF795
-17-
□Other control data
$30h Timbre allocation data
One piece can be generated at the same time up to four parts, and timbre can be assigned for each part. The data is
used by allocating four timbres out of eight timbres registered in the timbre data register to each part.
Default: 0000h
Index b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
$30h 0 V32 V31 V30 0 V22 V21 V20 0 V12 V11 V10 0 V02 V01 V00
“x” of Vx[2:0] indicates the part No.
Vx[2:0] and timbre data are as follows.
Vx[2:0] Timbre data to use
0h Timbre set in the Index of 10 to 13h is used.
1h Timbre set in the Index of 14 to 17h is used.
2h Timbre set in the Index of 18 to 1Bh is used.
3h Timbre set in the Index of 1C to 1Fh is used.
4h Timbre set in the Index of 20 to 23h is used.
5h Timbre set in the Index of 24 to 27h is used.
6h Timbre set in the Index of 28 to 2Bh is used.
7h Timbre set in the Index of 2C to 2Fh is used.
$31h Tempo data
This register sets “tempo” for reproduction of a piece. Setting data is equal to (8739/TEMPO)-1. TEMPO is the
number of crotchets that can be reproduced in one minute.
Default: 0000h
Index b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
$31h 0 0 0 0 0 0 0 0 T7 T6 T5 T4 T3 T2 T1 T0
$32h FM section control
Default: 0000h
Index b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
$32h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR ST
ST : This bit is used to control start/stop of a piece. “1” for start and “0” for stop.
FIFO becomes empty when ST is set to “0.”
CLR : This bit is used to initialize the whole LSI by the software. All the registers except “ Timbre data register” of
Index 10 to 2Fh are initialized. Bit CLR itself is not cleared even if setting to “1.” In normal operation, write “0” into
the bit CLR..

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$33h Clock selection
Default: 0000h
Index b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
$33h 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKSEL
This register is used to set the clock frequency inputted through CLK_I pin when making the clock setting in the
preset mode.
A clock with any frequency can be input during the reset period.
(For details of the clock setting, see “On clock frequency setting” (page 24)).
CKSEL [2:0] Clock frequency (MHz)
0h(*) 2.688
1h 19.200
2h 19.680
3h 19.800
4h 8.400
5h 14.400
6h 27.821
7h 12.600
(*)When clock is set in the programmable mode, set CLKSEL[2:0] to “0h”.
$34h Interrupt control
Default: 0000h
Index b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
$34h 0 0 0 0 0 0 0 0 0 0 IRQE IRQ point
The musical score data is taken into the FIFO which has a capacity for 32 data. As the sounds are reproduced, the data in
FIFO are processed and deleted. And when the amount of data remaining in FIFO becomes less than the setting value of
IRQ point, an interrupt signal is generated. At this point, set “0” to IRQE and then write the subsequent musical score
data into FIFO.
Be sure to write data in excess of the IRQ point. After writing the data, reset IRQE to “1” and wait another interrupt
signal.
IRQ point can be set in 32 ways from 0 (empty) to 31 (1 data vacancy).
IRQE is the interrupt enable bit. “1” indicates Enable.

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$35h Speaker volume control
$36h FM volume control
$37h Earphone output volume control
Default: 0000h
Index b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
$35-7h 0 0 0 0 0 0 0 0 0 0 0 V4 V3 V2 V1 V0
These bits are used to set the volume of each source. The volume setting consists of 31 steps and MUTE state, and can
be set in 1dB steps. As the MUTE is selected in the default state, cancel and use the MUTE state before sound
generation. And, be sure to power down the volume after muting it.
Relation between register setting value and volume.
V[4:0] Volume(dB) V[4:0] Volume(dB) V[4:0] Volume(dB) V[4:0] Volume(dB)
00h MUTE 08h -23 10h -15 18h -7
01h -30 09h -22 11h -14 19h -6
02h -29 0Ah -21 12h -13 1Ah -5
03h -28 0Bh -20 13h -12 1Bh -4
04h -27 0Ch -19 14h -11 1Ch -3
05h -26 0Dh -18 15h -10 1Dh -2
06h -25 0Eh -17 16h - 9 1Eh -1
07h -24 0Fh -16 17h - 8 1Fh 0
$38h Power Management control
Default: 001Eh
Index b15 b14 b13 b12 b11 B10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
$38h 0 0 0 0 0 0 0 0 0 0 0 AP4 AP3 AP2 AP1 DP
These bits are used to control the power-down. 1 digital line and 4 analog lines can be independently controlled. (For
details, refer to “■Power-down control division diagram”.)
Setting all bits to “1” will minimize the power of the entire LSI.
DP : Setting of “1” can power down the entire digital section.
AP1 : Setting of “1” can power down the VREF circuit in the analog section.
AP2 : Setting of “1” can power down the FM volume, speaker volume, equalizer circuit, and the non-inverted
amplifier side of speaker output section.
AP3 : Setting of “1” can power down the inverted amplifier side of the speaker output section.
AP4 : Setting of “1” can power down the DAC and earphone output volume.
After initialization, the analog section (AP1 to AP4) is in the power-down state.

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$39h Clock setting
Default: 0000h
Index b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
$39h 0 0 0 0 0 0 0 CLKSET
The register is used to set the clock frequency that is input through the CLK_I pin when the setting is made in the
programmable mode. Be sure to complete the setting before its sound generation.
A clock with any frequency can be input during the reset period.
For details of the clock setting, see “Clock Frequency Setting” (page 24).
CLKSET [8:0] Clock frequency(MHz)
000000000b (Preset mode)
000000001b Prohibition
: :
000101111b Prohibition
000110000b 2.684658000
000110001b 2.740588375
: :
111110001b 27.797396375
111110010b 27.853326750
111110011b Prohibition
: :
111111111b Prohibition
The values that can be set to CLKSET are “000000000b”, and “000110000b” to “111110010b.”
When other value is set, the operation is not guaranteed.
A value to set to CLKSET can be found by using the following formula.
CLKSET = Clock frequency [KHz] / 447.443 × 8
For example, when the clock frequency is 3 MHz:
CLKSET = 3000 / 447.443 × 8 is about 54 = 000110110b
And, actual clock frequency to be set is as follows.
Clock frequency [kHz] = 54 × 447.443 / 8 = 3020.24[kHz] = 3.02024[MHz]