Yamaha Lmy2-mlab User manual

SERVICE MANUAL

PA 011736

200406-

オープンプライス

■ CONTENTS（目次）

SPECIFICATION（総合仕様）........................................................... 3

PANEL LAYOUT（パネルレイアウト）.............................................. 5

DIMENSIONS（寸法図）................................................................... 5

BLOCK DIAGRAM（ブロックダイアグラム）.................................. 6

LEVEL DIAGRAM（レベルダイアグラム）....................................... 7

LSI PIN DESCRIPTION（LSI端子機能表）..................................... 8

IC BLOCK DIAGRAM（ICブロック図）........................................... 9

CIRCUIT BOARD（シート基板図）................................................. 10

INSPECTION（検査）................................................................ 13/17

OVERALL CIRCUIT DIAGRAM（総回路図）

PARTS LIST

LMY2-MLAB

MIC/LINE INPUT CARD

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LMY2-MLAB

2

IMPORTANT NOTICE

This manual has been provided for the use of authorized Yamaha Retailers and their service personnel. It has been assumed that basic

service procedures inherent to the industry, and more specifically Yamaha Products, are already known and understood by the users,

and have therefore not been restated.

WARNING: Failure to follow appropriate service and safety procedures when servicing this product may result in personal injury,

destruction of expensive components, and failure of the product to perform as specified. For these reasons, we

advise all Yamaha product owners that all service required should be performed by an authorized Yamaha Retailer or

the appointed service representative.

IMPORTANT: The presentation or sale of this manual to any individual or firm does not constitute authorization, certification or

recognition of any applicable technical capabilities, or establish a principle-agent relationship of any form.

The data provided is believed to be accurate and applicable to the unit(s) indicated on the cover. The research, engineering, and

service departments of Yamaha are continually striving to improve Yamaha products. Modifications are, therefore, inevitable and

changes in specification are subject to change without notice or obligation to retrofit. Should any discrepancy appear to exist, please

contact the distributor's Service Division.

WARNING: Static discharges can destroy expensive components. Discharge any static electricity your body may have

accumulated by grounding yourself to the ground bus in the unit (heavy gauge black wires connect to this bus).

IMPORTANT: Turn the unit OFF during disassembly and part replacement. Recheck all work before you apply power to the unit.

WARNING: CHEMICAL CONTENT NOTICE!

The solder used in the production of this product contains LEAD.In addition, other electrical/electronic and/or plastic (where applicable)

components may also contain traces of chemicals found by the California Health and Welfare Agency (and possibly other entities) to cause

cancer and/or birth defects or other reproductive harm.

DO NOT PLACE SOLDER, ELECTRICAL/ELECTRONIC OR PLASTIC COMPONENTS INYOUR MOUTH FOR ANY REASON WHAT-

SOEVER!

Avoid prolonged, unprotected contact between solder and your skin!When soldering, do not inhale solder fumes or expose eyes to solder/

flux vapor!

If you come in contact with solder or components located inside the enclosure of this product, wash your hands before handling food.

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3

LMY2-MLAB

■ SPECIFICATIONS（総合仕様）

ANALOG INPUT

Connector Item

Item

Specification

Item Specification

Specification

INPUT 1A,1B,2A,2B

XLR-3-31 Balanced (1: GND, 2: Hot, 3: Cold)

AD converter 24bit linear+4bit floating 128 Times Oversampling

LEDS

SIGNAL A green LED turns on at 34 +/-2dB below clipping.

B A orange LED turns on at B selecting.

FUNCTIONS

Input Gain -68 dB to +10 dB (1 dB step)

A/B select A or B

+48 V ON/OFF

These function can be controlled from CS1D and PM1D Manager

MISCELLANEOUS

Dimensions Height

Depth 322.1 mm

Width 120 mm

40 mm

Net Weight 350 g

Operation Temperatu re Range 10 to 35

Storage temperature -20 to 60

System Software requirement

PM1D software Ver 1.7 or later

ANALOG INPUT CHARACTERISTICS

Input Terminals Gain Actual load For use with Input level Connector

impedance nominal Nominal*6 Max. before clip

CH1A, CH1B -68 dB 3 K 50-600 Mics & -68 dBu (309uV) -54 dBu (775uV) XLR-3-31 type (Balanced)*2

CH2A, CH2B +10 dB 600 Lines +10 dBu (2.45 V) +24 dBu (12.3 V)

*1. 0 dBu is referenced to 0.775 Vrms.

*2. CH1A, CH1B, CH2A, CH2B XLR-3-31 type connectors are balanced.(1=GND, 2=HOT, 3=COLD )

*3. AD converters are 24 bit linear +4 bit floating,128 times oversampling.

*4. +48 VDC (phantom power) is individually supplied to each input connectors.

*5. Gain in the table is the display which appears in CS1D.

*6. In put level which produces the nominal output level (+10 dBu).

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LMY2-MLAB

4

ELECTRICAL CHARACTERISTICS

Output impedance of signal generator:150 ohms, fs=44.1 k or 48 kHz

Gain in the table below is the display which appears in CS1D.

FREQUENCY RESPONSE @20 Hz-20 kHz,refer to the nominal output level @1 kHz

Input Output Conditions

MIN TYP MAX UNIT

CH1A, CH1B LMY4-DA Gain:-68 dB@+10 dBu - 3 1 dB

dB

CH2A, CH2B Gain:+10 dB@+10 dBu - 3 1 dB

dB

kHz

dB

GAIN ERROR @1 kHz

CH1A, CH1B LMY4-DA GAIN -68 dB@+10 dBu -1 1

CH2A, CH2B GAIN +10 dB@+10 dBu -1 1

Total Harmonic Distortion

CH1A, CH1B LMY4-DA +10 dBu@20 Hz-20kHz GAIN: -68 dB 0.3 %

CH2A, CH2B Full scale output @1 kHz GAIN: -68 dB 0.05 %

+10 dBu@20 Hz-20 kHz GAIN: +10 dB 0.02 %

Full scale output @1 kHz GAIN: +10 dB 0.007 %

Dynamic Range

CH1A, CH1B LMY4-DA GAIN +10 dB * 120

CH2A, CH2B *Dynamic range are measured with a 6 dB/octave filter @12.7 kHz;

equivalent to a 20 kHz filter with infinite dB/octave attenuation.

Hum & Noise @20 Hz-20 kHz

CH1A, CH1B LMY4-DA Equivalent Input Noise -128

CH2A, CH2B Rs=150 ,GAIN: -68 dB

CH1A, CH1B LMY4-DA Rs=150 ,GAIN: -26 dB -80

CH2A, CH2B *Hum & Noise range are measured with a 6 dB/octave filter @12.7 kHz;

equivalent to a 20 kHz filter with infinite dB/octave attenuation.

Crosstalk @1kHz

From/To To/From Conditions

CH N CH (N-1) or (N+1) Adjacent inputs -90

CH N A CH N B Adjacent inputs -90

Parameter Conditions

Sampling frequency range 39.69 50.88

Signal delay Analog input to digital output@fs=48 kHz 1.5 ms

Power requirements DC digital 5 V 270 mA

DC analog 5 V 200 mA

DC analog +15 V 90 mA

DC analog -15 V 90 mA

DC +48 V 30 mA

Phantom power Output Voltage non-load 46 48 50 V

Output Current 7.5 mA

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5

LMY2-MLAB

■ PANEL LAYOUT（パネルレイアウト）

■ DIMENSIONS（寸法図）

322.1

301.8 (1.3)

1

18

100

123

120

40

733

Unit (単位): mm

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LMY2-MLAB

6

■ BLOCK DIAGRAM（ブロックダイアグラム）

14 dB

HA1

HA2

Amp

HA3 Amp

30 dB

24 dB

18 dB

12 dB

6 dB

0 dB

48V

A/D ADFC

IC108

28P IC904

44P

A/D

Amp

D7-0/b

I1/a

SYNC/b

256FS/a

A10-8/b

Reg.

/RES

SIGNAL

[CH1A]

[CH1B]

[CH2A]

[CH2B]

B

3

8

GND

0 dB

JK100

LD100

LD200

LD203

LD103

RY200

RY201 IC200, 201

IC206, 207

IC209

IC202

IC109

IC102

IC203

IC204

RY100

RY101

RY102

RY202

IC100, 101

IC106, 107

IC103

IC105

IC908 CN900

IC907

IC902, 903, 905, 906

IC908

IC104

12

31

3

21

6

11

12

212125

15 31

29

24

13

16

18

7

15

19

7

4

12

122

3

3310

674

25

15

10

4

1

7

212

1

3

6

11

12

21

3

46

3

4

12

3

12

3

12

3

JK101

JK200

JK201

18 dB

PAD 38 dB

14 dB

HA1

HA2

Amp

HA3

30 dB

24 dB

18 dB

12 dB

6 dB

0 dB

48V

B

0 dB

18 dB

PAD 38 dB Amp

Amp

SIGNAL

28CA1-8829942-1

IC208

28P

IC205

Ratedinput[dB]

定格入力 GAIN GAIN GAIN GAIN HA GAIN

GAIN

SWSEL*A SWSEL*B GAIN*_X GAIN*_Y GAIN*_Z

GC*

"ON" CHANNEL

HA1 HA2 PAD HA3 DSP

-68

-62

-56

-50

-44

-38

-32

-26

-20

-14

-8

-2

4

10

38

0

HI

LOW

0

14

LOW

HI

0

-18

HI

LOW

HI

LOW

HI

LOW

HI

LOW

HI

LOW

30

24

18

12

6

0

18

12

6

0

12

6

0

LOW

HI

LOW

HI

LOW

HI

LOW

HI

LOW

HI

LOW

HI

LOW

1X,0Y,1Z

0X,1Y,1Z

0X,0Y,1Z

1X,0Y,0Z

0X,1Y,0Z

0X,0Y,0Z

0X,0Y,1Z

1X,0Y,0Z

0X,1Y,0Z

0X,0Y,0Z

1X,0Y,0Z

0X,1Y,0Z

0X,0Y,0Z

6

0

74

68

62

56

50

44

38

32

26

20

14

8

2

-4

GAINSettingtable(GAIN設定表)

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LMY2-MLAB

■ LEVEL DIAGRAM（レベルダイアグラム）

[0dBu=0.775Vrms]

GAIN MAX

MAX INPUT [-54dB]

GAIN MAX

NOMINAL INPUT [-68dB]

MAX INPUT [24dB]

NOMINAL INPUT [10dB]

GAIN MIN

+24

+20

+10

0

-10

-20

-30

-40

-50

-60

-70

-80

ANALOG

HA2

HA1 HA3

dBu

DIGITALANALOG

0

-10

-20

-30

-40

-50

-60

-70

-80

DIGITAL

-90

-100

-110

dBFS

[0dBFS:Full scale]

28CA1-8829942-2

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LMY2-MLAB

8

■ LSI PIN DESCRIPTION（LSI端子機能表）

YAC509 (XM167A00) ADFC

ML2: IC904

No. NAME I/O FUNCTION

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

SI0 (L)

SI1 (L)

SI0 (R)

SI1 (R)

WCKI

BCKI

IMOD0 (*)

IMOD1 (*)

ITM0 (*)

ITM1 (*)

GSEL0 (*)

GSEL1 (*)

DFC (*)

GCC (*)

HTC (*)

CFT0 (*)

CFT1 (*)

GND

VDD

Test1 (*)

Test2 (*)

Test3

I

I/O

I

O

Input to Lch LO gain side (IMOD0=1)

Input to Lch (IMOD0=0)

Input to Lch HI gain side (IMOD0=1)

Input to Rch LO gain side (IMOD0=1)

Input to Rch (IMOD0=0)

Input to Rch HI gain side (IMOD0=1)

Word clock input/output of serial input

Bit clock input/output of serial input

Setting of serial input modes. "1" = parallel,

"0" = serial

Setting of serial input modes. "1" =

asynchronous, "0" = synchronous

Setting of input data timing

( ")

Setting of a floating gain

( ")

Digital filter ON/OFF ("1"=ON, "0"=OFF)

Automatic adjustment of floating gain

ON/OFF ("1"=ON, "0"=OFF)

Quasi instantaneous cross fade bold time

ON/OFF ("1"=ON, "0"=OFF)

Setting of cross fade time

( ")

GND

VDD(+5V)

Normally non-connected

"

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

XO

XI

CK256A

MCK

BCKO

WCKO

SYNC

SOR

SOL

CKSEL (*)

RESET

MUTE (*)

OMD (*)

NSC (*)

Test4

Test5

VDD

GND

DLSP0 (*)

FLSW (*)

Test6 (*)

Test7 (*)

O

I

O

I/O

O

I

O

I

Connect X’tal OUT crystal oscillator or input

256fs clock to XI.

Connect X’tal IN crystal oscillator or input

256fs clock to XI.

Output clock which is inputted to 256fs OUT

XI.

Output 128fs clock.

Output 64fs bit clock which divides MCK

(It rises at the head of SYNC).

Output 1fs word clock which divides MCK

and of which the duty ratio is 50%.

Input/output of 1fs synchronous clock (The

fall of SYNC makes the 6th rise of 256fs

the head of WC.)

Output in order of Rch data and Lch data.

Output in order of Lch data and Rch data.

Switching of input or output of SYNC. "1" =

output, "0" = input.

Internal reset at "0".

Output "0" for output mute all at "0".

SOL, SOR output (switching of "0"MBS

First/"1" LSB First).

Noise shooping ON/OFF. "1"=OFF, "0"=ON.

Normally non-connected.

"

VDD(+5V)

GND

Floating delay switching.

("1"=16 sample delay, "0"=0 sample delay)

Floating inhibiting SW.

"1"= floating, "0"= floating is inhibited.

ADC of output wave at HI level side.

Normally non-connected.

"

ITM1

0

1

ITM0

0

1

0

1

Input timing (format)

Move forward 20 bits closer

16 bits B.B format

18 bits B.B format

20 bits B.B format

GSEL1

0

1

GSEL0

0

1

0

1

Floating gain

12 dB (2 bits)

18 dB (3 bits)

24 dB (4 bits)

30 dB (5 bits)

CFT1

0

1

CFT0

0

1

0

1

Cross fade time

0 ms

53 ms

106 ms

212 ms

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9

LMY2-MLAB

AK5392-VS-E2 (XV065A00) A/D CONVERTER

ML2: IC108,208

No. NAME I/O FUNCTION

1

2

3

4

5

6

7

8

9

10

11

12

13

14

VREFL

GNDL

VCOML

AINL+

AINL-

ZCAL

VD

DGND

CAL

RST

SMODE2

SMODE1

LSCK

SCLK

O

I

O

I

I/O

L ch standard voltage output (+3.75V)

L ch standard grand (0 V)

L ch common voltage (+2.5 V)

L ch analog +input

L ch analog -input

Zero calibration

"L"=VCOML, VCOMR

"H": Analog input (AINLI,AINRI)

Power supply for digital

Ground for digital

Calibration status

Reset

Serial interface mode select

Clock for L/R ch select

Serial data clock

15

16

17

18

19

20

21

22

23

24

25

26

27

28

SDATA

FSYNC

MCLK

CMODE

HPFE

TEST

B GND

A GND

VA

AINR-

AINR+

VCOMR

GNDR

VREFR

O

I/O

I

O

Serial data output

Frame synchronization clock

Master clock input

Master clock select

HPF enable pin

Test pin

Ground (0 V)

Ground for analog (0 V)

Power source for analog (5V)

Rch analog -input

Rch analog +input

R ch common voltage (2.5 V)

R ch standard glound (0 V)

R ch standard voltage output (3.75 V)

■ IC BLOCK DIAGRAM（ICブロック図）

SN74LV273APWR (X5074A00)

Octal 3-State D-Type Flip Flop

ML2: IC902, 903, 905

TC74VHC245FT (XU797A00)

Octal 3-State Bus Buffer

ML2: IC906, 908, 910

NJM2068MD-T2 (X3505A00)

Dual Operatinal Amplifier

ML2: IC100, 109, 200, 209

HIC-HA: IC101, 102

TC74VHC244FT (XW234A00)

Octal 3-State Bus Buffer

ML2: IC909

SN74LV138ANSR (IS013810)

DECODER

ML2: IC907

SN74LV08APWR (X4463A00)

Qual 2 Input AND

ML2: IC901

1

2

3

4-V

8

7

6

5

Output A +V

Non-Inverting

Input A

-DC Voltage Supply

+DC Voltage

Supply

Output B

Inverting

Input B

Non-Inverting

Input B

Inverting

Input A

+-

ENABLEINPUTS

G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

H

L

H

X

L

H

L

H

X

L

H

X

L

X

L

H

X

H

X

L

X

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

SELECTINPUTS

OUTPUTS

GND

Vcc

8Q

8D

7D

7Q

6Q

6D

5D

5Q

CLKGND

4Q

4D

3D

3Q

2Q

2D

1D

1Q

CLR

1D1R

2

3

4

5

6

7

8

9

10

A1

A2

A3

A4

A5

A6

A7

A8

GND 11

12

13

14

15

16

17

18

19

20 V

CC

OE

B1

B2

B3

B4

B5

B6

B7

B8

1

2

3

4

5

6

7

8

9

10 11

12

13

14

15

16

17

18

19

20

QQ

DD

CK CK

CL CL

QQ

DDCK CK

CL CL

QQ

DD

CK CK

CL CL

QQ

DD

CK CK

CL CL

1

2

3

1A

1Y

42A

52B

62Y

7 VSS

1B

14

13

12

Vcc

4A

11 4Y

10 3B

93A

83Y

4B

1

2

3

4

5

6

7

A

B

Select

Enable

Output

B

CC

G2A G2A

G2B G2B

G1 G1

Y7 Y7

16

15

14

13

12

11

10

Vcc

Y0Y0

Y1Y1

Y2Y2

Y3 Output

Y3

Y4Y4

Y5Y5

8

GND 9Y6

A

Y6

1G

1A1

2Y4

1A2

2Y3

1A3

2Y2

1A4

2Y1

1 20

2 19

3 18

4 17

5 16

6 15

7 14

8 13

9 12

10 11

VDD (Vcc)

2G

1Y1

2A4

1Y2

2A3

1Y3

2A2

1Y4

2A1(GND) Vss

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TEL 13942296513 QQ 376315150 892498299

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LMY2-MLAB

10

■ CIRCUIT BOARDS（シート基板図）

TC74HC4053AF(EL) (XY879A00)

MULTIPLEXER ML2: IC105, 205

OPA2134UA/2K5 (X2420A00)

Dual Operatinal Amplifier

ML2: IC101, 103, 106, 107, 201, 203, 206, 207

SSM2402S (XW399A00)

Analog Switch

ML2: IC104, 204

1

2

3

4

5

6

7

8

13

14

15

16

9

10

11

12

Vcc

2-COM

1-COM

1Y1

1Y0

A

B

CGND

GND

INH

3Y0

3-COM

3Y1

2Y0

2Y1

1

2

3

4

8

7

6

5

Out A

A

B

V-

V+

Out B

-In B

+In B

-In A

+In A

+-

CONTROL INPUTS

INHIMIT

C*

X: Don’t care. *: Except HC4052A GAIN_X=A GAIN_X=B GAIN_X=C

BA

HC4051A HC4052A HC4053A

0X,0Y,0Z

1X,0Y,0Z

0X,1Y,0Z

1X,1Y,0Z

0X,0Y,1Z

1X,0Y,1Z

0X,1Y,1Z

1X,1Y,1Z

NONE

0

1

2

3

4

5

6

7

NONE

L

H

L

H

L

H

L

H

X

L

H

X

L

H

L

H

L

H

X

0X, 0Y

1X, 1Y

2X, 2Y

3X, 3Y

- -

NONE

"ON" CHANNEL

1

2

3

4

5

6

7

GROUND

16

15

14

13

12

11

10

V+

89

SW1CON

NC3

SW1IN

NC5

NC8

V-

SW2CON

NC14

SW2IN

NC12

SW2OUT

NC10

NC9

SW1OUT

S1 S2

to ML4 Circuit board

Note: See parts list for details of circuit board component parts.

注：シートの部品詳細はパーツリストをご参照ください。

2NAP-WC06320

●

HIC-HA Circuit Board（HIC-HAシート）

Components side (部品側)

Pattern side (パターン側)

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11

LMY2-MLAB

A

A’

A

A’ 2NAP-WC26140 1

● ML2 Circuit Board

（ML2シート）

Components side (部品側)

CH2B

CH2A

CH1B

CH1A

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LMY2-MLAB

12

B

B’

B

B’

● ML2 Circuit Board

（ML2シート）

Pattern side (パターン側)

2NAP-WC26140 1

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13

LMY2-MLAB

■ INSPECTION

1. Measuring Condition

1-1. Condition

Set LMY2-MLAB to AI8 and make an inspection by reference to the following block diagram.

Unless otherwise specified, the following conditions will apply.

・Set GAIN at 0 dB.

・Set GAIN for LMY4-DA at +24 dB.

・0 dBu=0.775 Vrms

・The output impedance of the oscillator is 150 Ω.

・Inputimpedencefortheoscilloscope,levelmeter,etc.shouldbe100kΩormore.

・Correct the noise measurement through an LPF with 12.7 kHz, -6 dB/OCT. (Use the average value, not the effective value.)

・Set WORD CLOCK for

AI8 at INT 48 k. However, as it is sourced through BNC from Function Generator for inspection of Fs

operation range, change over DipSW on UNC beforehand. (See Procedure 3.)

・

Since WORD CLOCK for AO8 is provided through INPUT A port, set DipSW on UNC beforehand. (See Procedure 3.)

・Set the load for the analog output of AO8 at 600 ohm.

Make GAIN settings using DipSW on UNC circuit board. (See Procedure 3.)

1-2. Test Program

The test program starts running when DipSW on each UNC circuit board for

AI8 and AO8 is set in debug mode and power is

activated. For setting, see Procedure 3.

For both AI8 and AO8, use the firmware "AI8/AO8 firmware" of PMID SYSTEM SOFTWARE whose version corresponds to the following.

LMY2-MLAB

SIN oscillator

AI8

BLOCK DIAGRAM

AO8

INPUT AOUTPUT A

68 pin cable

Clock source selection

is subject to inspection.

Function Generator

LMY4-DA

Distortion

Indicator

Int48 BNC

HEAD

PHONE

Amplifier

Version 1.70.0

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LMY2-MLAB

14

2-2. Gain/FrequencyCharacteristics/DistortionRatio(BothCH1AandCH2A)

* Inspect CH1B and CH2B only in case GAIN = 0 dB and input level = +23 dBu.

In this case, check that two LED indicators light up correctly.

(*1): It is based on the time of input 1 kHz.

(*2): It is based on the time of input +23 dBu.

Activatepowerindebugmode.Activatepowerindebugmode.

Displaythecardtypeeverysecond.

(Noneedtocheck)

GAINleadcheckeverysecond

(Noneedtocheck)

Displaythecardtypeeverysecond.

(Int48kHz)

78dB

66dB

54dB

48dB

36dB

18dB

12dB



0dB



+23±1.0dBu



−

-30±0.4dB（*2）

-55dBu

-43dBu

-31dBu

-25dBu

-13dBu

+5dBu

+11dBu

+23dBu

+10dBu

-7dBu

-3.0〜+1.0dB（*1）

−

-3.0〜+1.0dB（*1）

−

-2.0〜+1.0dB（*1）

−

-30±0.4dB（*2）



-2.0〜+1.0dBu（*1）



−

-30±0.4dB（*2）

1kHz 20Hz 20kHz lessthan0.05%

−

lessthan0.03%

−

lessthan0.007%

lessthan0.02%

lessthan0.05%



Tolerancelevel(THD)



1kHz

Tolerancelevel(outputlevel)

Inputlevel

AI8

GAINsetting

(SLOT1=LMY2-MLAB)

(InputA)

WordClocksourcetype

AO8AI8

2. INSPECTION

2-1. Option card ID

Conduct an ID check when power is activated after the card is inserted. 7-segment LED in front of AI8 displays the left digit = (slot

number) and right digit = (card type). This will be displayed for 8 slots in sequence, so visually check that it is recognized as LMY2-

MLAB. Also WordClock source currently locked will be finally displayed, so check that it is in the state of Int 48 kHz. Likewise,

check that 7-segment LED in front of AO8 is in the final state of WordClock source = Input A.

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15

LMY2-MLAB



2-3. Difference in Each CH Level (Both CH1A and CH2A)

Specify the range of the gain difference at 1 kHz measured in the above 2-2 as follows.



2-4. Residure Noise (LPF: 12.7 kHz) (Both CH1A and CH2A)



2-5. EIN (LPF: 12.7 kHz) (Both CH1A and CH2A)







However, outside the above tolerance level the measuring value - (gain at 1 kHz) -128.



2-6. Stroke Between CH1A and CH2A (1 kHz)

Check by inputting a signal to CH1A under the following condition. (Check for CH2A in the same manner.)



2-7. SIGNAL LED Lighting Level CH2A (1 kHz)

Check that SIGNAL LED comes on and goes out at the following input level.



2-8. Phantom Voltage (All of CH1A, CH1A and CH2B)

Set DipSW to PHANTOM ON on the circuit board and activate PHANTOM MASTER.

Check that when a resistor of 10 k ohm is connected between 2-pin and 1-pin of XLR with 2-pin and 3-pin short-circuit, the voltage

between 2-pin and 1-pin is 34 to 38 Vand that an electric discharge occurs immediately when PHANTOM MASTER is off.

2-9. Fs Operating Range (Both CH1A and CH2A)

WordClock being provided by BNC of AI8 (48 kHz +6.5%, 44.1 kHz -10%)

Set UNI circuit board so that WordClock can be switched over to BNC.

Proceed to inspection after checking that the 7-segment LED displays the following.



qFs=51.2 kHz（48 kHz +6.5%）

・Set Function Generator for 51.12 kHz.

・Check that the output level listed below can be achieved.

wFs=39kHz（44.1kHz-10%）

 ・SetFunctionGeneratorfor39.69kHz.

 Makethesameinspectionasinqand check that the same output level can be achieved.

DisplayofWordClocktype

（BNC）

Tolerance leveo

less than -67 dBu

Condition

Input 150 Ωshorted

for CH2A

CH1A input level

+23 dBu

AI8 GAIN setting

0 dB

Specified range

Within 1 dB

Tolerance level

less than -79 dBu

less than -95 dBu

Condition

Input 150Ωshorted

AI8 GAIN setting

36 dB

0 dB

Tolerancelevel

Comeson

Goesout

Inputlevel

-8dBu

-13dBu

Tolerance level

less than -50 dBu

Condition

Input 150Ωshorted

AI8 GAIN setting

78 dB

Tolerance level

+23±1.0 dBu

Input level

+23 dBu

Input frequency

1 kHz

AI8 GAIN setting

0 dB

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LMY2-MLAB

16

2-10.Sound Production Inspection (Both CH1A and CH1A and CH2A)

Input frequency of 1 kHz.

Set DipSW of UNC so that GAIN=Sweep.

Check that the output level varies.

2-11.CMG Adjustment (Both CH1A and CH2A)

Condition

Connect a resistor as follows.



qAdjusting VR100 and VR200

Set GAIN for 48 dB, apply a signal of +8 dBu/kHz to AMY2-MLAB and adjust the pre-set volume (VR100 for CH1A and

VR200 for CH2A) so that the output level can be as low as possible. Check that the adjusted output level is -46 dBu or less.

wAdjusting VR101 and VR201

Set GAIN for 18 dB, apply a signal of +8 dBu/kHz to AMY2-MLAB and adjust the pre-set volume (VR101 for CH1A and

VR201 for CH2A) so that the output level can be as low as pssible. Check that the adjusted output level is -60 dBu or less.



 TakecareofVR***becauseitisamulti-rotarytype(25+/-5rotations)withoutastopper.



3. Setting DipSW for AI8 and AO8 (UNC)

The construction of UNC circuit board is the same for both AI8 and AO8, htough each DipSW has a different meaning.

Though the following shows the setting, DipSW is not used in any case. (Null)



R124ΩNote1

LMY2-MLAB（CH1AorCH2A）

C

H

GNote1）Limittherelativeerroroftwo24ohmresistorstoamaximum50mohm.

ClockisprovidedfromINPUTA

GAIN=+24dBset

R124ΩNote1

1



Inorderof

2,3and4



5

6

7

Operatingmode

1:Operation 0:Debug

1:ALLA

1:ALLOFF

1:ALLMIN(0dB)

0:ALLB

0:ALLON

0:2,3,4GAINmode(*1)



WCSel

mode(*1)

GAIN

mode(*1)

A/BSel

Phantom

GAIN

1,1,1

Int48kHz

1,1,1

Sweep(*2)

43218

CPU

1:ON

UNCcircuitboard

0:OFF 765

1,0,1

Int39kHz

1,0,1

66dB

0,1,1

Int44.1kHz

0,1,1

78dB

0,0,1

(OUTPUTA)

0,0,1

54dB

1,1,0

(OUTPUTB)

1,1,0

48dB

0,1,0

(OUTPUTC)

0,1,0

36dB

0,0,0

nouse

0,0,0

12dB

1,0,0

BNC

1,0,0

18dB

WCWCWC

 (*1):If DipSW7 is off, it provides "WCSel = Int 48 kHz fixed and DipSW2, 3, & 4 in GAIN mode."

 (*2):A variance of 6 dB occurs every two seconds. (0dB→78dB→0dB→78dB...)

※AI8(UNC)DipSWsetting [1:ON(=GND)0:OFF(=+5V)]

4321

ON

8765

※AO8(UNC)DipSWsetting [1:ON(=GND)0:OFF(=+5V)]

 Forfurtherdetails,aboutAO8DipSW,refertoLMY4-DA.

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17

LMY2-MLAB

■ 検査

1. 測定条件

1-1. 条件

 AI8にLMY2-MLABをセットし、下図の接続構成により検査を行います。

 特に指定のないときは以下の条件とします。

 ・GAIN設定を0dBとします。

 ・LMY4-DAのGAIN設定は+24dBとします。

 ・0dBu=0.775Vrms

 ・発振器の出力インピーダンスは150Ωとします。

 ・オシロスコープ、レベル計等の入力インピーダンスは100kΩ以上とします。

 ・ノイズ測定は12.7kHz、-6dB/OCTのLPFで補正します。（実行値ではなく平均値での測定とします。）

・

AI8のWORDCLOCKはINT48kにしますが、Fs動作範囲検査の際は、FunctionGeneratorよりBNC経由で供給するので、



 あらかじめUNC上のDipSWを切替えます。（3項参照）

・

AO8のWORDCLOCKはINPUTAポート経由で供給するので、あらかじめUNC上のDipSWを設定しておきます。（3項参照）



 ・AO8アナログ出力の負荷は600Ωとします。

 GAIN設定は、UNCシート内のDipSWで行います。（3項参照）



1-2. テストプログラム



AI8・AO8の各UNCシート上にあるDipSWをデバッグモードに設定し電源ONすることでテストプログラムが起動します。



 設定方法については、3項を参照してください。

 AI8・AO8共にファームウエアーは、下記に記載されたバージョンと一致するPMIDSYSTEMSOFTWAREの"AI8/AO8

 ファームウエアー"を使用してください。

LMY2-MLAB AI8

接続図

AO8

INPUTAOUTPUTA

FunctionGenerator

LMY4-DA

68ピンケーブル

Int48 BNC

HEAD

PHONE

SIN波発振器

アンプ

Clockソースは

検査により選択

歪計

バージョン 1.70.0

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LMY2-MLAB

18

2-2. 利得・周波数特性・歪率（CH1A、CH2A共）

 ※CH1B、CH2Bに関してはGAIN=0dB入力レベル＝+23dBuのみ検査します。

 この際、BのLED2個が正常点灯することを確認します。



 (*1):1kHz入力時を基準とします。

 (*2):+23dBu入力時を基準とします。



デバックモードで電源ONデバックモードで電源ON

1秒ごとにカード種別表示

（確認の必要なし）

1秒ごとにGAINリードチェック

（確認の必要なし）

1秒ごとにカード種別表示

（Int48kHz）

78dB

66dB

54dB

48dB

36dB

18dB

12dB



0dB



+23±1.0dBu



−

-30±0.4dB（*2）

-55dBu

-43dBu

-31dBu

-25dBu

-13dBu

+5dBu

+11dBu

+23dBu

+10dBu

-7dBu

-3.0〜+1.0dB（*1）

−

-3.0〜+1.0dB（*1）

−

-2.0〜+1.0dB（*1）

−

-30±0.4dB（*2）



-2.0〜+1.0dBu（*1）



−

-30±0.4dB（*2）

1kHz 20Hz 20kHz 0.05%以下

−

0.03%以下

−

0.007%以下

0.02%以下

0.05%以下



許容範囲（THD）

1kHz

許容範囲（出力レベル）

入力レベル

AI8

GAIN設定

（SLOT1=LMY2-MLAB）

（InputA）

WordClockソース種別

AO8側AI8側

2. 検査

2-1. OPTIONCARDID



カード挿入後、電源ON時にIDチェックを行います。AI8正面の7セグメントLED上に左の桁＝（スロット番号）右の桁＝（カード種類）



 と表示されます。これが8スロット分順次表示されるのでLMY2-MLABと認識しているか目視確認してください。

 また最後に現在ロックしているWordClockソースが表示されるので、Int48kHzの状態になっているか確認します。

 同様に、AO8正面の7セグメントLEDが最終的にWordClockソース＝InputAとなっているか確認します。

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19

LMY2-MLAB



2-3. 各CH間のレベル差（CH1A、CH2A共）

 2-2で測定した1kHzでの利得差の範囲を以下のように規定します。



2-4. 残留ノイズ（LPF:12.7kHz）（CH1A、CH2A共）



2-5. EIN（LPF:12.7kHz）（CH1A、CH2A共）







 ただし、上記許容範囲に入らない場合は、測定値−（1kHzにおける利得）≦-128



2-6. CH1A、CH2A間のストローク（1kHz）

 以下の条件でCH1Aに信号入力し検査します。（CH2Aも同様に検査します。）



2-7. SignalLED点灯レベル（CH1A、CH2A共）

 以下の入力レベルでSIGNALLEDの点灯・消灯を確認すること。



2-8. ファントム電圧（CH1A、CH1B、CH2A、CH2B共）

 UNCシート内DipSWをファントムONとし、ファントムマスターをONとします。

 XLRの2ピンと3ピンをショートし、2-1ピン間に10kΩ負荷を接続したとき両端の電圧が34〜38Vであること、またファン

 トムマスターOFFしたとき、速やかに放電することを確認します。



2-9. Fs動作範囲（CH1A、CH2A共）

 AI8のBNCよりWordClock供給（48kHz+6.5%、44.1kHz-10%）

 AI8のWordClockソースをBNCに切替えるようUNCシートを設定します。

 AI8の7セグメントLEDが次のように表示されることを確認後、検査を行います。



qFs=51.2kHz（48kHz+6.5%）

 ・FunctionGeneratorの設定を51.12kHzにします。

 ・下表の出力レベルが得られることを確認します。



wFs=39kHz（44.1kHz-10%）

 ・FunctionGeneratorの設定を39.69kHzにします。

 qの検査と同様に行い、同様の出力レベルが得られることを確認します。

WordClockソース種別表示

（BNC）

許容範囲

-67dBu以下

条件

CH2Aを

入力150Ωショート

CH1A入力レベル

+23dBu

AI8GAIN設定

0dB

設定範囲

1dB以内

許容範囲

-79dBu以下

-95dBu以下

条件

入力150Ωショート

AI8GAIN設定

36dB

0dB

許容範囲

点灯

消灯

入力レベル

-8dBu

-13dBu

許容範囲

-50dBu以下

条件

入力150Ωショート

AI8GAIN設定

78dB

許容範囲

+23±1.0dBu

入力レベル

+23dBu

入力周波数

1kHz

AI8GAIN設定

0dB

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TEL 13942296513 QQ 376315150 892498299

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LMY2-MLAB

20

2-10.

音だし検査（CH1A、CH2A共）

 ・入力周波数1kHz

 ・UNCのDipSWをGAIN=スイープに設定します。

 出力レベルが変化することを確認します。



2-11.

CMG調整（CH1A、CH2A共）

条件

 ・下記の様に抵抗を接続します。



qVR100,VR200の調整



GAIN設定を48dBとし、LMY2-MLABに+8dBu/1kHzの信号を加え出力レベルが出来るだけ小さくなるよう半固定ボリ



 ューム（CH1AはVR100、CH2AはVR200）を調整します。調整後の出力レベルは-46dBu以下であることを確認します

。



wVR101,VR201の調整

 GAIN設定を18dBとし、LMY2-MLABに+8dBu/1kHzの信号を加え出力レベルが出来るだけ小さくなるよう半固定ボリ



 ューム（CH1AはVR101、CH2AはVR201）を調整します。調整後の出力レベルは-60dBu以下であることを確認します

。





VR***は多回転型（25±5回転）で、ストッパーがないので注意してください。また、メーカー出荷時にほぼ中央にセット



 されています。



3

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 AI8・AO8（UNC）DipSW設定

 AI8・AO8共にUNCシートの構成は同じですが、各DipSWの意味が違います。

 以下に設定を示しまが、いずれの場合もDipSW8は使用しません。（無効）

R124Ω注1

LMY2-MLAB（CH1AorCH2A）

H

C

G注1）24Ω抵抗2本の相対誤差は50mΩ以内とします。

INPUTAよりクロック供給

GAIN=+24dB設定

R124Ω注1

1



2,3,4

の順で



5

6

7

動作モード1:運用 0:デバック

1:ALLA

1:ALLOFF

1:ALLMIN(0dB)

0:ALLB

0:ALLON

0:2,3,4GAINモード

(*1)



WCSel

モード

(*1)



GAIN

モード

(*1)



A/BSel

ファントム

GAIN

1,1,1

Int48kHz

1,1,1

スイープ

(*2)

43218

CPU

1:ON

UNCシート

0:OFF 765

1,0,1

Int39kHz

1,0,1

66dB

0,1,1

Int44.1kHz

0,1,1

78dB

0,0,1

(OUTPUTA)

0,0,1

54dB

1,1,0

(OUTPUTB)

1,1,0

48dB

0,1,0

(OUTPUTC)

0,1,0

36dB

0,0,0

nouse

0,0,0

12dB

1,0,0

BNC

1,0,0

18dB

WCWCWC

 (*1):DipSW7がOFF時「WCSel＝Int48kHz固定かつDipSW2,3,4はGAINモード」となります。

 (*2):0dB→78dB→0dB→78dB・・・と2秒ごとに6dBずつ変化を繰り返します。

※AI8(UNC)DipSW設定 [1:ON(=GND)0:OFF(=+5V)]

4321

ON

8765

※AO8(UNC)DipSW設定 [1:ON(=GND)0:OFF(=+5V)]

 AO8DipSWの詳細については、LMY4-DAの検査をご参照ください。

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http://www.xiaoyu163.com

Yamaha LMY2-MLAB User manual

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