4D systems Picaso User manual

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Picaso Processor
Embedded Graphics Processor
DATASHEET
Document Revision: 2.0
Document Date: 26th July 2017

Picaso Processor Datasheet
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Table of Contents
1. Description .............................................................................................................. 4
2. Features................................................................................................................... 4
3. Applications ............................................................................................................. 5
4. Pin Configuration and Summary ............................................................................... 6
5. Pin Description......................................................................................................... 9
5.1. Display Interface .......................................................................................................... 9
5.2. SPI Interface –Memory Card .................................................................................... 10
5.3. Serial Ports –UARTS .................................................................................................. 10
5.4. Audio Interface........................................................................................................... 11
5.5. Touch Screen Interface.............................................................................................. 12
5.6. GPIO –General Purpose IO ....................................................................................... 12
5.7. System Pins................................................................................................................. 13
6. 4DGL –Software Language ..................................................................................... 13
7. In Circuit Serial Programming ................................................................................. 14
8. Picaso Architecture ................................................................................................ 14
8.1. PmmC Firmware......................................................................................................... 15
9. System Registers Memory Map .............................................................................. 16
10. Memory Cards –FAT16......................................................................................... 18
11. Hardware Tools .................................................................................................... 18
11.1. Programming Tools.................................................................................................. 18
11.2. Evaluation Display Modules .................................................................................... 19
12. 4D Labs - Workshop4 IDE...................................................................................... 20
12.1. Designer Environment............................................................................................. 20
12.2. ViSi Environment...................................................................................................... 20
12.3. ViSi Genie Environment........................................................................................... 21
12.4. Serial Environment................................................................................................... 21
13. Reference Design ................................................................................................. 22
14. Package Details .................................................................................................... 23
15. PCB Land Pattern.................................................................................................. 24

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16. Specifications and Ratings .................................................................................... 25
17. Revision History ................................................................................................... 26
18. Legal Notice ......................................................................................................... 27
19. Contact Information ............................................................................................. 27

Picaso Processor Datasheet
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1. Description
The Picaso Processor is a custom embedded 4DGL
graphics controller designed to interface with many
popular OLED and LCD display panels. Powerful
graphics, text, image, animation and countless more
features are built right inside the chip. It offers a
simple plug-n-play interface to many 16-bit 80-Series
colour LCD and OLED displays.
Picaso is designed to work with minimal design effort
as all of the data and control signals are provided by
the chip to interface directly to the display. This offers
enormous advantage to the designer in development
time and cost saving and takes away all of the burden
of low level design.
Note: If using Picaso, please refer to Section 8.1 for
information on customising the PmmC. Please
contact Technical Support or Sales before starting.
Picaso belongs to a family of processors powered by a
highly optimised soft core virtual engine, EVE
(Extensible Virtual Engine). EVE is a proprietary, high
performance virtual processor with an extensive byte-
code instruction set optimised to execute compiled
4DGL programs. 4DGL (4D Graphics Language) was
specifically developed from ground up for the EVE
engine core. It is a high level language which is easy to
learn and simple to understand yet powerful enough
to tackle many embedded graphics applications.
All of the display built-in driver libraries implement
and share the same high-level function interface. This
allows your GUI application to be portable to different
display controller types.
2. Features
Low-cost OLED, LCD and TFT display graphics user
interface solution.
Ideal as a standalone embedded graphics
processor or interface to any host controller as a
graphics co-processor.
Connect to any colour display that supports an 80-
Series 16 bit wide CPU interface. All data and
control signals are provided.
Built in high performance virtual processor core
(EVE) with an extensive byte-code instruction set
optimised for 4DGL, the high level 4D Graphics
Language.
Comprehensive set of built in graphics and
multimedia services.
Display full colour images, animations, icons and
video clips.
14KB of Flash memory for user code storage and
14KB of SRAM for user variables.
13 Digital I/O pins.
I2C interface (Master).
D0…D15, RD, WR, RS, CS – Display interface
FAT16 file services.
2 Asynchronous hardware serial ports
SPI interface support for SDHC/SD memory card
for multimedia storage and data logging purposes
(micro-SD with up to 2GB and SDHC memory
cards starting from 4GB and above).
4-Wire Resistive Touch panel interface.
Audio support for wave files and complex sound
generation with a dedicated 16-bit PWM audio
output.
8 x 16 bit timers with 1 millisecond resolution.
Single 3.3 Volt Supply @25mA typical.
Available in a 64 pin TQFP 10mm x 10mm
package.
RoHS compliant.

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3. Applications
General purposes embedded graphics.
Elevator control systems.
Point of sale terminals.
Electronic gauges and metres.
Test and measurement and general purpose
instrumentation.
Industrial control and Robotics.
Automotive system displays.
GPS navigation systems.
Medical Instruments and applications.
Home appliances and Smart Home Automation.
Security and Access control systems.
Gaming equipment.
Aviation systems.
HMI with touch panels.

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4. Pin Configuration and Summary
Picaso Processor Pin Out
PIN
SYMBOL
I/O
DESCRIPTION
1
IO1
I/O
General Purpose IO1 pin. This pin is 5.0V tolerant.
2
XR
A
4-Wire Resistive Touch Screen Right signal. Connect this pin to XR or X+
signal of the touch panel.
3
YU
A
4-Wire Resistive Touch Screen Up signal. Connect this pin to YU or Y+
signal of the touch panel.
4
SCK
O
SPI Serial Clock output. SD memory card use only. Connect this pin to
the SPI Serial Clock (SCK) signal of the memory card.
5
SDI
I
SPI Serial Data Input. SD memory card use only. Connect this pin to the
SPI Serial Data Out (SDO) signal of the memory card.
6
SDO
O
SPI Serial Data Output. SD memory card use only. Connect this pin to the
SPI Serial Data In (SDI) signal of the memory card.
7
RESET
I
Master Reset signal. Connect a 4.7K resistor from this pin to VCC.
8
SDCS
O
SD Memory-Card Chip Select. SD memory card use only. Connect this pin
to the Chip Enable (CS) signal of the memory card.
9, 20, 25, 41
GND
P
Device Ground.
10, 19, 26, 38, 57
VCC
P
Device Positive Supply.
I = Input, O = Output, P = Power, A = Analogue

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Picaso Processor Pin Out (continued…)
PIN
SYMBOL
I/O
DESCRIPTION
11
D5
I/O
Display Data Bus bit 5.
12
D4
I/O
Display Data Bus bit 4.
13
D3
I/O
Display Data Bus bit 3.
14
D2
I/O
Display Data Bus bit 2.
15
D1
I/O
Display Data Bus bit1.
16
D0
I/O
Display Data Bus bit 0.
17
D6
I/O
Display Data Bus bit 6.
18
D7
I/O
Display Data Bus bit 7.
21
D8
I/O
Display Data Bus bit 8.
22
D9
I/O
Display Data Bus bit 9.
23
D10
I/O
Display Data Bus bit 10.
24
D11
I/O
Display Data Bus bit 11.
27
D12
I/O
Display Data Bus bit 12.
28
D13
I/O
Display Data Bus bit 13.
29
D14
I/O
Display Data Bus bit 14.
30
D15
I/O
Display Data Bus bit 15.
31
RX1
I
Asynchronous Serial port COM1 receive pin, RX1. Connect this pin to
external serial device Transmit (Tx) signal. This pin is 5.0V tolerant.
32
TX1
O
Asynchronous Serial port COM1 transmit pin, TX1. Connect this pin to
external serial device receive (Rx) signal. This pin is 5.0V tolerant.
33
TX0
O
Asynchronous Serial port Transmit pin, TX. Connect this pin to host micro-
controller Serial Receive (Rx) signal. The host receives data from Picaso
via this pin. This pin is 5.0V tolerant.
34
RX0
I
Asynchronous Serial port Receive pin, RX. Connect this pin to host micro-
controller Serial Transmit (Tx) signal. The host transmits data to Picaso via
this pin. This pin is 5.0V tolerant.
35
RES
O
Display RESET. Picaso initialises the display by strobing this pin LOW.
Connect this pin to the Reset (RES) signal of the display.
36
SDA
I/O
I2C Data In/Out.
37
SCL
O
I2C Clock Output.
39
CLK1
I
Device Clock input 1 of a 12MHz crystal.
40
CLK2
O
Device Clock input 2 of a 12MHz crystal.
42
BUS6
I/O
General Purpose Parallel I/O BUS(0..7), bit 6. This pin is 5.0V tolerant.
43
BUS7
I/O
General Purpose Parallel I/O BUS(0..7), bit 7. This pin is 5.0V tolerant.
44
IO5/BUS_
WR
I/O
General Purpose IO5 pin. Also used for BUS_WR signal to write and latch
the data to the parallel GPIO BUS(0..7).
45
AUDENB
O
Audio Enable. Connect this pin to amplifier control.
LOW: Enable external Audio amplifier.
HIGH: Disable external Audio amplifier.
46
AUDIO
O
Pulse Width Modulated (PWM) Audio output. Connect this pin to a 2
stage low pass filter then into an audio amplifier.
47
XL
O
4-Wire Resistive Touch Screen Left signal. Connect this pin to XL or X-
signal of the touch panel.
48
YD
O
4-Wire resistive touch screen bottom signal. Connect this pin to YD or Y-
signal of the touch panel.
49
DCENB
O
DC-DC high voltage enable signal. This maybe the high voltage that drives
the LCD backlight or the OLED panel supply.
High: Enable DC-DC converter.
Low : Disable DC-DC converter.
50
BUS0
I/O
General Purpose Parallel I/O BUS(0..7), bit 0. This pin is 5.0V tolerant.
I = Input, O = Output, P = Power, A = Analogue

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Picaso Processor Pin Out (continued…)
PIN
SYMBOL
I/O
DESCRIPTION
51
BUS1
I/O
General Purpose Parallel I/O BUS(0..7), bit 1. This pin is 5.0V tolerant.
52
BUS2
I/O
General Purpose Parallel I/O BUS(0..7), bit 2. This pin is 5.0V tolerant.
53
BUS3
I/O
General Purpose Parallel I/O BUS(0..7), bit 3. This pin is 5.0V tolerant.
54
BUS4
I/O
General Purpose Parallel I/O BUS(0..7), bit 4. This pin is 5.0V tolerant.
55
BUS5
I/O
General Purpose Parallel I/O BUS(0..7), bit 5. This pin is 5.0V tolerant.
56
REF
P
Internal voltage regulator filter capacitor. Connect a 4.7uF to 10uF capacitor
from this pin to Ground.
58
WR
O
Display Write strobe signal. Picaso asserts this signal LOW when writing data to
the display. Connect this pin to the Write (WR) signal of the display.
59
RD
Display Read strobe signal. Picaso asserts this signal LOW when reading data
from the display. Connect this pin to the Read (RD) signal of the display.
60
CS
O
Display Chip Select. Picaso asserts this signal LOW when accessing the display.
Connect this pin to the Chip Select (CS) signal of the display.
61
RS
O
Display Register Select.
LOW: Display index or status register is selected.
HIGH: Display GRAM or register data is selected.
Connect this pin to the Register Select (RS or A0 or C/D or similar naming
convention) signal of the display.
62
IO4/BUS_RD
I/O
General Purpose IO4 pin. Also used for BUS_RD signal to read and latch the
data in to the parallel GPIO BUS(0..7).
63
IO3
I/O
General Purpose IO3 pin. This pin is 5.0V tolerant.
64
IO2
I/O
General Purpose IO2 pin. This pin is 5.0V tolerant.
I = Input, O = Output, P = Power, A = Analogue

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5. Pin Description
The Picaso Processor provides both a hardware and a
software interface. This section describes in detail the
hardware interface pins of the device.
5.1. Display Interface
The Picaso supports LCD and OLED displays with an 80-
Series 16-bit wide CPU data interface. The connectivity
to the display is easy and straight forward. The Picaso
generates all of the necessary timing to drive the
display.
CS
RS
RD
WR
Operation
0
0
0
1
Read Display Status Register
0
0
1
0
Write Display Index Register
0
1
0
1
Read Display GRAM Data
0
1
1
0
Write Register or GRAM Data
1
X
X
X
No Operation
Display Operation Table
D0-D15 pins (Display Data Bus):
The Display Data Bus (D0-D15) is a 16-bit bidirectional
port and all display data writes and reads occur over
this bus. Other control signals such as RW, RD CS, and
RS synchronise the data transfer to and from the
display.
CS pin (Display Chip Select):
The access to the display is only possible when the
Display Chip Select (CS) is asserted LOW. Connect this
pin to the Chip Select (CS) signal of the display.
RS pin (Display Register Select):
The RS signal determines whether a register command
or data is sent to the display.
LOW: Display index or status register is selected.
HIGH: Display GRAM or register data is selected.
Connect this pin to the Register Select (RS) signal of
the display. Different displays utilise various naming
conventions such as RS, A0, C/D or similar. Be sure to
check with your display manufacturer for the correct
name and function.
RES pin (Display Reset):
Display RESET. Picaso initialises the display by strobing
this pin LOW. Connect this pin to the Reset (RES) signal
of the display.
DCENB pin (External DC/DC Enable):
DC-DC high voltage enable signal. This maybe the high
voltage that drives the LCD backlight or the OLED
panel supply.
WR pin (Display Write):
This is the display write strobe signal. The Picaso
asserts this signal LOW when writing data to the
display in conjunction with the display data bus (D0-
D15). Connect this pin to the Write (WR) signal of the
display.
Item
Sym
Min
Typ
Max
Write Low Pulse
tWL
50
-
-
Write High Pulse
tWH
50
-
-
Write Bus Cycle Total
tWT
100
-
-
Write Data Setup
tDS
25
-
-

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RD pin (Display Read):
This is the display read strobe signal. The Picaso
asserts this signal LOW when reading data from the
display in conjunction with the display data bus (D0-
D15). Connect this pin to the Read (RD) signal of the
display.
Item
Sym
Min
Typ
Max
Read Low Pulse
tRL
150
-
-
Read High Pulse
tRH
150
-
-
Read Bus Cycle Total
tRT
300
-
-
Read Data Hold
tDH
75
-
-
5.2. SPI Interface –Memory Card
The Picaso supports SD, micro-SD and MMC memory
cards via its hardware SPI interface. The memory card
is used for all multimedia file retrieval such as images,
animations and movie clips and the SPI interface is
dedicated for this purpose only. The memory card can
also be used as general purpose storage for data
logging applications (RAW and FAT16 format support).
Support is available for micro-SD with up to 2GB
capacity and for high capacity HC memory cards
starting from 4GB and above.
SDI pin (SPI Serial Data In):
The SPI Serial Data Input (SDI). SD memory card use
only. Connect this pin to the SPI Serial Data Out (SDO)
signal of the memory card.
SDO pin (SPI Serial Data Out):
The SPI Serial Data Output (SDI). SD memory card use
only. Connect this pin to the SPI Serial Data In (SDI)
signal of the memory card.
SCK pin (SPI Serial Clock):
The SPI Serial Clock output (SCK). SD memory card use
only. Connect this pin to the SPI Serial Clock (SCK)
signal of the memory card.
SDCS pin (SD Memory Card Chip Select):
SD Memory-Card Chip Select (SDCS). SD memory card
use only. Connect this pin to the Chip Enable (CS)
signal of the memory card.
5.3. Serial Ports –UARTS
The Picaso Processor has two dedicated hardware
Asynchronous Serial ports that can communicate with
external serial devices. These are referred to as the
COM0 and the COM1 serial ports.
The primary features are:
Full-Duplex 8 bit data transmission and reception.
Data format: 8 bits, No Parity, 1 Stop bit.
Independent Baud rates from 300 baud up to
256K baud.
Single byte transmits and receives or a fully
buffered service. The buffered service feature
runs in the background capturing and buffering
serial data without the user application having to
constantly poll any of the serial ports. This frees
up the application to service other tasks.

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A single byte serial transmission consists of the start
bit, 8-bits of data followed by the stop bit. The start bit
is always 0, while a stop bit is always 1. The LSB (Least
Significant Bit, Bit 0) is sent out first following the start
bit. Figure below shows a single byte transmission
timing diagram.
COM0 is also the primary interface for 4DGL user
program downloads and chip configuration PmmC
programming. Once the compiled 4DGL application
program (EVE byte-code) is downloaded and the user
code starts executing, the serial port is then available
to the user application.
Refer to Section 7. In Circuit Serial Programming for
more details on PmmC/Firmware programming.
TX0 pin (Serial Transmit COM0):
Asynchronous Serial port COM0 transmit pin, TX0.
Connect this pin to external serial device receive (Rx)
signal. This pin is 5.0V tolerant.
RX0 pin (Serial Receive COM0):
Asynchronous Serial port COM0 receive pin, RX0.
Connect this pin to external serial device transmit (Tx)
signal. This pin is 5.0V tolerant.
TX1 pin (Serial Transmit COM1):
Asynchronous Serial port COM1 transmit pin, TX1.
Connect this pin to external serial device receive (Rx)
signal. This pin is 5.0V tolerant.
RX1 pin (Serial Receive COM1):
Asynchronous Serial port COM1 receive pin, RX1.
Connect this pin to external serial device transmit (Tx)
signal. This pin is 5.0V tolerant.
5.4. Audio Interface
The exclusive audio support in the Picaso Processor
makes it better than its peers in the Graphics
processor range. PWM ensures better sound quality
with a volume range of 8 to 127. A simple instruction
empowers the user to execute the audio files. Audio
operation can be carried out simultaneously with the
execution of other necessary instructions.
For a complete list of audio commands please refer to
the separate document titled:
Picaso Internal Functions Manual
AUDIO pin (Audio PWM output):
External Amplifier Output pin. This pin provides a 16-
bit DAC/PWM audio output to use with an external
audio amplifier. Example circuit below provides a low
cost implementation. If unused then this pin must be
left open or floating.
Optional Power Audio Circuit
AUDENB pin (Audio Enable output):
External Amplifier enable pin. This pin provides
ON/OFF amplifier control. If unused then this pin must
be left open or floating.
LOW: Enable external Audio amplifier.
HIGH: Disable external Audio amplifier.

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5.5. Touch Screen Interface
The Picaso supports 4-Wire resistive touch panels. The
diagram below shows a simplified interface between
the Picaso and a touch panel.
XR pin (Touch Panel X-Read input):
4-Wire Resistive Touch Screen X-Read analog signal.
Connect this pin to XR or X+ signal of the touch panel.
XL pin (Touch Panel X-Drive output):
4-Wire Resistive Touch Screen X Drive signal. Connect
this pin to XL or X- signal of the touch panel.
YU pin (Touch Panel Y-Read input):
4-Wire Resistive Touch Screen Y-Read analog signal.
Connect this pin to YU or Y+ signal of the touch panel.
YD pin (Touch Panel Y-Drive output):
4-Wire Resistive Touch Screen Y Drive signal. Connect
this pin to YD or Y- signal of the touch panel.
5.6. GPIO –General Purpose IO
There are 13 general purpose Input/Output (GPIO)
pins available to the user. These are grouped as
IO1..IO5 and BUS0..BUS7. The 5 I/O pins (IO1..IO5),
provide flexibility of individual bit operations while the
8 pins (BUS0..BUS7), known as GPIO BUS, serve
collectively for byte wise operations. The IO4 and IO5
also act as strobing signals to control the GPIO Bus.
GPIO Bus can be read or written by strobing a low
pulse (50 nsec duration or greater) the IO4/BUS_RD or
IO5/BUS_WR for read or write respectively. For
detailed usage refer to the separate document titled:
Picaso Internal Functions Manual
IO1-IO3 pins (3 x GPIO pins):
General purpose I/O pins. Each pin can be individually
set for INPUT or an OUTPUT. Power-Up Reset default
is all INPUTS.
IO4/BUS_RD pin (GPIO IO4 or BUS_RD pin):
General Purpose IO4 pin. Also used for BUS_RD signal
to read and latch the data in to the parallel GPIO
BUS0..BUS7.
IO5/BUS_WR pin (GPIO IO5 or BUS_WR pin):
General Purpose IO5 pin. Also used for BUS_WR signal
to write and latch the data to the parallel GPIO
BUS0..BUS7.
BUS0-BUS7 pins (GPIO 8-Bit Bus):
8-bit parallel General purpose I/O Bus.
Note: All GPIO pins are 5.0V tolerant.

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5.7. System Pins
VCC pins (Device Supply Voltage):
Device supply voltage pins. These pins must be
connected to a regulated supply voltage in the range
of 3.0 Volts to 3.6 Volts DC. Nominal operating voltage
is 3.3 Volts.
GND pins (Device Ground):
Device ground pins. These pins must be connected to
system ground.
RESET pin (Device Master Reset):
Device Master Reset pin. An active low pulse of
greater than 2 micro-seconds will reset the device.
Connect a resistor (1K through to 10K, nominal 4.7K)
from this pin to VCC. Only use open collector type
circuits to reset the device if an external reset is
required. This pin is not driven low by any internal
conditions.
CLK1, CLK2 pins (Device Oscillator Inputs):
CLK1 and CLK2 are the device oscillator pins. Connect
a 12MHz AT strip cut crystal with 22pF capacitors from
each pin to GND as shown in the diagram below.
6. 4DGL –Software Language
The Picaso processor belongs to a family of processors
powered by a highly optimised soft core virtual
engine, EVE (Extensible Virtual Engine).
EVE is a proprietary, high performance virtual-
machine with an extensive byte-code instruction set
optimised to execute compiled 4DGL programs. 4DGL
(4D Graphics Language) was specifically developed
from ground up for the EVE engine core. It is a high
level language which is easy to learn and simple to
understand yet powerful enough to tackle many
embedded graphics applications.
4DGL is a graphics oriented language allowing rapid
application development, and the syntax structure
was designed using elements of popular languages
such as C, Basic, Pascal and others.
Programmers familiar with these languages will feel
right at home with 4DGL. It includes many familiar
instructions such as IF..ELSE..ENDIF, WHILE..WEND,
REPEAT..UNTIL, GOSUB..ENDSUB, GOTO, PRINT as
well as some specialised instructions SERIN, SEROUT,
GFX_LINE, GFX_CIRCLE and many more.
For detailed information pertaining to the 4DGL
language, please refer to the following documents:
4DGL Programmer's Reference Manual
Picaso Internal Functions Manual
To assist with the development of 4DGL applications,
the Workshop4 IDE combines a full-featured editor, a
compiler, a linker and a downloader into a single PC-
based application. It's all you need to code, test and
run your applications.

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7. In Circuit Serial Programming
The Picaso processor is a custom graphics processor.
All functionality including the high level commands are
built into the chip. This chip level configuration is
available as a Firmware/PmmC (Personality-module-
micro-Code) file.
A PmmC file contains all of the low level micro-code
information (analogy of that of a soft silicon) which
define the characteristics and functionality of the
device. The ability of programming the device with a
PmmC file provides an extremely flexible method of
customising as well as upgrading it with future
enhancements.
A PmmC file can only be programmed into the device
via its COM0 serial port and an access to this must be
provided for on the target application board. This is
referred to as In Circuit Serial Programming (ICSP).
Figure below provides a typical implementation for
the ICSP interface.
The PmmC file is programmed into the device with the
aid of Workshop4, the 4D Labs IDE software (See
Section 12). To provide a link between the PC and the
ICSP interface, a specific 4D Programming Cable is
required and is available from 4D Systems.
Using a non-4D programming interface could damage
your processor, and void your Warranty.
Note: The Picaso processor is shipped blank and it
must be programmed with the PmmC configuration
file.
8. Picaso Architecture
The figure below illustrates the Picaso Processors
architecture.
Picaso is a high level graphics processor which runs the
high level 4DGL (4D Graphics Language).
It is not a conventional microcontroller with
conventional microcontroller architecture, it is a
custom graphics processor and therefore low level
access to the chip is not required nor available to the
User.
4DGL provides high level functions for the User and
does all the low level work in the background in a
highly optimised fashion.

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8.1. PmmC Firmware
PmmC (Personality Module Micro-Code) - this is the
operating system, incorporating the EVE runtime
(Extensible Virtual Engine) which has an extensive
byte-code instruction set programmed via the
Workshop4 Software IDE.
The PmmC Loader can be thought of like a bootloader,
and allows the transfer of a PmmC from the Users’ PC
into the System Flash storage on the Picaso processor.
Within the PmmC are hundreds of builtin functions for
graphics, sound, math functions etc, no need to
include libraries, or wait for hefty compile times –it’s
all built in.
The PmmC is in protected memory, and cannot be
read or damaged by inadvertent writes to illegal FLASH
areas.
The PmmC is upgradable by the User and can be done
at any time. It however will wipe the Users application
from Flash, so this will need to be reloaded after a
PmmC update is completed.
Loading the PmmC is achieved using our PmmC Loader
tool, or using the ScriptC command line tool.
Note: IMPORTANT!!! If you are wanting to use
Picaso in a product, please contact the 4D Labs Tech
Support or Sales departments to discuss your
requirements. PmmC’s can ONLY be created by 4D
Labs, and depending on the display you have
selected and the Driver IC it uses, will determine
how difficult the process is. Please make contact
with us BEFORE you start.

Picaso Processor Datasheet
©2017 4D Labs Semiconductors Page 16 of 27
www.4dsystems.com.au
9. System Registers Memory Map
The following tables outline in detail the Picaso system registers and flags.
Picaso System Registers and Flags
LABEL
ADDRESS
USAGE
DEC
HEX
RANDOM_LO
32
0x20
random generator LO word
RANDOM_HI
33
0x21
random generator HI word
SYSTEM_TIMER_LO
34
0x22
1msec system timer LO word
SYSTEM_TIMER_HI
35
0x23
1msec system timer HI word
TIMER0
36
0x24
1msec user timer 0
TIMER1
37
0x25
1msec user timer 1
TIMER2
38
0x26
1msec user timer 2
TIMER3
39
0x27
1msec user timer 3
TIMER4
40
0x28
1msec user timer 3
TIMER5
41
0x29
1msec user timer 3
TIMER6
42
0x2A
1msec user timer 3
TIMER7
43
0x2B
1msec user timer 3
SYS_X_MAX
44
0x2C
display hardware X res-1
SYS_Y_MAX
45
0x2D
display hardware Y res-1
GFX_XMAX
46
0x2E
width of current orientation
GFX_YMAX
47
0x2F
height of current orientation
GFX_LEFT
48
0x30
image left real point
GFX_TOP
49
0x31
image top real point
GFX_RIGHT
50
0x32
image right real point
GFX_BOTTOM
51
0x33
image bottom real point
GFX_X1
52
0x34
image left clipped point
GFX_Y1
53
0x35
image top clipped point
GFX_X2
54
0x36
image right clipped point
GFX_Y2
55
0x37
image bottom clipped point
GFX_X_ORG
56
0x38
current X origin
GFX_Y_ORG
57
0x39
current Y origin
GFX_HILITE_LINE
58
0x3A
current multi line button hilite line
GFX_LINE_COUNT
59
0x3B
count of lines in multiline button
GFX_LAST_SELECTION
60
0x3C
Last selected line
GFX_HILIGHT_BACKGROUND
61
0x3D
multi button hilite background colour
GFX_HILIGHT_FOREGROUND
62
0x3E
multi button hilite background colour
GFX_BUTTON_FOREGROUND
63
0x3F
store default text colour for hilite line tracker
GFX_BUTTON_BACKGROUND
64
0x40
store default button colour for hilite line tracker
GFX_BUTTON_MODE
65
0x41
store current buttons mode
GFX_TOOLBAR_HEIGHT
66
0x42
height above
GFX_STATUSBAR_HEIGHT
67
0x43
height below
GFX_LEFT_GUTTER_WIDTH
68
0x44
width to left
GFX_RIGHT_GUTTER_WIDTH
69
0x45
width to right
GFX_PIXEL_SHIFT
70
0x46
pixel shift for button depress illusion
GFX_VECT_X1
71
0x47
gp rect, used by multiline button to hilite required line

Picaso Processor Datasheet
©2017 4D Labs Semiconductors Page 17 of 27
www.4dsystems.com.au
Picaso System Registers and Flags (continued…)
LABEL
ADDRESS
USAGE
DEC
HEX
GFX_VECT_Y1
72
0x48
GFX_VECT_X2
73
0x49
GFX_VECT_Y2
74
0x4A
GFX_THUMB_PERCENT
75
0x4B
size of slider thumb as percentage
GFX_THUMB_BORDER_DARK
76
0x4C
darker shadow of thumb
GFX_THUMB_BORDER_LIGHT
77
0x4D
lighter shadow of thumb
TOUCH_XMINCAL
78
0x4E
touch calibration value
TOUCH_YMINCAL
79
0x4F
touch calibration value
TOUCH_XMAXCAL
80
0x50
touch calibration value
TOUCH_YMAXCAL
81
0x51
touch calibration value
IMG_WIDTH
82
0x52
width of currently loaded image
IMG_HEIGHT
83
0x53
height of currently loaded image
IMG_FRAME_DELAY
84
0x54
if image, else inter frame delay for movie
IMG_FLAGS
85
0x55
bit 4 determines colour mode, other bits reserved
IMG_FRAME_COUNT
86
0x56
count of frames in a movie
IMG_PIXEL_COUNT_LO
87
0x57
count of pixels in the current frame
IMG_PIXEL_COUNT_HI
88
0x58
count of pixels in the current frame
IMG_CURRENT_FRAME
89
0x59
last frame shown
MEDIA_ADDRESS_LO
90
0x5A
micro-SD byte address LO
MEDIA_ADDRESS_HI
91
0x5B
micro-SD byte address HI
MEDIA_SECTOR_LO
92
0x5C
micro-SD sector address LO
MEDIA_SECTOR_HI
93
0x5D
micro-SD sector address HI
MEDIA_SECTOR_COUNT
94
0x5E
micro-SD number of bytes remaining in sector
TEXT_XPOS
95
0x5F
text current x pixel position
TEXT_YPOS
96
0x60
text current y pixel position
TEXT_MARGIN
97
0x61
text left pixel pos for carriage return
TXT_FONT_TYPE
98
0x62
font type, 0 = system font, else pointer to user font
TXT_FONT_MAX
99
0x63
max number of chars in font
TXT_FONT_OFFSET
100
0x64
starting offset (normally 0x20)
TXT_FONT_WIDTH
101
0x65
current font width
TXT_FONT_HEIGHT
102
0x66
Current font height
GFX_TOUCH_REGION_X1
103
0x67
touch capture region
GFX_TOUCH_REGION_Y
104
0x68
GFX_TOUCH_REGION_X2
105
0x69
GFX_TOUCH_REGION_Y2
106
0x6A
GFX_CLIP_LEFT_VAL
107
0x6B
left clipping point (set with gfx_ClipWindow(...)
GFX_CLIP_TOP_VAL
108
0x6C
top clipping point (set with gfx_ClipWindow(...)
GFX_CLIP_RIGHT_VAL
109
0x6D
right clipping point (set with gfx_ClipWindow(...)
GFX_CLIP_BOTTOM_VAL
110
0x6E
bottom clipping point (set with gfx_ClipWindow(...)
GFX_CLIP_LEFT
111
0x6F
current clip value (reads full size if clipping turned off)
GFX_CLIP_TOP
112
0x70
current clip value (reads full size if clipping turned off)
GFX_CLIP_RIGHT
113
0x71
current clip value (reads full size if clipping turned off)
GFX_CLIP_BOTTOM
114
0x72
current clip value (reads full size if clipping turned off)
GRAM_PIXEL_COUNT_LO
115
0x73
LO word of count of pixels in the set GRAM area
GRAM_PIXEL_COUNT_HI
116
0x74
HI word of count of pixels in the set GRAM area
NOTE: These registers are accessible with peekW and pokeW functions.

Picaso Processor Datasheet
©2017 4D Labs Semiconductors Page 18 of 27
www.4dsystems.com.au
10. Memory Cards –FAT16
The Picaso Processor uses
off the shelf standard
SDHC/SD/micro-SD
memory cards with up to
2GB capacity usable with
FAT16 formatting. For any
FAT file related operations,
before the memory card can be used it must first be
formatted with FAT16 option. The formatting of the
card can be done on any PC system with a card reader.
Select the appropriate drive and choose the FAT16 (or
just FAT in some systems) option when formatting.
The card is now ready to be used in the Picaso based
application.
The Picaso Processor also
supports high capacity HC
memory cards (4GB and
above). The available capacity
of SD-HC cards varies
according to the way the card is partitioned and the
commands used to access it.
The FAT partition is always first (if it exists) and can be
up to the maximum size permitted by FAT16. Windows
7 will format FAT16 up to 4GB. Windows XP will format
FAT16 up to 2GB and the Windows XP command
prompt will format FAT16 up to 4GB.
RMPET, a 4D Labs Tool found in the Workshop4 IDE, is
capable of repartitioning and formatting microSD
cards to be the appropriate type and format for 4D
Labs processors. This should be used for all cards.
Note: A SPI Compatible SDHC/SD/micro-SD card
MUST be used. Picaso along with other 4D Labs
Processors require SPI mode to communicate with
the SD card. If a non-SPI compatible SD card is used
then the processor will simply not be able to mount
the card.
11. Hardware Tools
The following hardware tools are required for full
control of the Picaso Processor.
11.1. Programming Tools
The 4D Programming Cable, uUSB-PA5 Programming
Adaptors, and gen4-PA (gen4 Programming Adaptor)
are essential hardware tools to program, customise
and test the Picaso Processor. Anyone of these can be
used.
The 4D programming interfaces are used to program a
new Firmware/PmmC, Display Driver and for
downloading compiled 4DGL code into the processor.
They even serve as an interface for communicating
serial data to the PC.
The 4D Programming Cable, uUSB-PA5 Programming
Adaptors, and gen4-PA are available from 4D Systems,
www.4dsystems.com.au
Using a non-4D programming interface could damage
your processor, and void your Warranty.
4D Programming Cable
uUSB-PA5 Programming Adaptor
gen4-PA (gen4 Programming Adaptor)

Picaso Processor Datasheet
©2017 4D Labs Semiconductors Page 19 of 27
www.4dsystems.com.au
11.2. Evaluation Display Modules
The following modules, available from 4D Systems, can be used for evaluation purposes to discover what the Picaso
processor has to offer.
gen4-uLCD-24PT –2.4” Intelligent Picaso Display
gen4-uLCD-28PT –2.8” Intelligent Picaso Display
gen4-uLCD-32PT –3.2” Intelligent Picaso Display
Note: gen4 Picaso display module plastic ships in Red colour, not white as pictured.

Picaso Processor Datasheet
©2017 4D Labs Semiconductors Page 20 of 27
www.4dsystems.com.au
12. 4D Labs - Workshop4 IDE
Workshop4 is a comprehensive software IDE that
provides an integrated software development
platform for all of the 4D family of processors and
modules. The IDE combines the Editor, Compiler,
Linker and Down- Loader to develop complete 4DGL
application code. All user application code is
developed within the Workshop4 IDE.
The Workshop4 IDE supports multiple development
environments for the user, to cater for different user
requirements and skill level.
The Designer environment enables the user to
write 4DGL code in its natural form to program
the Picaso module.
A visual programming experience, suitably called
ViSi, enables drag-and-drop type placement of
objects to assist with 4DGL code generation and
allows the user to visualise how the display will
look while being developed.
An advanced environment called ViSi-Genie
doesn’t require any 4DGL coding at all, it is all
done automatically for you. Simply lay the display
out with the objects you want, set the events to
drive them and the code is written for you
automatically. ViSi-Genie provides the latest rapid
development experience from 4D Labs.
A Serial environment is also provided to
transform the Picaso module into a slave serial
module, allowing the user to control the display
from any host microcontroller or device with a
serial port.
The Workshop4 IDE is available from the 4D Labs
website. www.4dsystems.com.au
For a comprehensive manual on the Workshop4 IDE
Software along with other documents, refer to the
documentation from the 4D Labs website, on the
Workshop4 product page.
12.1. Designer Environment
Choose the Designer environment to write 4DGL code
in its raw form.
The Designer environment provides the user with a
simple yet effective programming environment where
pure 4DGL code can be written, compiled and
downloaded to the Picaso.
12.2. ViSi Environment
ViSi was designed to make the creation of graphical
displays a more visual experience.
ViSi is a great software tool that allows the user to see
the instant results of their desired graphical layout.
Additionally, there is a selection of inbuilt dials, gauges
and meters that can simply be placed onto the
simulated module display. From here each object can
have its properties edited, and at the click of a button
all relevant 4DGL code associated with that object is
produced in the user program. The user can then write
4DGL code around these objects to utilise them in the
way they choose.