IBM PowerPC 405GP User manual

----
----
-- ---
- ---
- ~ ---
- -- ---
.-----
-~-y-
PowerPC 405GP
Embedded Processor
User's Manual
Preliminary Volume 1
GK10-3118-03

Sixth Preliminary Edition (June 2000)
This edition of IBM PowerPC 405GP Embedded Processor User's Manual applies to the IBM PowerPCTM
405GP 32-bit embedded processor, until otherwise indicated in new versions or application notes.
The following paragraph does not apply to the United Kingdom or any country where such provisions
are
inconsistent with local law: INTERNATIONAL BUSINESS MACHINES CORPORATION PROVIDES
THIS MANUAL
"AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED,
INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE. Some states
do not allowdisclaimer of express or implied warranties in
certain transactions; therefore,
this statement may not apply to you.
IBM does not warrant that the products in this publication, whether individually or as one or more groups, will
meet your requirements or that the publication or the accompanying product descriptions are error-free.
This publication could contain technical inaccuracies or typographical errors. Changes are periodically made to
the information herein; these changes will be incorporated
in new editions of the publication. IBM may make
improvements and/or changes
in the product(s) and/or program(s) described in this publication at any time.
It is possible that this publication may contain references to, or information about, IBM products (machines and
programs), programming, or services that are not announced
in your country. Such references or information
must not be construed to mean that IBM intends to announce such IBM products, programming, or services
in
your country. Any reference to an IBM licensed program in this publication is not intended to state or imply that
you can use only IBM's licensed program.
You can use any functionally equivalent program instead.
While the information contained herein is believed to be accurate, such information is preliminary, and should not
be relied upon for accuracy orcompleteness, and no representations orwarranties of accuracy or completeness
are made.
No part of this publication may be reproduced or distributed
in any form or by any means, or stored in a data
base or retrieval system, without the written permission of IBM.
Requests for copies of this publication and for technical information about IBM products should be made to your
IBM Authorized Dealer or your IBM Marketing Representative.
Address technical queries about this product to [email protected]
Address comments about this publication to:
IBM Corporation
Department YM5A
P.O. Box 12195
Research Triangle Park, NC 27709
IBM may use or distribute whatever information you supply in any way it believes appropriate without incurring
any obligation to you.
© Copyright International Business Machines Corporation 1996, 2000. All rights reserved
4321
Notice to U.S. Government Users -Documentation Related to Restricted Rights -Use, duplication, or
disclosure is subject to restrictions set forth
in GSA ADP Schedule Contract with IBM Corporation.
Preliminary

Patents and Trademarks
IBM may have patents or pending patent applications covering the subject matter in this publication. The
furnishing of this publication does not give you any license to these patents.
You can send license inquiries, in
writing, to the IBM Director of Licensing, IBM Corporation, North Castle Drive, Armonk,
NY 10504, United States
of America.
The following terms are trademarks of IBM Corporation:
IBM
CodePack
CoreConnect
PowerPC
PowerPC Architecture
RISCTrace .
RISCWatch
Other terms which are trademarks are the property of their respective owners.

Preliminary

Contents
Figures ..................................•................:...............................................................................xxix
Tables ......•..............................................................................................•..................................xli
About This Book .............................................................................................................:..... xlvii
Who Should Use This Book ......................................................................................... """"'"'''''''''''''''''''''''' xlvii
How to Use This Book .................................................................................................................................... xlvii
Conventions ................................................................................................................................................... xlviii
Part I. Introducing the PPC405GP Embedded Processor ................................................... 1-1
Chapter 1. Overview ............................................................................................................... 1-1
PPC405GP Features """'"'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' .......................................... 1-2
Bus and Peripheral Features ....................................................................................................................... 1-2
PowerPC Processor Core Features ............................................................................................................ 1-3
PowerPC Architecture .""""".""""""""" .. """"""." .. """".""".""""" ... """"""."" ....................................... 1-4
The PPC405GP as a PowerPC Implementation .............................................................................................. 1-5
RISC Processor Core Organization .................................................................................;............................... 1-5
Instruction and Data Cache Controllers ....................................................................................................... 1-5
Instruction Cache Unit ............................................................................................................................ 1-6
Data Cache Unit
.. """ .. """""" .. """"""".""."."".""."" ... """"""""."""" ............................................ 1-6
Memory Management Unit .......................................................................................................................... 1-6
Timer Facilities ............................................................................................................................................ 1-8
Debug .......................................................................................................................................................... 1-8
Development Tool Support """""'"'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' .......................... 1-8
Debug Modes
""""""".""""""""".""".""".".".""".""".""""" .. """""" ............................................. 1-9
Processor Core Interfaces ............................. ""'" ............................ """"'"'''''''''''''''' ................................ 1-9
Processor Local Bus ...................................................................................... "".""." .. """".""""""." ... 1-9
Device Control Register Bus ................................................................................................................... 1-9
Clock and Power Management ""'"'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' ........................ 1-9
JTAG ....................................................................................................................................................... 1-9
Interrupts .. """'"'''''''''' ......................................... """"" ........ "" .. " .. " .. ".. .............................................. 1-9
On-Chip Memory .................................................................................................................................... 1-9
Processor Core Programming Model ............................................................................................................... 1-9
Data Types ................................................................................................................................................ 1-10
Processor Core Register Set Summary .................................................................................................... 1-10
General Purpose Registers ................................................................................................................... 1-10
Special Purpose Registers ...................................... ""."... ................................................................... 1-10
Machine State Register ........................................................................................................................ 1-10
Condition Register
"""""'"'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' ......................................... 1-11
Device Control Registers .......... """""""""".".""."" .. ".""." ... ".""." .. "" ............................ """""""" 1-11
Memory-Mapped 1/0 Registers """""""""""""""'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' ....................... 1-11
Addressing Modes ..................................................................................................................................... 1-11
Chapter 2. On-Chip Buses ..................................................................................................... 2-1
Processor Local Bus ........................................................................................................................................ 2-1
PLB Features .............................................................................................................................................. 2-2
PLB Masters and Slaves ............................................................................................................................. 2-2
PLB Master Assignments ............................................................................................................................ 2-2
PLB Transfer Protocol """""""."""""."""""" ... """""." .. """."""" .. """"."""."" .................................... 2-3
Overlapped PLB Transfers .......................................................................................................................... 2-4
PLB Arbiter Registers """'"'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' ............................................. 2-5
PLB Arbiter Control Register (PLBO_ACR) ............................................................................................. 2-5
PLB Error Address Register (PLBO_BEAR) ............................................................................................ 2-5
Preliminary Contents v

PLB Error Status Register (PLBO_BESR) .............................................................................................. 2-6
PLB to OPB Bridge Registers ....................................................................................... ... ........................... 2-8
Bridge Error Address Register (POBO_BEAR) ....................................................................................... 2-8
Bridge Error Status Registers (POBO_BESRO-POBO_BESR1) ............................................................ 2-8
On-Chip Peripheral Bus ....................................................................................................................... 2-11
OPB Features ........................................................................................................................................... 2-11
OPB Master Assignments ......................................................................................................................... 2-12
OPB Arbiter Registers ............................................................................................................................... 2-12
OPB Arbiter Control Register (OPBAO_CR) ......................................................................................... 2-12
OPB Arbiter Priority Register (OPBAO_PR) ......................................................................................... 2-13
Part II. The PPC405GP RiSe Processor ............................................................................... 11-1
Chapter 3. Programming Model ............................................................................................3-1
User and Privileged Programming Models ...................................................................................................... 3-1
Memory Organization and Addressing ............................................................................................................ 3-1
Physical Address Map ............................................................................................. ... ................................ 3-2
Storage Attributes ....................................................................................................................................... 3-3
Registers .............................................
... ......................................................................................................... 3-3
General Purpose Registers (RO-R31) ......................................................................................................... 3-6
Special Purpose Registers.......................................................................................................................... 3-6
Count Register (CTR)
... ..................................................................................................... ... .................. 3-7
Link Register (LR) ................................................................................................................................. 3-8
Fixed Point Exception Register (XER) ...............
... ................................................................................. 3-8
Special Purpose Register General (SPRGO-SPRG7) ......................................................................... 3-11
Processor Version Register (PVR) ....................................................................................................... 3-12
Condition Register (CR) ............................................................................................................................ 3-12
CR Fields after Compare Instructions .................................................................................................. 3-13
The
CRO Field ...................................................................................................................................... 3-14
The Time Base .......................................................................................................................................... 3-15
Machine State Register (MSR) ................................................................................................................. 3-15
Device Control Registers .......................................................................................................................... 3-16
Directly Accessed DCRs ...................................................................................................................... 3-17
Indirectly Accessed DCRs .................................................................................................................... 3-19
Indirect Access of SDRAM Controller DCRs ............................................................................................ 3-19
Indirect Access of External Bus Controller DCRs ..................................................................................... 3-20
Indirect Access of Decompression Controller DCRs ................................................................................ 3-21
Memory-Mapped Input/Output Registers .................................................................................................. 3-22
Directly Accessed MMIO Registers ..................................................................................................... 3-22
Indirectly Accessed MMIO Registers ................................................................................................... 3-25
Data Types and Alignment ............................................................................................................................ 3-26
Alignment for Storage Reference and Cache Control Instructions ........................................................... 3-27
Alignment and Endian Operation .............................................................................................................. 3-27
Summary of Instructions Causing Alignment Exceptions ......................................................................... 3-28
Byte Ordering ............................................................................................................................................... 3-28
Structure Mapping Examples ........................................................................................
... ......................... 3-29
Big Endian Mapping ............................................................................................................................. 3-29
Little Endian Mapping ........................................................................................................................... 3-30
Support for Little Endian Byte Ordering .................................................................................................... 3-30
Endian (E) Storage Attribute ..................................................................................................
... ................ 3-30
Fetching Instructions from Little Endian Storage Regions ................................................................... 3-31
Accessing Data in Little Endian Storage Regions ................................................................................
3-31
PowerPC Byte-Reverse Instructions .................................................................................................... 3-32
Instruction Processing ................................................................................................................................... 3-33
Branch Processing ..............................................................................................
... ....................................... 3-34
Unconditional Branch Target Addressing Options .................................................................................... 3-34
Conditional Branch Target Addressing Options ........................................................................................ 3-35
vi PPC405GP User's Manual Preliminary

Conditional Branch Condition Register Testing ......................................................................................... 3-35
BO Field on Conditional Branches ............................................................................................................ 3-35
Branch Prediction ...................................................................................................................................... 3-36
Speculative Accesses .................................................................................................................................... 3-37
Speculative Accesses in the PPC405GP .................................................................................................. 3-37
Prefetch Distance Down an Unresolved Branch Path .......................................................................... 3-38
Prefetch of Branches to the CTR and Branches to the LR ................................................................... 3-38
Preventing Inappropriate Speculative Accesses ....................................................................................... 3-38
Fetching Past an Interrupt-Causing or Interrupt-Returning Instruction ................................................. 3-39
Fetching Past tw or twi Instructions ...................................................................................................... 3-39
Fetching Past an Unconditional Branch ................................................................................................ 3-40
Suggested Locations of Memory-Mapped Hardware ............................................................................ 3-40
Summary ................................................................................................................................................... 3-41
Privileged Mode Operation ............................................................................................................................ 3-41
MSR Bits and Exception Handling ............................................................................................................ 3-41
Privileged Instructions ............................................................................................................................... 3-42
Privileged SPRs ........................................................................................................................................ 3-42
Privileged DCRs ........................................................................................................................................ 3-43
Synchronization ............................................................................................................................................. 3-43
Context Synchronization ........................................................................................................................... 3-44
Executio!,,! Synchronization ........................................................................................................................ 3-46
Storage Synchronization ........................................................................................................................... 3-46
Instruction Set ................................................................................................................................................ 3-47
Instructions Specific to IBM PowerPC Embedded Processors ................................................................. 3-48
Storage Reference Instructions ................................................................................................................. 3-48
Arithmetic Instructions ............................................................................................................................... 3-49
Logical Instructions .................................................................................................................................... 3-50
Compare Instructions ................................................................................................................................ 3-50
Branch Instructions .................................................................................................................................... 3-51
CR Logical Instructions ......................................................................................................................... 3-51
Rotate Instructions ................................................................................................................................ 3-51
Shift Instructions ................................................................................................................................... 3-52
Cache Management Instructions .......................................................................................................... 3-52
Interrupt Control Instructions ..................................................................................................................... 3-52
TLB Management Instructions .................................................................................................................. 3-53
Processor Management Instructions ..........................................................;.............................................. 3-53
Extended Mnemonics ................................................................................................................................ 3-53
Chapter 4. Cache Operations ................................................................................................ 4-1
ICU Organization ............................................................................................................................................ 4-2
ICU Operations ............................................................................................................................................ 4-3
Instruction Cachability Control ..................................................................................................................... 4-4
Instruction Cache Synonyms ....................................................................................................................... 4-4
ICU Coherency ............................................................................................................................................. 4-5
DCU Organization ............................................................................................................................................ 4-5
DCU Operations .......................................................................................................................................... 4-6
DCU Write Strategies .................................................................................................................................. 4-7
DCU Load and Store Strategies .................................................................................................................. 4-7
Data Cachability Control .............................................................................................................................. 4-8
DCU Coherency .......................................................................................................................................... 4-9
Cache Instructions ........................................................................................................................................... 4-9
ICU Instructions ........................................................................................................................................... 4-9
DCU Instructions ....................................................................................................................................... 4-10
Cache Control and Debugging Features ....................................................................................................... 4-11
CCRO Programming Guidelines ................................................................................................................ 4-13
ICU Debugging .......................................................................................................................................... 4-14
Preliminary
Contents vii

DCU Debugging ........................................................................................................................................ 4-15
DCU Performance ......................................................................................................................................... 4-16
Pipeline Stalls ........................................................................................................................................... 4-16
Cache Operation Priorities ........................................................................................................................ 4-17
Simultaneous Cache Operations .............................................................................................................. 4-18
Sequential Cache Operations ................................................................................................................... 4-18
Chapter 5. On-Chip Memory .................................................................................................. 5-1
OCM Addressing ............................................................................................................................................. 5-1
OCM Programming Guidelines ........................................................................................................................ 5-2
Store Data Bypass Behavior and Memory Coherency.................................................................................... 5-3
Registers ......................................................................................................................................................... 5-5
OCM Instruction-Side Address Range Compare Register (OCMO_ISARC) ............................................... 5-5
OCM Instruction-Side Control Register (OCMO_ISCNTL) .......................................................................... 5-6
OCM Data-Side Address Range Compare Register (OCMO_DSARC) ...................................................... 5-6
OCM Data-Side Control Register (OCMO_DSCNTL) ................................................................................. 5-7
Chapter 6. Memory Management .......................................................................................... 6-1
MMU Overview ................................................................................................................................................ 6-1
Address Translation......................................................................................................................................... 6-1
Translation Lookaside Buffer (TLB) ................................................................................................................. 6-2
Unified TLB ................................................................................................................................................. 6-2
TLB Fields ................................................................................................................................................... 6-3
Page Identification Fields ....................................................................................................................... 6-3
Translation Field ..................................................................................................................................... 6-4
Access Control Fields............................................................................................................................. 6-5
Storage Attribute Fields .......................................................................................................................... 6-5
Shadow Instruction TLB .....................................................................................................................:......... 6-6
ITLB Accesses ....................................................................................................................................... 6-6
Shadow Data TLB ....................................................................................................................................... 6-7
DTLB Accesses ...................................................................................................................................... 6-7
Shadow TLB Consistency ...................................................................................................................... 6-8
TLB-Related Interrupts .................................................................................................................................... 6-9
Data Storage Interrupt
.~ .............................................................................................................................. 6-9
Instruction Storage Interrupt ..................................................................................................................... 6-1 °
Data TLB Miss Interrupt ............................................................................................................................ 6-10
Instruction TLB Miss Interrupt ................................................................................................................... 6-10
TLB Management .......................................................................................................................................... 6-1 °
TLB Search Instructions (tlbsxltlbsx.) ........................................................................:.............................. 6-11
TLB Read/Write Instructions (tJbre/tlbwe) ................................................................................................. 6-11
TLB Invalidate Instruction (tibia) ............................................................................................................... 6-11
TLB Sync Instruction (tlbsync) .................................................................................................................. 6-11
Recording Page References and Changes ...................................................................................................
6-11
Access Protection .......................................................................................................................................... 6-12
Access Protection Mechanisms
in the TLB ............................................................................................... 6-12
General Access Protection ................................................................................................................... 6-12
Execute Permissions ............................................................................................................................ 6-13
Write Permissions .......:........................................................................................................................ 6-13
Zone Protection .................................................................................................................................... 6-13
Access Protection for Cache Control Instructions ..................................................................................... 6-15
Access Protection for String Instructions .................................................................................................. 6-16
Real-mode Storage Attribute Control ............................................................................................................ 6-17
Storage Attribute Control Registers .......................................................................................................... 6-18
Data Cache Write-through Register (DCWR) ....................................................................................... 6-18
Data Cache Cachability Register (DCCR) ............................................................................................ 6-19
Instruction Cache Cachability Register (ICCR) .................................................................................... 6-19
Storage Guarded Register (SGR) ........................................................................................................ 6-19
viii PPC405GP User's Manual Preliminary

Storage User-defined 0 Register (SUOR) ............................................................................................. 6-19
Storage Little-Endian Register (SLER) ................................................................................................. 6-19
Part III. PPC405GP System Operations ............................................................................... 111-1
Chapter 7. Clocking ............................................................................................................... 7-1
PLL Overview ................................................................................................................................................... 7-1
Input Reference Clock (SysClk) ....................................................................................................................... 7-2
External Clock Strapping Setup ....................................................................................................................... 7-3
Sample Clock Ratios ........................................................................................................................................ 7-4
PCI Clocking .................................................................................................................................................... 7-7
PCI Clocks ................................................................................................................................................... 7-8
PCI Adapter Applications ............................................................................................................................ 7-8
Serial Port Clocking ......................................................................................................................................... 7-9
Clocking Registers ........................................................................................................................................... 7-9
PLL Mode Register (CPCO_PLLMR) ......................................................................................................... 7-10
Chip Control Register 0 (CPCO_CRO) ....................................................................................................... 7-11
Chapter 8. Reset and Initialization ........................................................................................ 8-1
Reset Signals ................................................................................................................................................... 8-1
Reset Types ..................................................................................................................................................... 8-1
Core Reset .................................................................................................................................................. 8-1
Chip Reset ................................................................................................................................................... 8-1
System Reset .............................................................................................................................................. 8-2
PCI Power Management Initiated Resets ........................................................................................................ 8-2
Processor Initiated Resets ............................................................................................................................... 8-2
Processor State After Reset ............................................................................................................................ 8-2
Processor Register Contents After Reset ........................................................................................................ 8-3
Machine State Register Contents after Reset ............................................................................................. 8-3
Contents of Special Purpose Registers after Reset .................................................................................... 8-4
OCR Contents after Reset ............................................................................................................................... 8-4
MMIO Register Contents After Reset .............................................................................................................. 8-8
PPC405GP Chip Initialization ........................................................................................................................ 8-12
OCM Initialization ...................................................................................................................................... 8-13
Initializing Instruction-Side OCM ........................................................................................................... 8-13
Initializing Data-Side OCM .................................................................................................................... 8-13
UIC Initialization ........................................................................................................................................ 8-14
UART
Initialization ..................................................................................................................................... 8-14
PPC405GP Initial Processor Sequencing .............................................:........................................................ 8-14
Initialization Requirements ............................................................................................................................. 8-15
Initialization Code Example ............................................................................................................................ 8-16
Chapter 9. Pin Strapping and Sharing ................................................................................. 9-1
Pin Strapping ................................................................................................................................................... 9-1
Chip Pin Strapping Register (CPCO_PSR) .................................................................................................. 9-1
Pin Sharing ...................................................................................................................................................... 9-3
Chapter 10. Interrupt Controller Operations ......................................................................10-1
UIC Overview ................................................................................................................................................. 10-1
UIC Features .................................................................................................................................................. 10-1
UIC Interrupt Assignments ....................................................................................................................:........ 10-1
Interrupt Programmability ............................................................................................................................... 10-3
UIC
Registers ................................................................................................................................................. 10-3
UIC
Status Register (UICO_SR) ................................................................................................................ 10-3
UIC
Enable Register (UICO_ER) ............................................................................................................... 10-6
UIC
Critical Register (UICO_CR) ............................................................................................................... 10-8
UIC
Polarity Register (UICO_PR) ............................................................................................................ 10-10
UIC
Trigger Register (UICO_TR) ............................................................................................................. 10-13
Preliminary
Contents
ix

UIC Masked Status Register (UICO_MSR) ............................................................................................. 10-16
UIC Vector Configuration Register (UICO_VCR) .................................................................................... 10-18
UIC Vector Register (UICO_VR) .............................................................................................................. 10-19
Using the Value in UICO_ VR as a Vector Address or Entry Table Lookup ........................................ 10-20
Vector Generation Scenarios ............................................................................................................. 10-20
Interrupt Handling in the Processor Core .................................................................................................... 10-22
Architectural Definitions and Behavior ......................................................................................................... 10-22
Behavior of the PPC405GP Implementation ............................................................................................... 10-23
Interrupt Handling Priorities ......................................................................................................................... 10-24
Critical and Noncritical Interrupts ................................................................................................................. 10-26
General Interrupt Handling Registers ........................................................................................................... 10-27
Machine State Register (MSR) ........................................ ~ ...................................................................... 10-28
Save/Restore
Registers 0 and 1 (SRRO-SRR1) .................................................................................... 10-29
Save/Restore Registers 2 and 3 (SRR2-SRR3) .. ....................................................... ... ........................ 10-30
Exception Vector Prefix Register (EVPR) .............................................................................................. 10-31
Exception Syndrome Register (ESR) ...................................................................................................... 10-31
Data Exception Address Register (DEAR) .............................................................................................. 10-34
Critical Input Interrupts ................................................................................................................................ 10-34
Machine Check Interrupts ............................................................................................................................ 10-35
Instruction Machine Check Handling ...................................................................................................... 10-35
Data Machine Check Handling ................................................................................................................ 10-36
Data
Storage Interrupt ................................................................................................................................. 10-36
Instruction Storage Interrupt .................................................................................:...................................... 10-38
External Interrupt ......................................................................................................................................... 10-38
External Interrupt Handling ..................................................................................................................... 10-39
Alignment Interrupt ...................................................................................................................................... 10-39
Program Interrupt ........................................................................................................................................ 10-40
System Call Interrupt ................................................................................................................................... 10-41
Programmable Interval Timer (PIT) Interrupt ............................................................................................... 10-41
Fixed Interval Timer (FIT) Interrupt............................................................................................ ........ .......... 10-42
Watchdog Timer Interrupt ... ............................................................ ..... ............ .... ........................... ...... ....... 10-43
Data TLB Miss Interrupt ............ ... .................................................................... .... ........................................ 10-43
Instruction TLB Miss Interrupt ...................................................................................................................... 10-44
Debug Interrupt ............................................................................................................................................ 10-44
Chapter 11. Timer Facilities ................................................................................................ 11-1
Time Base ..................................................................................................................................................... 11-2
Reading the Time Base .............. .... .......... .... .............................................. ..... ......................................... 11-3
Writing the Time Base ............................................................................................................................... 11-3
Programmable Interval Timer (PIT) ............................................................................................................... 11-4
Fixed Interval Timer (FIT) ......................................................................................................................... 11-5
Watchdog Timer ..... ... .... ..... .... .......................................................... .... .............. .... ....................................... 11-6
Timer Status Register (TSR) ................................ ... ...................................................................................... 11-8
Timer
Control Register (TCR) ....... ... .................... ....... .................................................................................... 11-9
Chapter 12. Debugging ........................................................................................................ 12-1
Development Tool Support ............................................................................................................................ 12-1
Debug Interfaces ........................................................................................................................................... 12-1
IEEE 1149.1 Test Access Port (JTAG Debug Port) ...................................................................................... 12-1
JTAG Connector .................. ..... .................... .... ......................................... .... .... ... ......................................... 12-2
JTAG Instructions ..................................................................................................................................... 12-3
JTAG Boundary Scan ............................................................................................................................... 12-3
JTAG Implementation ................................ ... ............. .... ........... .... ... ...................................................... ... 12-4
JTAG 10 Register (CPCO_JTAGID) .......................................................................................................... 12-4
Trace Port...................................................................................................................... .... .......... ... ............... 12-5
Debug Modes ................................................................................................................................................ 12-6
Internal Debug Mode ................................................................................................................................ 12-6
x PPC405GP User's Manual Preliminary

External Debug Mode ................................................................................................ .... ......................... ... 12-6
Debug Wait Mode ........ ...................................................................................... ........ ................................ 12-7
Real-time Trace Debug Mode .............................................. .... .................. .... ........................................... 12-7
Processor Control .... ............. ... .............................................................................................................. ... ..... 12-8
Processor Status..................... ... ........... ... .... .................................................................................................. 12-8
Debug Registers ............;................................................................................................................................ 12-8
Debug Control Registers ..................................... .... .................................................................................. 12-9
Debug Control Register ° (DBCRO) ...................................................................................................... 12-9
Debug Control Register1 (DBCR1) ..................................................................................................... 12-11
Debug Status Register (DBSR) .............................................................................................................. 12-12
Instruction Address Compare Registers (IAC1-IAC4) ............................................................................ 12-14
Data Address Compare Registers (DAC1-DAC2) ................................................................................ 12-14
Data Value Compare Registers (DVC1-DVC2) ...................................................................................... 12-15
Debug Events .......................................................................................................................................... 12-16
Instruction Complete Debug Event .......................................................................................................... 12-16
Branch Taken Debug Event .................................................................................................................... 12-17
Exception Taken Debug Event ................................................................................................................ 12-17
Trap Taken Debug Event ........................................................................................................................ 12-17
Unconditional Debug Event ...........................................................................................;......................... 12-17
lAC Debug Event ..................................................................................................................................... 12-17
lAC Exact Address Compare .............................................................................................................. 12-17
lAC Range Address Compare ............................................................................................................ 12-17
DAC Debug Event ................................................................................................................................... 12-18
DAC Exact Address Compare ............................................................................................................ 12-19
DAC Range Address Compare ........................................................................................................... 12-19
Data Address Compare (DAC) Applied to Cache Instructions ............................................................ 12-20
DAC Applied to String Instructions ...................................................................................................... 12-21
Data Value Compare Debug Event ......................................................................................................... 12-21
Imprecise Debug Event .....................................................;..................................................................... 12-23
Chapter 13. Clock and Power Management .......................................................................13-1
CPM Registers ............................................................................................................................................... 13-1
CPM Enable Register (CPCO_ER) ............................................................................................................ 13-3
CPM Force Register (CPCO_FR) .............................................................................................................. 13-3
CPM Status Register (CPCO_SR) ............................................................................................................. 13-3
Chapter 14. Decompression Controller Operation ........................................................... 14-1
Code Compression and Decompression ...................................................................... ... .............................. 14-1
Code Compression .................................................................................................................................... 14-1
Code Decompression ....................................................................................................................... ... ...... 14-2
Instruction Fetches to Compressed Pages ............................................................................................... 14-2
Instruction Fetches to Uncompressed Pages ............................................................................................ 14-3
Performance ..............:............................................................................................................................... 14-3
Decompression Controller Registers ........................................................... .... .............................................. 14-3
Index Table Origin Registers (DCPO_ITORO-DCPO_ITOR3) ................................................................... 14-4
Decompression Address Decode Definition Registers (DCPO_ADDRO-DCPO_ADDR1) ......................... 14-5
Decompression Configuration Register (DCPO_CFG) .............................................................................. 14-5
Decompression Controller ID Register (DCPO_ID) ................................................................................... 14-6 .
Decompression Controller Version Register (DCPO_ VER) ....................................................................... 14-6
Decompression Controller PLB Error Address Register (DCPO_PLBBEAR) ............................................. 14-7
Decompression Controller Bus Error Address Register (DCPO_MEMBEAR) ........................................... 14-7
Decompression Controller Error Status Register ° (DCPO_ESR) ............................................................. 14-7
Part IV. PPC405GP External Interfaces .............................................................................. IV-1
Chapter 15. SDRAM Controller ...........................................................................................15-1
Interface Signals ......................................................................................................................................... ... 15-1
Accessing SDRAM Registers .. ............................................................................................................ .... ... ... 15-2
Preliminary
Contents
xi

SDRAM Controller Configuration and Status ................................................................................................ 15-3
Memory Controller Configuration Register (SDRAMO_CFG) .................................................................... 15-3
Memory Controller Status (SDRAMO_STATUS) .....
... ............................................................................... 15-5
Memory Bank
0-3 Configuration (SDRAMO_BOCR-SDRAMO_B3CR) ............... ... ............... ... ................ 15-6
Page Management ..........................................................................................................................;.......... 15-7
Logical Address to Memory Address Mapping ....... ... ................................................................... ... ......... 15-8
SDRAM Timing Register (SDRAMO_TR) .................................................................................................. 15-9
Selected Timing Diagrams ...................................................................................................................... 15-10
Auto (CAS Before RAS) Refresh ............................................................................................................ 15-13
Refresh Timer Register (SDRAMO_RTR) ............................................................................................... 15-13
Error Checking and Correction (ECC) ......................................................................................................... 15-14
ECC Configuration Register (SDRAMO_ECCCFG) ................................................................................ 15-14
Correctable ECC Errors ......................................................................................................... ... .............. 15-15
Uncorrectable ECC Errors ...................................................................................................................... 15-15
Error Locking ........................................................................................................................................... 15-16
ECC Error Status Register (SDRAMO_ECCESR) .................................................................................. 15-16
Bus Error Address Register (SDRAMO_BEAR) ...................................................................................... 15-17
Bus Error Syndrome Register °(SDRAMO_BESRO) .............................................................................. 15-17
Bus Error Syndrome Register 1 (SDRAMO_BESR1) .............................................................................. 15-18
Self-Refresh ................................................................................................................................................. 15-19
Power Management .......................................................................,............................................................ 15-20
Sleep Mode Entry ............................................................................. ... ................................................... 15-20
Power Management Idle Timer (SDRAMO_PMIT) .................................................................................. 15-20
Sleep Mode Exit ...................................................................................................................................... 15-21
Chapter 16. External Bus Controller ..................................................................................16-1
Interface Signals ............................................................................................................................................ 16-1
Interfacing to Byte, Halfword and Word Devices ...................................................................................... 16-3
Multiplexed II0s .. ............................... .... ....................................... .... .......... .... ..... .... ....... ... ....................... 16-4
Driver Enables
.. ............ ... ......................................................................................................................... 16-4
Non-Burst Peripheral Bus Transactions ........................................................................................................ 16-5
Single Read Transfer .................................................................,..................... ,. ....................................... 16-6
Single Write Transfer ................................................................................................................................ 16-7
Burst Transactions .....................................................................................................................
,................ ... 16-8
Burst Read Transfer .................................................................................................................................. 16-9
Burst Write Transfer ................................................................................................................................ 16-10
Device-Paced Transfers .............................................................;................................................................ 16-11
Device-Paced Single Read Transfer ....................................................................................................... 16-12
Device-Paced Single Write Transfer ....................................................................................................... 16-13
Device-Paced Burst Read Transfer ........................................................................................................ 16-14
Device-Paced Burst Write Transfer ........................................................................................................ 16-15
External Bus Master Interface ..................................................................................................................... 16-17
Arbitration ................................................................................................................................................ 16-17
Transaction Overview ...................................................................................................................:......... 16-19
Single Read and Single Write Transfers ..................................... ... ......................................................... 16-19
Burst Read Transfer ................................................................................................................................ 16-20
Burst Write Transfer ................................................................................................................................ 16-21
External Master Error Interrupts...................... ... .................................................................................. ... 16-22
EBC Registers ............................................................................................................................................. 16-23
EBC Configuration Register (EBCO_CFG) ............................................................................................. 16-23
Peripheral Bank Configuration Registers (EBCO_BnCR) ............................................................:.......... 16-25
Peripheral Bank Access Parameters (EBCO_BnAP) ........................ ... ................................................... 16-26
Error Reporting
... ...................................................................................... ... ................................................ 16-29
Error Locking ...............................................:........................................................................................... 16-29
Peripheral Bus Error Address Register (EBCO_BEAR) .......................................................................... 16-29
Peripheral Bus Error Status Register °(EBCO_BESRO) ........................................................................ 16-30
xII PPC405GP User's Manual Preliminary

Peripheral Bus Error Status Register 1 (EBCO_BESR1) ......................................................................... 16-32
Chapter 17. PCllnterface .......... ~ .......................................................................................... 17-1
PCI Overview ................................................................................................................................................. 17-1
PCI Bridge Features .................................................................................................................................. 17-1
PCI Bridge Block Diagram ......................................................................................................................... 17-2
Byte Ordering ............................................................................................................................................ 17-2
Reference Information .............................................................................................................................. 17-3
PCI Bridge Functional Blocks ......................................................................................................................... 17-4
PLB-to-PCI Half-Bridge ............................................................................................................................. 17-4
PCI-to-PLB Half-Bridge ............................................................................................................................. 17-5
PCI Arbiter ................................................................................................................................................. 17-5
PCI Bridge Address Mapping ......................................................................................................................... 17-6
PLB-to-PCI Address Mapping ................................................................................................................... 17-6
PCI-to-PLB Address Mapping ................................................................................................................... 17-8
PCI Target Map Configuration ................................................................................................................... 17-9
PCI Bridge Transaction Handling ................................................................................................................. 17-10
PLB-to-PCI Transaction Handling ........................................................................................................... 17-10
PCI Master Commands ....................................................................................................................... 17-10
PLB Slave Read Handling .................................................................................................................. 17-12
Prefetching .......................................................................................................................................... 17-12
,PLB Slave Write Handling .................................................................................................................. 17-12
Aborted PLB Requests ....................................................................................................................... 17-13
Retried PCI Reads .............................................................................................................................. 17-13
PCI-to-PLB Transaction Handling ........................................................................................................... 17-13
PLB Master Commands ...................................................................................................................... 17-14
Handling of Reads from PCI Masters ................................................................................................. 17-15
Handling Writes from PCI Masters ...................................................................................................... 17-17
Miscellaneous ..................................................................................................................................... 17-17
Completion Ordering ............................................................................................................................... 17-18
PCI Producer-Consumer Model .......................................................................................................... 17-18
Collision Resolution ................................................................................................................................. 17-18
PCI Bridge Configuration Registers ............................................................................................................. 17-19
PCI Bridge Register Summary ................................................................................................................ 17-19
PCI Bridge Local Configuration Registers ............................................................................................... 17-21
PMM °Local Address Register (PCILO_PMMOLA) ............................................................................ 17-21
PMM °Mask/Attribute Register (PCILO_PMMOMA) ........................................................................... 17-22
PMM °PCI Low Address Register (PCILO_PMMOPCILA) ................................................................. 17-22
PMM °PCI High Address Register (PCILO_PMMOPCIHA) ................................................................ 17-23
PMM 1 Local Address Register (PCILO_PMM1 LA) ............................................................................ 17-23
PMM 1 Mask/Attribute Register (PCILO_PMM1 MA) .........:................................................................. 17-24
PMM 1 PCI Low Address Register (PCILO_PMM1 PCILA) ................................................................. 17-24
PMM 1 PCI High Address Register (PCILO_PMM1PCIHA) ................................................................ 17-25
PMM 2 Local Address Register (PCILO_PMM2LA) ............................................................................ 17-25
PMM 2 Mask/Attribute Register (PCILO_PMM2MA) ........................................................................... 17-25
PMM 2 PCI Low Address Register (PCILO_PMM2PCILA) ................................................................. 17-26
PMM 2 PCI High Address Register (PCILO_PMM2PCIHA) ................................................................ 17-27
PTM 1 Memory Size/Attribute Register (PCILO_PTM1 MS) ................................................................ 17-27
PTM 1 Local Address Register (PCILO_PTM1 LA) .............................................................................. 17-27
PTM 2 Memory Size/Attribute Register (PCILO_PTM2MS) ................................................................ 17-28
PTM 2 Local Address Register (PCILO_PTM2LA) .............................................................................. 17-28
PCI Configuration Registers .................................................................................................................... 17-29
PCI Configuration Address Register (PCICO_CFGADDR) ................................................................. 17-29
PCI Configuration Data Register (PCICO_CFGDATA) ....................................................................... 17-30
PCI Vendor ID Register (PCICO_VENDID) ......................................................................................... 17-31
PCI Device ID Register (PCICO_DEVID) ............................................................................................ 17-31
Preliminary Contents xiii

PCI Command Register (PCICO_CMD) ............................................................................................. 17-31
PCI Status Register (PCICO_STATUS) .............................................................................................. 17-33
PCI Revision 10 Register (PCICO_REVID) ......................................................................................... 17-34
PCI Class Register (PCICO_CLS) ...................................................................................................... 17-35
PCI Cache Line Size Register (PCICO_CACHELS) ........................................................................... 17-35
PCI Latency Timer Register (PCICO_LATTIM) .................................................................................. 17-36
PCI Header Type Register (PCICO_HDTYPE) ................................................................................... 17-36
PCI Built-In Self Test (BIST) Control Register (PCICO_BIST) ............................................................ 17-37
Unused PCI Base Address Register Space ....................................................................................... 17-37
PCI PTM 1 BAR (PCICO_PTM1BAR) ..................................................................................:............. 17-37
PCI PTM 2 BAR (PCICO_PTM2BAR) ................................................................................................ 17-38
PCI Subsystem Vendor 10 Register (PCICO_SBSYSVID) ................................................................. 17-39
PCI Subsystem 10 Register (PCICO_SBSYSID) ................................................................................ 17-39
PCI Capabilities Pointer (PCICO_CAP) .............................................................................................. 17-40
PCllnterrupt Line Register (PCICO_INTLN) ...................................................................................... 17-40
PCllnterrupt Pin Register (PCICO_INTPN) ........................................................................................ 17-41
PCI Minimum Grant Register (PCICO_MINGNT) ............................................................................... 17-41
PCI Maximum Latency Register (PCICO_MAXLTNCY) ..................................................................... 17-41
PCllnterrupt Control/Status Register (PCICO_ICS) ........................................................................... 17-42
Error Enable Register (PCICO_ERREN) ............................................................................................ 17-42
Error Status Register (PCICO_ERRSTS) ........................................................................................... 17-43
Bridge Options 1 Register (PCICO_BRDGOPT1) .............................................................................. 17-44
PLB Slave Error Syndrome Register °(PCICO_PLBBESRO) ............................................................ 17-45
PLB Slave Error Syndrome Register 1 (PCICO_PLBBESR1) ............................................................ 17-47
PLB Slave Error Address Register (PCICO_PLBBEAR) .................................................................... 17-48
Capability Identifier (PCICO_CAPID) .................................................................................................. 17-49
Next Item Pointer (PCICO_NEXTIPTR) .............................................................................................. 17-49
Power Management Capabilities (PCICO_PMC) ................................................................................ 17-50
Power Management Control/Status Register (PCICO_PMCSR) ........................................................ 17-50
PMCSR PCI-to-PCI Bridge Support Extensions (PCICO_PMCSRBSE) ............................................ 17-51
PCI Data Register (PCICO_DATA) ..................................................................................................... 17-52
Bridge Options 2 Register (PCICO_BRDGOPT2) .............................................................................. 17-52
Power Management State Change Request Register (PCICO_PMSCRR) ........................................ 17-54
Error Handling ............................................................................................................................................. 17-55
PLB Unsupported,Transfer Type ............................................................................................................ 17-55
PCI Master Abort .................................................................................................................................... 17-55
Bridge PCI Master Receives Target Abort While PCI Bus Master .......................................................... 17-56
PCI Target Data Bus Parity Error Detection ........................................................................................... 17-57
PCI Master Data Bus Parity Error Detection ........................................................................................... 17-57
PCI Address Bus Parity Error While PCI Target ..................................................................................... 17-58
PLB Master Bus Error Detection ............................................................................................................. 17-58
PCI Bridge Clocking Configuration .............................................................................................................. 17-59
PCI Power Management Interface .............................................................................................................. 17-59
Capabilities and Power Management Status and Control Registers ...................................................... 17-59
Power State Control ................................................................................................................................. 17-59
Changing Power States .......................................................................................................................... 17-60
PCI Bridge Reset and Initialization .............................................................................................................. 17-61
Address Map Initialization ....................................................................................................................... 17-61
Other Configuration Register Initialization .............................................................................................. 17-63
Target Bridge Initialization ...................................................................................................................... 17-63
Local Processor Boot from PCI Memory ................................................................................................. 17-64
Type °Configuration Cycles for Other Devices ...................................................................................... 17-64
Timing Diagrams ......................................................................................................................................... 17-64
PCI Timing Diagr9.m Descriptions ......................................................................................... ~ ................. 17-65
PCI Master Burst Read From SDRAM ............................................................................................... 17-65
PCI Master Burst Write To SDRAM ................................................................................................... 17-65
xlv
PPC405GP User's Manual Preliminary

CPU Read From PCI Memory Slave, Nonprefetching ........................................................................ 17-65
CPU Read From PCI Memory Slave, Prefetching .............................................................................. 17-65
CPU Write To PCI Memory Slave ....................................................................................................... 17-65
PCI Memory To SDRAM DMA Transfer ............................................................................................. 17-66
SDRAM
To PCI Memory DMA Transfer ............................................................................................. 17-66
Asynchronous .......................................................................................................................................... 17-66
Synchronous ........................................................................................................................................... 17-92
.Chapter 18. Direct Memory Access Controller ..................................................................18-1
External Interface Signals .............................................................................................................................. 18-1
Functional Overview ...................................................................................................................................... 18-2
Peripheral Mode Transfers .. ................................................................................... ... ................................ 18-2
Memory-to-Memory Transfers ................................................................................................................... 18-3
Scatter/GatherTransfers ........................................................................................................................... 18-4
Configuration and Status Registers ............................................................................................................... 18-4
DMA Polarity Configuration Register (DMAO_POL) .................................................................................. 18-5
DMA Sleep Mode Register (DMAO_SLP) .................................................................................................. 18-6
DMA Status Register (DMAO_SR)
.. ........................................................................... ... ............................ 18-7
DMA Channel Control Registers (DMAO_CRO-DMAO_CR3) ................................................................... 18-8
DMA Source Address Registers (DMAO_SAO-DMAO_SA3) ................................................................... 18-10
DMA Destination Address Registers (DMAO_DAO-DMAO_DA3) ............................................................ 18-11
DMA Count Registers (DMAO_CTO-DMAO_CT3) ................................................................................... 18-11
DMA Scatter/Gather Descriptor Address Registers (DMAO_SGO-DMAO_SG3) .................................... 18-12
DMA Scatter/Gather Command Register (DMAO_SGC) ......................................................................... 18-13
Channel Priorities......................... ... ............................................................................................................. 18-13
Data Parity During DMA Peripheral Transfers ............................................................................................. 18-14
Errors ........................................................................................................................................................... 18-14
Address Alignment Error
.. ....................................................................................................................... 18-14
PLB Timeout ............................................................................................................................................ 18-15
Slave Errors .. ........................................................................................................................................... 18-15
DMA Interrupts ............................................................................................................................................. 18-15
Scatter/GatherTransfers ............................................................................................................................. 18-16
Programming the DMA Controller ................................................................................................................ 18-17
Peripheral Mode Transfers .. ................................................................................... ... .............................. 18-17
Memory-to-Memory Transfers ................................................................................................................. 18-20
Software-Initiated Memory-to-Memory Transfers (Non-Deviced Paced) ................................................ 18-21
Chapter 19. Ethernet Media Access Controller ................................................................. 19-1
EMAC Features ............................................................................................................................................. 19-2
EMAC Operation ............................................................................................................................................ 19-3
MAL Slave Logic ....................................................................................................................................... 19-4
OPB Slave Logic ....................................................................................................................................... 19-4
Ethernet Address Match Logic .................................................................................................................. 19-4
Configuration and Status Registers........................................................................................................... 19-4
Wake On LAN Logic .................................................................................................................................. 19-4
Ethernet MAC
.. .......................................................................................................................................... 19-5
EMAC Loop-Back Modes .......................................................................................................................... 19-5
EMAC Transmit Operation .....................................
... ..................................................................................... 19-5
Arbitration Between
TX Channels .........................................................................................,................... 19-6
Independent Mode .................................................................................................................................... 19-6
Dependent Mode ....................................................................................................................................... 19-6
MAL TX Descriptor Control/Status Field ............................................................................................... 19-7
Early Packet Termination in Transmit ................................................................................................... 19-9
Empty Packets ...................................................................................................................................... 19-9
Automatic Retransmission of Collided Packets .................................................................................... 19-9
Inter-Packet Gap (IPG) Tuning ............................................................................................................. 19-9
Full-Duplex Operation .. ... ...................................................................................................................... 19-9
Preliminary Contents
xv

Packet Content Configuration Options ............................................................................................... 19-10
EMAC Receive Operation ............................................................................................................................ 19-12
EMAC -MAL RX Packet Transfer Flow ................................................................................................. 19-12
MAL RX Descriptor Status ....................................................................................................................... 19-12
Early Packet Termination
In Receive ...................................................................................................... 19-13
Discarding Packets During Receive ........................................................................................................ 19-14
WOL Support ..............................................................................................................................;........... 19-14
EMAC WOL Support .......................................................................................................................... 19-15
Flow Control ................................................................................................................................................ 19-15
MAC Control Packet ............................................................................................................................... 19-15
Control Packet Transmission .................................................................................................................. 19-16
Integrated Flow Control ........................................................................................................................... 19-16
Control Packet Reception
.. ..................................................................................................................... 19-17
VLAN Support .............................................................................................................................................. 19-18
VLAN Tagged Packet Transmission ....................................................................................................... 19-19
VLAN Tagged Packet Reception ............................................................................................................ 19-19
Address Match Mechanism ..................................................................................................................... 19-20
Non-WOL Mode ................................................................................................................................. 19-20
WOL Mode ......................................................................................................................................... 19-22
EMAC Registers ...........................................................................................:.............................................. 19-23
Mode Register °(EMACO_MRO) ............................................................................................................ 19-25
Mode Register 1 (EMACO_MR1) ............................................................................................................ 19-25
Transmit Mode Register °(EMACO_
TMRO) ........................................................................................... 19-27
Transmit Mode Register 1 (EMACO_TMR1) ........................................................................................... 19-28
Low-Priority Requests ........................................................................................................................ 19-28
Urgent-Priority Requests .................................................................................................................... 19-28
Receive Mode Register (EMACO_RMR) ................................................................................................. 19-29
Interrupt Status Register (EMACO_ISR) ................................................................................................. 19-30
Interrupt Status Enable Register (EMACO_ISER) ................................................................................... 19-33
Individual Address High (EMACO_IAHR) ................................................................................................ 19-35
Individual Address Low (EMACO_IALR) ................................................................................................. 19-36
VLAN TPID Register (EMACO_VTPID) ................................................................................................... 19-36
VLAN TCI Register (EMACO_VTCI) ....................................................................................................... 19-36
Pause Timer Register (EMACO_PTR) .................................................................................................... 19-37
Individual Address Hash Tables
1-4 (EMACO_IAHT1-EMACO_IAHT4) ................................................ 19-37
Group Address Hash Tables
1-4 (EMACO_GAHT1-EMACO_GAHT4) ................................................. 19-37
Last Source Address High (EMACO_LSAH) ........................................................................................... 19-38
Last Source Address Low (EMACO_LSAL) ............................................................................................ 19-38
Inter-Packet Gap Value Register (EMACO_IPGVR) ............................................................................... 19-38
STA Control Register (EMACO_STACR) ................................................................................................ 19-39
Transmit Request Threshold Register (EMACO_TRTR) ......................................................................... 19-40
Receive Low/High Water Mark Register (EMACO_RWMR) .................................................................... 19-41
Number of Octets Transmitted (EMACO_OCTX) ..................................................................................... 19-42
Number of Octets Received (EMACO_OCRX) ........................................................................................ 19-42
Mil Interface .................................................................................................................................................. 19-42
Mil Station Management Interface .......................................................................................................... 19-42
EMAC -Mil Interface .............................................................................................................................. 19-43
MAL-EMAC Packet Transfer Flow............................................................................................................ 19-43
Programming Notes..................................................................................................................................... 19-44
Power-Up and Initialization ..................................................................................................................... 19-44
Reset Options ..................................................................................................................................... 19-44
Scenario 1 .......................................................................................................................................... 19-45
Scenario 2 ......................................................................................................................................:
... 19-45
Scenario 3 .......................................................................................................................................... 19-46
xvi PPC405GP User's Manual Preliminary

Chapter 20. Memory Access Layer .................................................................................... 20-1
MAL Features ................................................................................................................................................ 20-1
MAL -Internal Structure ........................................................................................................................... 20-3
PLB Master ........................................................................................................................................... 20-3
OPB Master .......................................................................................................................................... 20-3
TX Channel Handler ............................................................................................................................. 20-3
RX Channel Handler ............................................................................................................................: 20-3
TX Channel Arbiter ............................................................................................................................... 20-4
RX Channel Arbiter ............................................................................................................................... 20-4
TX Common Channel Logic .................................................................................................................. 20-4
RX Common Channel Logic ................................................................................................................. 20-4
Register Map File .................................................................................................................................. 20-4
Transmit and Receive Operations ................................................................................................................. 20-4
Buffer Descriptor Overview ............................................................................................................................ 20-7
Transmit Software Interface ........................................................................................................................... 20-9
Wrapping the BD Table for Transmit ....................................................................................................... 20-10
Continuous Mode for Transmit ................................................................................................................ 20-10
Back Up a Packet for Transmit ................................................................................................................ 20-10
Descriptor Not Valid for Transmit ....................................................................................................:....... 20-11
Scroll Descriptors for Transmit ................................................................................................................ 20-11
Receive Software Interface .......................................................................................................................... 20-12
Wrapping the BD Table for Receive ........................................................................................................ 20-12
Continuous Mode for Receive ................................................................................................................. 20-12
Descriptor Not Valid for Receive ............................................................................................................. 20-13
Buffer Length for Receive ........................................................................................................................ 20-13
Descriptor Buffer Status/Control Fields ........................................................................................................ 20-13
Information from a Software Device Driver Directed To MAL and COMMAC ......................................... 20-13
Information from MAL and COMMAC Directed to Software .................................................................... 20-14
Status/Control Field Handling .................................................................................................................. 20-14
Status/Control Field Format .................................................................................................................... 20-14
TX Status/Control Field Format ............................................................................................................... 20-15
Bit 0 - R - Ready ................................................................................................................................ 20-15
Bit 1- W - Wrap ................................................................................................................................. 20-15
Bit 2 - CM -Continuous Mode ........................................................................................................... 20-15
Bit 3 - L - Last .................................................................................................................................... 20-15
Bit 4 - Reserved ...........:..................................................................................................................... 20-16
Bit 5 - I - Interrupt .............................................................................................................................. 20-16
Bits 6 to 15 .......................................................................................................................................... 20-16
RX Status/Control Field Format .............................................................................................................. 20-16
Bit 0 - E - Empty ................................................................................................................................ 20-16
Bit 1- W - Wrap ................................................................................................................................. 20-17
Bit 2 - CM -Continuous Mode ........................................................................................................... 20-17
Bit 3 - L - Last .................................................................................................................................... 20-17
Bit 4 - F - First ................................................................................................................................... 20-17
Bit 5 - I - Interrupt .............................................................................................................................. 20-17
Bits 6 to 15 .......................................................................................................................................... 20-17
MAL Programming Notes ............................................................................................................................. 20-18
MAL Initialization ..................................................................................................................................... 20-18
Interrupts ................................................................................................................................................. 20-18
Error Handling ......................................................................................................................................... 20-19
Error Detection .................................................................................................................................... 20-19
Indicated Errors .................................................................................................................................. 20-19
Error Handling Registers ..................................................................................................................... 20-20
Operational Error Modes .................................................................................................................... 20-21
Resolution of an Error Situation ........................................................................................................... 20-21
Interrupts To Software ........................................................................................................................ 20-23
Preliminary Contents xvii

MAL Registers ............................................................................................................................................. 20-24
MALConfiguration Register (MALO_CFG) ............................................................................................. 20-25
Channel Active Set and Reset Registers ................................................................................................ 20-26
End of Buffer Interrupt Status Registers
.. ........................................................................................... 20-28
Error Registers ............................................................................................................................................ 20-29
MAL Error Status Register (MALO_ESR) .................................
......... ...................................................... 20-29
MAL Interrupt Enable Register (MALO_IER) ........................................................................................... 20-31
Descriptor Error Interrupt Registers (MALO_TXDEIR, MALO_RXDEIR) ................................................. 20-32
Channel Table Pointer Registers (MALO_TXCTPxR, MALO_RXCTPOR) ............................................... 20-33
Chapter 21. Serial Port Operations .....................................................................................21-1
Functional Description .................................................................................................................................... 21-1
Serial Input Clocking ...................................................................................................................................... 21-2
UART Registers ............................................................................................................................................. 21-4
Receiver Buffer Registers (UARTx_RBR) ................................................................................................ 21-5
Transmitter Holding Registers (UARTx_THR) .......................................................................................... 21-5
Interrupt Enable Registers (UARTx_IER) ................................................................................................. 21-5
Interrupt Identification Registers (UARTx_IIR) .......................................................................................... 21-6
FIFO Control Registers (UARTx_FCR) ..................................................................................................... 21-7
Line Control Registers (UARTx_LCR) ...................................................................................................... 21-8
Modem Control Registers (UARTx_MCR) .............................................................................................. 21-10
Line Status Registers (UARTx_LSR) ...................................................................................................... 21-11
Modem Status Registers (UARTx_MSR) ................................................................................................ 21-13
Scratchpad Registers (UARTx_SCR) ..................................................................................................... 21-13
Divisor Latch LSB and MSB Registers (UARTx_DLL, UARTx_DLM) ..................................................... 21-14
FIFO Operation ............................................................................................................................................ 21-15
Interrupt Mode ......................................................................................................................................... 21-15
Receiver ............................................................................................................................................. 21-15
Transmitter ......................................................................................................................................... 21-16
Polled Mode ............................................................................................................................................ 21-16
UART and Sleep Mode ................................................................................................................................ 21-16
DMA Operation ............................................................................................................................................ 21-17
Chip Control Register 0 (CPCO_CRO) .................................................................................................... 21-17
Transmitter DMA Mode ........................................................................................................................... 21-18
Receiver DMA Mode ................................................................................................................................ 21-20
Chapter 22. IIC Bus Interface ......................................................................................... ~ ....22-1
Addressing ..................................................................................................................................................... 22-1
Addressing Modes .................................................................................................................................... 22-1
Seven-Bit Addresses ..........................................................................................................
... ................... 22-2
Ten-Bit Addresses .................................................................................................................................... 22-2
IIC Registers ................................................................................................................................................... 22-2
IIC Register Descriptions ............................................................................................................................... 22-3
IICO Master Data Buffer ............................................................................................................................ 22-3
IICO Slave Data Buffer .............................................................................................................................. 22-4
IICO Low Master Address Register ........................................................................................................... 22-5
IICO High Master Address Register .......................................................................................................... 22-6
IICO Control Register ................................................................................................................................ 22-6
IICO Mode Control Register ...................................................................................................................... 22-8
IICO Status Register ................................................................................................................................ 22-10
IICO Extended Status Register ................................................................................................................ 22-11
IICO Low Slave Address Register ........................................................................................................... 22-14
IICO High Slave Address Register .......................................................................................................... 22-14
IICO Clock Divide Register ....................................................................................................................... 22-15
IICO Interrupt Mask Register ................................................................................................................... 22-16
IICO Transfer Count Register .................................................................................................................. 22-17
IIca Extended Control and Slave Status Register ... ... ............................................................................ 22-18
xviii PPC405GP User's Manual Preliminary

IICO Direct Control Register .................................................................................................................... 22-20
Interrupt Handling ..................:..................................................................................................................... 22-21
General Considerations ............................................................................................................................... 22-22
Chapter 23. GPIO Operations .............................................................................................. 23-1
GPIO Controller Overview ............................................................................................................................. 23-1
Features ......................................................................................................................................................... 23-1
GPIO Interface Signals .................................................................................................................................. 23-2
External Macro Signals ............................................................................................................................. 23-2
External Module Signals ............................................................................................................................ 23-3
Clock and Power Management ...................................................................................................................... 23-4
GPIO Register Overview ................................................................................................................................ 23-5
GPIO Register Reset Values ...................................................................................................................... 23-5
Detailed Register Description ..................................................................................... ~ .............................. 23-5
GPIO Output Register (GPIOO_OR) ..................................................................................................... 23-5
GPIO Three-State Control Register (GPIOO_ TCR) .............................................................................. 23-5
GPIO Open Drain Register (GPIOO_ODR) ........................................................................................... 23-6
GPIO Input Register (GPIOO_IR) .......................................................................................................... 23-6
Part V. Reference .................................................................................................................. V-1
Chapter 24. Instruction Set ................................................................................................. 24-1
Instruction Set Portability ............................................................................................................................... 24-1
Instruction Formats ........................................................................................................................................ 24-2
Pseudocode ................................................................................................................................................... 24-2
Operator Precedence ................................................................................................................................ 24-5
Register Usage .............................................................................................................................................. 24-5
Alphabetical Instruction Listing ...................................................................................................................... 24-5
add ............................................................................................................................................................ 24-6
addc ........................................................................................................................................................... 24-7
adde ...................................................................................................................................................... .... 24-8
addi ............................................................................................................................................................ 24-9
addic ........................................................................................................................................................ 24-10
addic ........................................................................................................................................................ 24-11
addis ........................................................................................................................................................ 24-12
addme ..................................................................................................................................................... 24-13
addze ....................................................................................................................................................... 24-14
and .......................................................................................................................................................... 24-15
andc ......................................................................................................................................................... 24-16
andi. ......................................................................................................................................................... 24-17
andis ........................................................................................................................................................ 24-18
b .............................................................................................................................................................. 24-19
bc ............................................................................................................................................................. 24-20
bcctr '" ...................................................................................................................................................... 24-26
bclr ........................................................................................................................................................... 24-30
cmp .......................................................................................................................................................... 24-34
cmpi ......................................................................................................................................................... 24-35
cmpl ......................................................................................................................................................... 24-36
cmpli ., ...................................................................................................................................................... 24-37
cntlzw ...................................................................................................................................................... 24-38
crand ....................................................................................................................................................... 24-39
crandc ...................................................................................................................................................... 24-40
creqv ........................................................................................................................................................ 24-41
crnand ..................................................................................................................................................... 24-42
crnor ........................................................................................................................................................ 24-43
cror .......................................................................................................................................................... 24-44
Preliminary Contents xix