IBM PowerPC 405GP User manual

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PowerPC 405GP
Embedded Processor
User's Manual
Preliminary Volume 1
GK10-3118-03

Sixth Preliminary Edition (June 2000)
This edition of IBM PowerPC 405GP Embedded Processor User's Manual applies to the IBM PowerPCTM
405GP 32-bit embedded processor, until otherwise indicated in new versions or application notes.
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Preliminary

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Preliminary

Contents
Figures ..................................•................:...............................................................................xxix
Tables ......•..............................................................................................•..................................xli
About This Book .............................................................................................................:..... xlvii
Who Should Use This Book ......................................................................................... """"'"'''''''''''''''''''''''' xlvii
How to Use This Book .................................................................................................................................... xlvii
Conventions ................................................................................................................................................... xlviii
Part I. Introducing the PPC405GP Embedded Processor ................................................... 1-1
Chapter 1. Overview ............................................................................................................... 1-1
PPC405GP Features """'"'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' .......................................... 1-2
Bus and Peripheral Features ....................................................................................................................... 1-2
PowerPC Processor Core Features ............................................................................................................ 1-3
PowerPC Architecture .""""".""""""""" .. """"""." .. """".""".""""" ... """"""."" ....................................... 1-4
The PPC405GP as a PowerPC Implementation .............................................................................................. 1-5
RISC Processor Core Organization .................................................................................;............................... 1-5
Instruction and Data Cache Controllers ....................................................................................................... 1-5
Instruction Cache Unit ............................................................................................................................ 1-6
Data Cache Unit
.. """ .. """""" .. """"""".""."."".""."" ... """"""""."""" ............................................ 1-6
Memory Management Unit .......................................................................................................................... 1-6
Timer Facilities ............................................................................................................................................ 1-8
Debug .......................................................................................................................................................... 1-8
Development Tool Support """""'"'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' .......................... 1-8
Debug Modes
""""""".""""""""".""".""".".".""".""".""""" .. """""" ............................................. 1-9
Processor Core Interfaces ............................. ""'" ............................ """"'"'''''''''''''''' ................................ 1-9
Processor Local Bus ...................................................................................... "".""." .. """".""""""." ... 1-9
Device Control Register Bus ................................................................................................................... 1-9
Clock and Power Management ""'"'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' ........................ 1-9
JTAG ....................................................................................................................................................... 1-9
Interrupts .. """'"'''''''''' ......................................... """"" ........ "" .. " .. " .. ".. .............................................. 1-9
On-Chip Memory .................................................................................................................................... 1-9
Processor Core Programming Model ............................................................................................................... 1-9
Data Types ................................................................................................................................................ 1-10
Processor Core Register Set Summary .................................................................................................... 1-10
General Purpose Registers ................................................................................................................... 1-10
Special Purpose Registers ...................................... ""."... ................................................................... 1-10
Machine State Register ........................................................................................................................ 1-10
Condition Register
"""""'"'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' ......................................... 1-11
Device Control Registers .......... """""""""".".""."" .. ".""." ... ".""." .. "" ............................ """""""" 1-11
Memory-Mapped 1/0 Registers """""""""""""""'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' ....................... 1-11
Addressing Modes ..................................................................................................................................... 1-11
Chapter 2. On-Chip Buses ..................................................................................................... 2-1
Processor Local Bus ........................................................................................................................................ 2-1
PLB Features .............................................................................................................................................. 2-2
PLB Masters and Slaves ............................................................................................................................. 2-2
PLB Master Assignments ............................................................................................................................ 2-2
PLB Transfer Protocol """""""."""""."""""" ... """""." .. """."""" .. """"."""."" .................................... 2-3
Overlapped PLB Transfers .......................................................................................................................... 2-4
PLB Arbiter Registers """'"'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' ............................................. 2-5
PLB Arbiter Control Register (PLBO_ACR) ............................................................................................. 2-5
PLB Error Address Register (PLBO_BEAR) ............................................................................................ 2-5
Preliminary Contents v

PLB Error Status Register (PLBO_BESR) .............................................................................................. 2-6
PLB to OPB Bridge Registers ....................................................................................... ... ........................... 2-8
Bridge Error Address Register (POBO_BEAR) ....................................................................................... 2-8
Bridge Error Status Registers (POBO_BESRO-POBO_BESR1) ............................................................ 2-8
On-Chip Peripheral Bus ....................................................................................................................... 2-11
OPB Features ........................................................................................................................................... 2-11
OPB Master Assignments ......................................................................................................................... 2-12
OPB Arbiter Registers ............................................................................................................................... 2-12
OPB Arbiter Control Register (OPBAO_CR) ......................................................................................... 2-12
OPB Arbiter Priority Register (OPBAO_PR) ......................................................................................... 2-13
Part II. The PPC405GP RiSe Processor ............................................................................... 11-1
Chapter 3. Programming Model ............................................................................................3-1
User and Privileged Programming Models ...................................................................................................... 3-1
Memory Organization and Addressing ............................................................................................................ 3-1
Physical Address Map ............................................................................................. ... ................................ 3-2
Storage Attributes ....................................................................................................................................... 3-3
Registers .............................................
... ......................................................................................................... 3-3
General Purpose Registers (RO-R31) ......................................................................................................... 3-6
Special Purpose Registers.......................................................................................................................... 3-6
Count Register (CTR)
... ..................................................................................................... ... .................. 3-7
Link Register (LR) ................................................................................................................................. 3-8
Fixed Point Exception Register (XER) ...............
... ................................................................................. 3-8
Special Purpose Register General (SPRGO-SPRG7) ......................................................................... 3-11
Processor Version Register (PVR) ....................................................................................................... 3-12
Condition Register (CR) ............................................................................................................................ 3-12
CR Fields after Compare Instructions .................................................................................................. 3-13
The
CRO Field ...................................................................................................................................... 3-14
The Time Base .......................................................................................................................................... 3-15
Machine State Register (MSR) ................................................................................................................. 3-15
Device Control Registers .......................................................................................................................... 3-16
Directly Accessed DCRs ...................................................................................................................... 3-17
Indirectly Accessed DCRs .................................................................................................................... 3-19
Indirect Access of SDRAM Controller DCRs ............................................................................................ 3-19
Indirect Access of External Bus Controller DCRs ..................................................................................... 3-20
Indirect Access of Decompression Controller DCRs ................................................................................ 3-21
Memory-Mapped Input/Output Registers .................................................................................................. 3-22
Directly Accessed MMIO Registers ..................................................................................................... 3-22
Indirectly Accessed MMIO Registers ................................................................................................... 3-25
Data Types and Alignment ............................................................................................................................ 3-26
Alignment for Storage Reference and Cache Control Instructions ........................................................... 3-27
Alignment and Endian Operation .............................................................................................................. 3-27
Summary of Instructions Causing Alignment Exceptions ......................................................................... 3-28
Byte Ordering ............................................................................................................................................... 3-28
Structure Mapping Examples ........................................................................................
... ......................... 3-29
Big Endian Mapping ............................................................................................................................. 3-29
Little Endian Mapping ........................................................................................................................... 3-30
Support for Little Endian Byte Ordering .................................................................................................... 3-30
Endian (E) Storage Attribute ..................................................................................................
... ................ 3-30
Fetching Instructions from Little Endian Storage Regions ................................................................... 3-31
Accessing Data in Little Endian Storage Regions ................................................................................
3-31
PowerPC Byte-Reverse Instructions .................................................................................................... 3-32
Instruction Processing ................................................................................................................................... 3-33
Branch Processing ..............................................................................................
... ....................................... 3-34
Unconditional Branch Target Addressing Options .................................................................................... 3-34
Conditional Branch Target Addressing Options ........................................................................................ 3-35
vi PPC405GP User's Manual Preliminary

Conditional Branch Condition Register Testing ......................................................................................... 3-35
BO Field on Conditional Branches ............................................................................................................ 3-35
Branch Prediction ...................................................................................................................................... 3-36
Speculative Accesses .................................................................................................................................... 3-37
Speculative Accesses in the PPC405GP .................................................................................................. 3-37
Prefetch Distance Down an Unresolved Branch Path .......................................................................... 3-38
Prefetch of Branches to the CTR and Branches to the LR ................................................................... 3-38
Preventing Inappropriate Speculative Accesses ....................................................................................... 3-38
Fetching Past an Interrupt-Causing or Interrupt-Returning Instruction ................................................. 3-39
Fetching Past tw or twi Instructions ...................................................................................................... 3-39
Fetching Past an Unconditional Branch ................................................................................................ 3-40
Suggested Locations of Memory-Mapped Hardware ............................................................................ 3-40
Summary ................................................................................................................................................... 3-41
Privileged Mode Operation ............................................................................................................................ 3-41
MSR Bits and Exception Handling ............................................................................................................ 3-41
Privileged Instructions ............................................................................................................................... 3-42
Privileged SPRs ........................................................................................................................................ 3-42
Privileged DCRs ........................................................................................................................................ 3-43
Synchronization ............................................................................................................................................. 3-43
Context Synchronization ........................................................................................................................... 3-44
Executio!,,! Synchronization ........................................................................................................................ 3-46
Storage Synchronization ........................................................................................................................... 3-46
Instruction Set ................................................................................................................................................ 3-47
Instructions Specific to IBM PowerPC Embedded Processors ................................................................. 3-48
Storage Reference Instructions ................................................................................................................. 3-48
Arithmetic Instructions ............................................................................................................................... 3-49
Logical Instructions .................................................................................................................................... 3-50
Compare Instructions ................................................................................................................................ 3-50
Branch Instructions .................................................................................................................................... 3-51
CR Logical Instructions ......................................................................................................................... 3-51
Rotate Instructions ................................................................................................................................ 3-51
Shift Instructions ................................................................................................................................... 3-52
Cache Management Instructions .......................................................................................................... 3-52
Interrupt Control Instructions ..................................................................................................................... 3-52
TLB Management Instructions .................................................................................................................. 3-53
Processor Management Instructions ..........................................................;.............................................. 3-53
Extended Mnemonics ................................................................................................................................ 3-53
Chapter 4. Cache Operations ................................................................................................ 4-1
ICU Organization ............................................................................................................................................ 4-2
ICU Operations ............................................................................................................................................ 4-3
Instruction Cachability Control ..................................................................................................................... 4-4
Instruction Cache Synonyms ....................................................................................................................... 4-4
ICU Coherency ............................................................................................................................................. 4-5
DCU Organization ............................................................................................................................................ 4-5
DCU Operations .......................................................................................................................................... 4-6
DCU Write Strategies .................................................................................................................................. 4-7
DCU Load and Store Strategies .................................................................................................................. 4-7
Data Cachability Control .............................................................................................................................. 4-8
DCU Coherency .......................................................................................................................................... 4-9
Cache Instructions ........................................................................................................................................... 4-9
ICU Instructions ........................................................................................................................................... 4-9
DCU Instructions ....................................................................................................................................... 4-10
Cache Control and Debugging Features ....................................................................................................... 4-11
CCRO Programming Guidelines ................................................................................................................ 4-13
ICU Debugging .......................................................................................................................................... 4-14
Preliminary
Contents vii

DCU Debugging ........................................................................................................................................ 4-15
DCU Performance ......................................................................................................................................... 4-16
Pipeline Stalls ........................................................................................................................................... 4-16
Cache Operation Priorities ........................................................................................................................ 4-17
Simultaneous Cache Operations .............................................................................................................. 4-18
Sequential Cache Operations ................................................................................................................... 4-18
Chapter 5. On-Chip Memory .................................................................................................. 5-1
OCM Addressing ............................................................................................................................................. 5-1
OCM Programming Guidelines ........................................................................................................................ 5-2
Store Data Bypass Behavior and Memory Coherency.................................................................................... 5-3
Registers ......................................................................................................................................................... 5-5
OCM Instruction-Side Address Range Compare Register (OCMO_ISARC) ............................................... 5-5
OCM Instruction-Side Control Register (OCMO_ISCNTL) .......................................................................... 5-6
OCM Data-Side Address Range Compare Register (OCMO_DSARC) ...................................................... 5-6
OCM Data-Side Control Register (OCMO_DSCNTL) ................................................................................. 5-7
Chapter 6. Memory Management .......................................................................................... 6-1
MMU Overview ................................................................................................................................................ 6-1
Address Translation......................................................................................................................................... 6-1
Translation Lookaside Buffer (TLB) ................................................................................................................. 6-2
Unified TLB ................................................................................................................................................. 6-2
TLB Fields ................................................................................................................................................... 6-3
Page Identification Fields ....................................................................................................................... 6-3
Translation Field ..................................................................................................................................... 6-4
Access Control Fields............................................................................................................................. 6-5
Storage Attribute Fields .......................................................................................................................... 6-5
Shadow Instruction TLB .....................................................................................................................:......... 6-6
ITLB Accesses ....................................................................................................................................... 6-6
Shadow Data TLB ....................................................................................................................................... 6-7
DTLB Accesses ...................................................................................................................................... 6-7
Shadow TLB Consistency ...................................................................................................................... 6-8
TLB-Related Interrupts .................................................................................................................................... 6-9
Data Storage Interrupt
.~ .............................................................................................................................. 6-9
Instruction Storage Interrupt ..................................................................................................................... 6-1 °
Data TLB Miss Interrupt ............................................................................................................................ 6-10
Instruction TLB Miss Interrupt ................................................................................................................... 6-10
TLB Management .......................................................................................................................................... 6-1 °
TLB Search Instructions (tlbsxltlbsx.) ........................................................................:.............................. 6-11
TLB Read/Write Instructions (tJbre/tlbwe) ................................................................................................. 6-11
TLB Invalidate Instruction (tibia) ............................................................................................................... 6-11
TLB Sync Instruction (tlbsync) .................................................................................................................. 6-11
Recording Page References and Changes ...................................................................................................
6-11
Access Protection .......................................................................................................................................... 6-12
Access Protection Mechanisms
in the TLB ............................................................................................... 6-12
General Access Protection ................................................................................................................... 6-12
Execute Permissions ............................................................................................................................ 6-13
Write Permissions .......:........................................................................................................................ 6-13
Zone Protection .................................................................................................................................... 6-13
Access Protection for Cache Control Instructions ..................................................................................... 6-15
Access Protection for String Instructions .................................................................................................. 6-16
Real-mode Storage Attribute Control ............................................................................................................ 6-17
Storage Attribute Control Registers .......................................................................................................... 6-18
Data Cache Write-through Register (DCWR) ....................................................................................... 6-18
Data Cache Cachability Register (DCCR) ............................................................................................ 6-19
Instruction Cache Cachability Register (ICCR) .................................................................................... 6-19
Storage Guarded Register (SGR) ........................................................................................................ 6-19
viii PPC405GP User's Manual Preliminary

Storage User-defined 0 Register (SUOR) ............................................................................................. 6-19
Storage Little-Endian Register (SLER) ................................................................................................. 6-19
Part III. PPC405GP System Operations ............................................................................... 111-1
Chapter 7. Clocking ............................................................................................................... 7-1
PLL Overview ................................................................................................................................................... 7-1
Input Reference Clock (SysClk) ....................................................................................................................... 7-2
External Clock Strapping Setup ....................................................................................................................... 7-3
Sample Clock Ratios ........................................................................................................................................ 7-4
PCI Clocking .................................................................................................................................................... 7-7
PCI Clocks ................................................................................................................................................... 7-8
PCI Adapter Applications ............................................................................................................................ 7-8
Serial Port Clocking ......................................................................................................................................... 7-9
Clocking Registers ........................................................................................................................................... 7-9
PLL Mode Register (CPCO_PLLMR) ......................................................................................................... 7-10
Chip Control Register 0 (CPCO_CRO) ....................................................................................................... 7-11
Chapter 8. Reset and Initialization ........................................................................................ 8-1
Reset Signals ................................................................................................................................................... 8-1
Reset Types ..................................................................................................................................................... 8-1
Core Reset .................................................................................................................................................. 8-1
Chip Reset ................................................................................................................................................... 8-1
System Reset .............................................................................................................................................. 8-2
PCI Power Management Initiated Resets ........................................................................................................ 8-2
Processor Initiated Resets ............................................................................................................................... 8-2
Processor State After Reset ............................................................................................................................ 8-2
Processor Register Contents After Reset ........................................................................................................ 8-3
Machine State Register Contents after Reset ............................................................................................. 8-3
Contents of Special Purpose Registers after Reset .................................................................................... 8-4
OCR Contents after Reset ............................................................................................................................... 8-4
MMIO Register Contents After Reset .............................................................................................................. 8-8
PPC405GP Chip Initialization ........................................................................................................................ 8-12
OCM Initialization ...................................................................................................................................... 8-13
Initializing Instruction-Side OCM ........................................................................................................... 8-13
Initializing Data-Side OCM .................................................................................................................... 8-13
UIC Initialization ........................................................................................................................................ 8-14
UART
Initialization ..................................................................................................................................... 8-14
PPC405GP Initial Processor Sequencing .............................................:........................................................ 8-14
Initialization Requirements ............................................................................................................................. 8-15
Initialization Code Example ............................................................................................................................ 8-16
Chapter 9. Pin Strapping and Sharing ................................................................................. 9-1
Pin Strapping ................................................................................................................................................... 9-1
Chip Pin Strapping Register (CPCO_PSR) .................................................................................................. 9-1
Pin Sharing ...................................................................................................................................................... 9-3
Chapter 10. Interrupt Controller Operations ......................................................................10-1
UIC Overview ................................................................................................................................................. 10-1
UIC Features .................................................................................................................................................. 10-1
UIC Interrupt Assignments ....................................................................................................................:........ 10-1
Interrupt Programmability ............................................................................................................................... 10-3
UIC
Registers ................................................................................................................................................. 10-3
UIC
Status Register (UICO_SR) ................................................................................................................ 10-3
UIC
Enable Register (UICO_ER) ............................................................................................................... 10-6
UIC
Critical Register (UICO_CR) ............................................................................................................... 10-8
UIC
Polarity Register (UICO_PR) ............................................................................................................ 10-10
UIC
Trigger Register (UICO_TR) ............................................................................................................. 10-13
Preliminary
Contents
ix