Acromag AcroPack Series User manual

AcroPack Series AP560A
Four Channel CAN Module
USER’S MANUAL
ACROMAG INCORPORATED
30765 South Wixom Road
Wixom, MI 48393-2417 U.S.A.
Tel: [phone]
Email: [e-mail]
Copyright 2020, Acromag, Inc., Printed in the USA.
Data and specifications are subject to change without notice.
8501173A

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Table of Contents
GENERAL INFORMATION 5
Intended Audience .................................................................................................................................. 5
Preface..................................................................................................................................................... 5
Trademark, Trade Name and Copyright Information 5
Radio Frequency Interference Statement.......................................................................................... 5
Environmental Protection Statement 5
AP560A OVERVIEW.................................................................................................................................. 5
Ordering Information .............................................................................................................................. 6
KEY FEATURES.......................................................................................................................................... 6
AcroPack Module Interface Features ...................................................................................................... 7
Signal Interface Products......................................................................................................................... 7
Software Support..................................................................................................................................... 7
Windows7
VxWorks7
Linux8
1. PREPARATION FOR USE 9
UNPACKING AND INSPECTION ................................................................................................................ 9
Installation Considerations...................................................................................................................... 9
CONNECTORS ........................................................................................................................................ 10
Field I/O Connector P2 10
Logic Interface Connector 15
2. PROGRAMMING INFORMATION 17
PCIe Configuration Address Space ........................................................................................................ 17
Configuration Registers ......................................................................................................................... 17
MEMORY MAP....................................................................................................................................... 18
CAN Registers 19
Channel Busy Register, (Read) - (Base + 08H) 19
Channel x Command Register, (Read/Write) - (BAR0 + Chan X base + 00H) 20
Channel x Control Register, (Read/Write) - (BAR0 + Chan X base + 04H) 20
Channel x Output Message Registers, (Read/Write) - (BAR0 + Chan X base + 10H thru 1CH) 21
Channel x Input Message Registers, (Read/Write) - (BAR0 + Chan X base + 20H thru 2CH) 21
Interrupt Controller 21
Interrupt Status Register 22
Interrupt Pending Register 23
Interrupt Enable Register 23
Interrupt Acknowledge Register 24
Set Interrupt Enable Register 24
Clear Interrupt Enable Register 25
Interrupt Vector Register 25
Master Enable Register 25
AXI XADC Analog to Digital Converter (System Monitor) 26

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Firmware Revision Register 27
Location in System Register 27
HI-3111 MODES OF OPERATION ........................................................................................................... 28
Initialization Mode 28
Normal Mode 28
Loopback Mode 28
Monitor Mode 28
Sleep Mode 29
CAN PROTOCOL OVERVIEW................................................................................................................... 29
BIT ENCODING ....................................................................................................................................... 29
Message Frames.................................................................................................................................... 30
Standard Data Frame 30
Extended Data Frame 33
Remote Frame 35
Error Frame 37
Overload Frame 39
BIT WISE ARBITRATION.......................................................................................................................... 40
BIT TIMING............................................................................................................................................. 42
Synchronization Segment (Sync Seg) 42
Propagation Time Segment (Prog Seg) 42
Phase Buffer Segment 1 and Phase Buffer Segment 2 (Phase Seg1 and Phase Seg2) .......................... 43
Sample Point 43
Phase Errors (e) 44
Synchronization ..................................................................................................................................... 44
Examples................................................................................................................................................ 44
REGISTERS.............................................................................................................................................. 45
Power-On-Reset .................................................................................................................................... 46
HI-3111 CAN Controller Registers ......................................................................................................... 46
Control Register 0 46
Control Register 1 48
BIT Timing Register 0 49
BIT Timing Register 1 50
Transmit Error Counter Register 51
Receive Error Counter Register 51
Message Status Register 52
Error Register 53
Interrupt Flag Register 54
Interrupt Enable Register 55

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Status Flag Register 56
Free Running Timer 57
Command Summary 57
HI-3111 Transmit Buffer ........................................................................................................................ 59
MESSAGE TRANSMISSION SEQUENCE 59
LOADING THE TRANSMIT FIFO 60
Transmit History FIFO 60
Single Frame Transmission 61
HI-3111 Receive Buffers and Frame Acceptance Filters........................................................................ 63
Receive Buffers 63
Filter and Mask ID Format 63
Reading the Receive Buffers 63
Programming Interrupts 67
Interrupt Programming Example 67
General Sequence of Events for Processing an Interrupt 67
3. THEORY OF OPERATION 69
CAN BUS PHYSICAL CONNECTION 69
CARRIER INTERFACE 69
PCIe INTERFACE LOGIC 69
AP560A CONTROL LOGIC 69
CAN Transceiver 69
4. SERVICE AND REPAIR 70
SERVICE AND REPAIR ASSISTANCE ........................................................................................................ 70
PRELIMINARY SERVICE PROCEDURE...................................................................................................... 70
WHERE TO GET HELP 70
5. SPECIFICATIONS 71
PHYSICAL................................................................................................................................................ 71
POWER................................................................................................................................................... 71
ENVIRONMENTAL .................................................................................................................................. 71
EMC Compliance 71
Vibration and Shock Standard 71
Reliability Prediction.............................................................................................................................. 72
PCIe Bus Specifications.......................................................................................................................... 72
Table 42 PCIe Bus Data Rates 73
6. APPENDIX 74
AP-CC-01 Heatsink Kit Installation......................................................................................................... 74
7. CERTIFICATE OF VOLATILITY 77
8. REVISION HISTORY 78

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GENERAL INFORMATION
Intended Audience
This users’ manual was written for technically qualified personnel who will be
working with I/O devices using the AcroPack module.
Preface
The information contained in this manual is subject to change without notice,
and Acromag, Inc. (Acromag) does not guarantee its accuracy. Acromag
makes no warranty of any kind with regard to this material, including, but not
limited to, the implied warranties of merchantability and fitness for a
particular purpose. Further, Acromag assumes no responsibility for any errors
that may appear in this manual and makes no commitment to update, or keep
current, the information contained in this manual. No part of this manual may
be copied or reproduced in any form, without the prior written consent of
Acromag.
Trademark, Trade Name and Copyright Information
© 2018 by Acromag Incorporated.
All rights reserved. Acromag and Xembedded are registered trademarks of
Acromag Incorporated. All other trademarks, registered trademarks, trade
names, and service marks are the property of their respective owners.
Radio Frequency Interference Statement
This is a Class A product. In a domestic environment, this product may cause
radio interference, in which case the user may find it necessary to take
adequate corrective measures.
Environmental Protection Statement
This product has been manufactured to satisfy environmental protection
requirements where possible. Many components used (structural parts,
circuit boards, connectors, etc.) are capable of being recycled. Final
disposition of this product after its service life must be conducted in
accordance with applicable country, state, or local laws or regulations.
AP560A OVERVIEW
The AcroPack Series AP560A provides four isolated CAN version 2.0B channels
capable of 1Mb/s bit rate. The AP560A can be configured to support ARINC
825 and CANaerospace standards.

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Ordering Information
The AcroPack ordering options are given in the following table:
Model
Operating Temperature Range
AP560AE-ISO-LF1
-40 to +71C
1. Applications requiring operating temperatures of 65°C to 71°C will require
purchase of AP-CC-01 AcroPack Conduction Cool Kit (See APPENDIX for
installation instructions) with a minimum airflow of 400LFM. For temperatures
below 65°C the module will require a minimum airflow of 200LFM.
Mini-
PCIe
x1 PCIe
FPGA
Field
I/O
FLASH
CAN
transceiver
CAN
controller
CAN
transceiver
CAN
controller
CAN
transceiver
CAN
controller
CAN
transceiver
CAN
controller
Figure 1 AP560A Block Diagram
KEY FEATURES
•4 isolated CAN channels.
•Implements CAN version 2.0B with programmable bit rate up to
1Mbit/sec. ISO 11898-5 compliant.
•Configurable to support ARINC 825 and CANaerospace Standards.
•Standard, Extended and Remote frames supported.
•8 maskable identifier filters.
•Filtering on ID and first two data bytes for both Standard and
Extended Identifiers.
•Monitor (Listen-only) mode.
•8-messageTransmit and Receive FIFOs.

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•Internal 16-bit free running counter for time tagging of transmitted or
received messages.
•Re-transmission disable capability.
AcroPack Module Interface Features
Field Connections –All CAN signal connections are made through a single
100-pin board stacking connector. An AcroPack carrier board will provide the
connection between the AcroPack module and the field cabling.
PCIe Bus –This AP module includes a PCI Express Generation 1 interface
operating at a speed of 2.5 Gbps with one lane in each direction.
Compatibility –– PCI Express Base Specification v2.1 compliant PCI Express
Endpoint.
Signal Interface Products
This AcroPack module will mate directly to all Acromag AcroPack carriers.
Once installed on the carrier, the module is accessed via a front panel
connector. The following cable is available for AcroPack carriers with the 68-
pin CHAMP connector:
Model 5028-609 adapter cable, 7 inches, 68-pin CHAMP 0.8mm to four
separate 9-pin D-SUB male connectors
Software Support
The AcroPack series products require support drivers specific to your
operating system. Supported operating systems include: Linux, Windows, and
VxWorks
Windows
Acromag provides software products (sold separately) to facilitate the
development of Windowsapplications interfacing with AcroPack modules.
This software (model APSW-API-WIN) consists of low-level drivers and
Dynamic Link Libraries (DLLs) that are compatible with a number of
programming environments. The DLL functions provide a high-level interface
to boards eliminating the need to perform low-level reads/writes of registers,
and the writing of interrupt handlers.
VxWorks
Acromag provides a software product (sold separately) consisting of
VxWorkssoftware. This software (Model APSW-API-VXW) is composed of
VxWorks(real time operating system) libraries for all AcroPack modules,
VPX I/O board products, and PCIe I/O Cards. The software is implemented as a

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library of “C” functions which link with existing user code to make possible
simple control of all Acromag AcroPack modules.
Linux
Acromag provides a software product consisting of Linuxsoftware. This
software (Model APSW-API-LNX) is composed of Linuxlibraries for all
AcroPack modules, VPX I/O board products, and PCIe I/O Cards. The software
is implemented as a library of “C” functions which link with existing user code
to make possible simple control of all Acromag AcroPack modules.

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1. PREPARATION FOR USE
IMPORTANT PERSONAL AND PRODUCT SAFETY CONSIDERATIONS
It is very important for the user to consider the possible safety implications of
power, wiring, component, sensor, or software failures in designing any type
of control or monitoring system. This is especially important where personal
injury or the loss of economic property or human life is possible. It is
important that the user employ satisfactory overall system design. It is
understood and agreed by the Buyer and Acromag that this is the Buyer's
responsibility.
WARNING: This board utilizes static sensitive components and should only
be handled at a static-safe workstation. This product is an electrostatic
sensitive device and is packaged accordingly. Do not open or handle this
product except at an electrostatic-free workstation. Additionally, do not ship
or store this product near strong electrostatic, electromagnetic, magnetic, or
radioactive fields unless the device is contained within its original
manufacturer’s packaging. Be aware that failure to comply with these
guidelines will void the Acromag Limited Warranty.
UNPACKING AND INSPECTION
Upon receipt of this product, inspect the shipping carton for evidence of
mishandling during transit. If the shipping carton is badly damaged or water
stained, request that the carrier's agent be present when the carton is
opened. If the carrier's agent is absent when the carton is opened and the
contents of the carton are damaged, keep the carton and packing material for
the agent's inspection.
For repairs to a product damaged in shipment, refer to the Acromag Service
Policy to obtain return instructions. It is suggested that salvageable shipping
cartons and packing material be saved for future use in the event the product
must be shipped.
This board is physically protected with packing material and electrically
protected with an anti-static bag during shipment. However, it is
recommended that the board be visually inspected for evidence of
mishandling prior to applying power.
The board utilizes static sensitive components and should only be handled at
a static-safe workstation.
Installation Considerations
Refer to the specifications for loading and power requirements. Be sure that
the system power supplies can accommodate the power requirements of the
carrier board, plus the installed AcroPack modules, within the voltage
tolerances specified.

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IMPORTANT: Adequate air circulation must be provided to prevent a temperature rise above the maximum
operating temperature.
The dense packing of the AcroPack module to the carrier/CPU board restricts
air flow within the card cage and is cause for concern. Adequate air circulation
must be provided to prevent a temperature rise above the maximum
operating temperature and to prolong the life of the electronics. If the
installation is in an industrial environment and the board is exposed to
environmental air, careful consideration should be given to air-filtering.
In a conduction cooled assembly, adequate thermal conduction must be
provided to prevent a temperature rise above the maximum operating
temperature.
CONNECTORS
Field I/O Connector P2
A field I/O interface connector provides a mating interface between the AP
modules and the carrier board. The 100 pin ST5-50-1.50-L-D-P-TR Samtec
connector is used on the AcroPack card as board to board interconnect. This
connector will mate with the 100 pin SS5-50-3.00-L-D-K-TR Samtec connector
on the carrier. The stack height is 4.5mm.
Pin assignments are unique to each AP model. Table 1 lists signal pin
assignments for the module field I/O connector. Pins are left unconnected to
meet the minimum creepage distance required for 60 Volt isolation. Front
panel connector P2 pin assignments are shown in Table 1.
Typically, the CAN bus is a twisted pair of wires with a characteristic
impedance of 120 ohms. Each end of the bus is terminated with 120 ohm
resistors in compliance with the standard to minimize signal reflections on the
bus. Alternatively, onboard termination resistors can be populated for low
speed or fault tolerant CAN applications. These resistors are not populated by
default.
Table 1 Field I/O Connector Pin Assignments
68 Pin
Champ
Carrier3
Connector
50 Pin
Champ
Carrier2
Connector2
Ribbon
Carrier
Connector1
Module
P2
Pin
Number
Field I/O Signal
1
1
1
2
CAN0H
35
26
2
1
CAN0L
4
Reserved/isolation
3
Reserved/isolation
2
2
3
6
Reserved/isolation

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68 Pin
Champ
Carrier3
Connector
50 Pin
Champ
Carrier2
Connector2
Ribbon
Carrier
Connector1
Module
P2
Pin
Number
Field I/O Signal
36
27
4
5
RTN0
8
Reserved/isolation
7
Reserved/isolation
3
3
5
10
Reserved/isolation
37
28
6
9
Reserved/isolation
12
Reserved/isolation
11
Reserved/isolation
4
4
7
14
Reserved/isolation
38
29
8
13
Reserved/isolation
16
Reserved/isolation
15
Reserved/isolation
5
5
9
18
Reserved/isolation
39
30
10
17
Reserved/isolation
20
Reserved/isolation
19
Reserved/isolation
6
6
11
22
Reserved/isolation
40
31
12
21
Reserved/isolation
24
Reserved/isolation
23
Reserved/isolation
7
7
13
26
Reserved/isolation
41
32
14
25
Reserved/isolation
28
Reserved/isolation
27
Reserved/isolation
8
8
15
30
Reserved/isolation
42
33
16
29
Reserved/isolation
32
Reserved/isolation
31
Reserved/isolation
9
9
17
34
CAN1H
43
34
18
33
CAN1L
36
Reserved/isolation

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68 Pin
Champ
Carrier3
Connector
50 Pin
Champ
Carrier2
Connector2
Ribbon
Carrier
Connector1
Module
P2
Pin
Number
Field I/O Signal
35
Reserved/isolation
10
10
19
38
Reserved/isolation
44
35
20
37
RTN1
40
Reserved/isolation
39
Reserved/isolation
11
11
21
42
Reserved/isolation
45
36
22
41
Reserved/isolation
44
Reserved/isolation
43
Reserved/isolation
12
12
23
46
Reserved/isolation
46
37
24
45
Reserved/isolation
48
Reserved/isolation
47
Reserved/isolation
13
13
25
50
Reserved/isolation
47
38
26
49
Reserved/isolation
52
Reserved/isolation
51
Reserved/isolation
14
14
27
54
Reserved/isolation
48
39
28
53
Reserved/isolation
56
Reserved/isolation
55
Reserved/isolation
15
15
29
58
Reserved/isolation
49
40
30
57
Reserved/isolation
60
Reserved/isolation
59
Reserved/isolation
16
16
31
62
Reserved/isolation
50
41
32
61
Reserved/isolation
64
Reserved/isolation
63
Reserved/isolation
17
17
33
66
CAN2H

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68 Pin
Champ
Carrier3
Connector
50 Pin
Champ
Carrier2
Connector2
Ribbon
Carrier
Connector1
Module
P2
Pin
Number
Field I/O Signal
51
42
34
65
CAN2L
68
Reserved/isolation
67
Reserved/isolation
18
18
35
70
Reserved/isolation
52
43
36
69
RTN2
72
Reserved/isolation
71
Reserved/isolation
19
19
37
74
Reserved/isolation
53
44
38
73
Reserved/isolation
76
Reserved/isolation
75
Reserved/isolation
20
20
39
78
Reserved/isolation
54
45
40
77
Reserved/isolation
80
Reserved/isolation
79
Reserved/isolation
21
21
41
82
Reserved/isolation
55
46
42
81
Reserved/isolation
82
Reserved/isolation
83
Reserved/isolation
22
22
43
86
Reserved/isolation
56
47
44
85
Reserved/isolation
88
Reserved/isolation
87
Reserved/isolation
23
23
45
90
Reserved/isolation
57
48
46
89
Reserved/isolation
92
Reserved/isolation
91
Reserved/isolation
24
24
47
94
CAN3H
58
49
48
93
CAN3L
96
Reserved/isolation

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68 Pin
Champ
Carrier3
Connector
50 Pin
Champ
Carrier2
Connector2
Ribbon
Carrier
Connector1
Module
P2
Pin
Number
Field I/O Signal
95
Reserved/isolation
25
25
49
98
Reserved/isolation
59
50
50
97
RTN3
100
Reserved/isolation
99
Reserved/isolation
Note:
1. VPX4500-CC-LF is an example of a carrier that uses the ribbon cable connector.
See image of carrier.
2. APCe7020E-LF is an example of a carrier that uses the 50-pin Champ connector.
See image of carrier.
3. The APCe7040E-LF is an example of a carrier that uses the 68-pin Champ
connector. See image of carrier below. On these carriers, pins 26 thru 34 and 60
thru 68 are not connected.

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Logic Interface Connector
The AP module logic edge connector interfaces to the mating connector on
the carrier board. The pin assignments of this connector are standard for all
AP modules according to the PCI Express MINI Card Electromechanical
Specification, REV 1.2 (with exceptions shown in Table 2 and noted below).
Power supplies +5, +12, and -12 Volt have been assigned to pins that are
reserved in the mini-PCIe specification. The ‘Present’ signal is grounded on
the AP module. In addition, COEX1, COEX2 –wireless transmitter control
signals are reassigned to JTAG signals TMS and TCK. Lastly, UIM_C4, UIM_C8 –
reserved User Identity Module signals are reassigned to JTAG signals TDI and
TDO.
Table 2 Logic Interface Connections
Pin #
Name
Pin #
Name
51
+5V2
52
+3.3V3
49
+12V2
50
GND
47
-12V2
48
N.C. (+1.5V)1
45
Present4
46
N.C. (LED_WPAN#)1
43
GND
44
N.C. (LED_WLAN#)1
41
+3.3V3
42
N.C. (LED_WWAN#)1
39
+3.3V3
40
GND
37
GND
38
N.C. (USB_D+)1
35
GND
36
N.C. (USB_D-)1
33
PETp0
34
GND
31
PETn0
32
SMB_DATA5
29
GND
30
SMB_CLK5
27
GND
28
N.C. (+1.5V)1
25
PERp0
26
GND
23
PERn0
24
+3.3V3

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Pin #
Name
Pin #
Name
21
GND
22
PERST#
19
TDI (UIM_C4)1
20
N.C. (W_DISABLE#)1
17
TDO (UIM_C8)1
18
GND
15
GND
16
N.C. (UIM_VPP)1
13
RECLK+
14
N.C. (UIM_RESET)1
11
REFCLK-
12
N.C (UIM_CLK)1
9
GND
10
N.C. (UIM_DATA)1
7
CLKREQ#1
8
N.C. (UIM_PWR)1
5
TCK (COEX2)1
6
N.C. (+1.5V)1
3
TMS (COEX1)1
4
GND
1
N.C. (WAKE#)1
2
+3.3V3
Note 1: Signals are not applicable for the AP560 implementation. Pins are
either “no connects” on the module or are repurposed for JTAG.
Note 2: +5V, +12V, and -12V power supplies have been assigned to pins that
are reserved in the mini-PCIe specification.
Note 3: All +3.3Vaux power pins are changed to +3.3V power.
Note 4: The ‘Present’ signal is tied to circuit common on the AP module.
Note 5: The SM Bus signals SMB_CLK and SMB_DATA are used to clock a
carrier location serial stream from the carrier. These signals are under the
control of the AcroPack module.

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2. PROGRAMMING INFORMATION
This Section provides the specific information necessary to program and
operate the AP560 module.
This Acromag AP560A is a PCI Express Base Specification, Revision
2.1compliant AcroPack module. The carrier/CPU connects a PCIe bus to the
AcroPack module.
The PCI bus is defined to address three distinct address spaces: I/O, memory,
and configuration space. The AcroPack module can be accessed via the PCIe
bus memory space and configuration spaces, only.
The AcroPack configuration registers are initialized by system software at
power-up to configure the card. The AP560A module is a Plug-and-Play PCIe
card. As a Plug-and-Play card the board’s base address and system interrupt
request line are not selected via jumpers but are assigned by system software
upon power-up via the configuration registers. A PCIe bus configuration
access is used to access an AcroPack’s configuration registers.
PCIe Configuration Address Space
When the computer is first powered-up, the computer’s system configuration
software scans the PCIe bus to determine what PCIe devices are present. The
software also determines the configuration requirements of the PCIe card.
The system software accesses the configuration registers to determine how
many blocks of memory space the module requires. It then programs the
board’s configuration registers with the unique memory address range
assigned.
The configuration registers are also used to indicate that the module requires
an interrupt request line. The system software then programs the
configuration registers with the interrupt request line assigned to the module.
Since this module is relocatable and not fixed in address space, this module’s
device driver must use the mapping information stored in the module’s
Configuration Space registers to determine where the module is mapped in
memory space and which interrupt line will be used.
Configuration Registers
The PCIe specification requires software driven initialization and configuration
via the Configuration Address space. This module provides 512 bytes of
configuration registers for this purpose. The AP560A contains the
configuration registers, shown in Table 3, to facilitate Plug-and-Play
compatibility.

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The Configuration Registers are accessed via the Configuration Address and
Data Ports. The most important Configuration Registers are the Base Address
Registers and the Interrupt Line Register which must be read to determine the
base address assigned to the AP560A and the interrupt request line that goes
active on an AP560A interrupt request.
Table 3 Configuration Registers
Reg.
Num.
D31 D24
D23 D16
D15 D8
D7 D0
0
Device ID=702C
Vendor ID= 16D5
1
Status
Command
2
Class Code=118000
Rev ID=00
3
BIST
Header
Latency
Cache
4
32-bit Memory Base Address for AP560A
32K-Byte Block (BAR0)
5 : 10
Not Used
11
Subsystem ID=702C
Subsystem Vendor ID=16D5
12
Not Used
13,14
Reserved
15
Max_Lat
Min_Gnt
Inter. Pin
Inter. Line
MEMORY MAP
This board is allocated a 32K byte block of memory that is addressable in the
PCIe bus memory space to control the acquisition of analog inputs from the
field. As such, three types of information are stored in the memory space:
control, status, and data.
The memory space address map for the AP560A is shown in Table 4. Note
that the base address for the AP560A in memory space must be added to the
addresses shown to properly access the AP560A registers.
Table 4 AP560A Memory Map
BAR0 Base Address
Size
Description
0x0000_0000→0x0000_0FFF
4K
CAN Registers
0x0000_1000→0x0000_1FFF
4K
Not Used
0x0000_2000→0x0000_2FFF
4K
Interrupt Controller
0x0000_3000→0x0000_3FFF
4K
XADC System Monitor

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BAR0 Base Address
Size
Description
0x0000_4000→0x0000_4FFF
4K
Firmware Revision
0x0000_5000→0x0000_5FFF
4K
Reserved
0x0000_6000→0x0000_6FFF
4K
Location in System
0x0000_7000→0x0000_7FFF
4K
Not Used
CAN Registers
The CAN Register memory space allows for control of the four independent
CAN registers. Table 5 shows the base address for each channel.
Table 5 CAN Channel Base Addresses
Description
Chan Base Addr+
Channel 0 Registers
100H
Channel 1 Registers
140H
Channel 2 Registers
180H
Channel 3 Registers
1C0H
Channel Busy Register, (Read) - (Base + 08H)
This read/write register is used to determine if the CAN controller is BUSY.
The function of each of the channel busy register bits are described in Table 6.
A power-up or system reset sets all interrupt register bits to 0.

AcroPack Series AP560 CAN Bus Interface Module
-
20
-
Table 6 Channel Busy Register
BIT
FUNCTION
15:0
Not Used
16
Channel 0 busy –This read-only bit indicates a message
transfer between the FPGA and the Channel 0 CAN
controller is in progress. When this bit is a logic “1” the
channel is busy. When this bit is a logic “0” the channel is
ready for the next message transfer.
17
Channel 1 busy –This read-only bit indicates a message
transfer between the FPGA and the Channel 1 CAN
controller is in progress. When this bit is a logic “1” the
channel is busy. When this bit is a logic “0” the channel is
ready for the next message transfer.
18
Channel 2 busy –This read-only bit indicates a message
transfer between the FPGA and the Channel 2 CAN
controller is in progress. When this bit is a logic “1” the
channel is busy. When this bit is a logic “0” the channel is
ready for the next message transfer.
19
Channel 3 busy –This read-only bit indicates a message
transfer between the FPGA and the Channel 3 CAN
controller is in progress. When this bit is a logic “1” the
channel is busy. When this bit is a logic “0” the channel is
ready for the next message transfer.
31:20
Not Used
Notes (Table 6):
1. All bits labeled “Not Used” will return logic “0” when read.
Channel x Command Register, (Read/Write) - (BAR0 + Chan X base + 00H)
A write to this register triggers the serial transmission of the SPI instruction
from the FPGA to the HI3111 CAN controller. Any additional data bytes
required for the selected instruction are also transmitted.
The function of each of the command register bits are described in Table 7.
Table 7 Command Register
BIT
FUNCTION
7:0
SPI Instruction –this 8-bit command is
transferred serially to the HI3111
31:8
Not Used1
Notes (Table 7):
1. All bits labeled “Not Used” will return logic “0” when read.
Channel x Control Register, (Read/Write) - (BAR0 + Chan X base + 04H)
The function of each of the control register bits are described in Table 8.