Acromag AcroPack AP470 Series User manual

Series AP470 AcroPack
48-Channel Digital I/O Module
USER’S MANUAL
ACROMAG INCORPORATED
30765 South Wixom Road
Wixom, MI 48393-2417 U.S.A.
Tel: [phone]
Fax: [phone]
Copyright 2016, Acromag, Inc., Printed in the USA.
Data and specifications are subject to change without notice.
8501055B

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Table of Contents
1.0 GENERAL INFORMATION..........................................................................................5
1.1 Intended Audience .......................................................................................................5
1.2 Preface.........................................................................................................................5
1.2.1 Trademark, Trade Name and Copyright Information .................................................................. 5
1.2.2 Class A Product Warning............................................................................................................. 5
1.2.3 Environmental Protection Statement ......................................................................................... 5
1.3 AcroPack Information –All Models ...............................................................................6
1.3.1 Ordering Information ................................................................................................................. 6
1.3.2 Key Features............................................................................................................................... 6
1.3.3 Key Features PCIe Interface ........................................................................................................ 7
1.4 Signal Interface Products ..............................................................................................7
1.5 Software Support .........................................................................................................8
Windows............................................................................................................................................ 8
VxWorks............................................................................................................................................ 8
Linux.................................................................................................................................................. 8
1.6 References ...................................................................................................................8
2.0 PREPARATION FOR USE..............................................................................................9
2.1 Unpacking and Inspecting.............................................................................................9
2.2 Installation Considerations .........................................................................................10
2.3 Non-Isolation Considerations......................................................................................10
2.4 Field I/O Connector ....................................................................................................10
Table 2.1 Field I/O Connector Pin Assignments ....................................................................................11
2.5 Logic Interface Connector ...........................................................................................14
Table 2.2 Logic Interface Connections ..................................................................................................15
3.0 PROGRAMMING INFORMATION ................................................................................16
CONFIGURATION REGISTERS................................................................................................................17
Table 3.1 Configuration Registers................................................................................................ 17
Standard (Default) Mode Memory Map...............................................................................................18

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Table 3.2: Standard Mode Memory Map .................................................................................... 19
Enhanced Mode Memory Map.............................................................................................................19
Table 3.3: Enhanced Mode Bank 0 Memory Map ....................................................................... 19
Table 3.4: Enhanced Mode Bank 1 Memory Map ....................................................................... 21
Table 3.5: Enhanced Mode Bank 2 Memory Map ....................................................................... 22
Table 3.6: Registers in Standard and Enhanced Mode Memory Map ......................................... 23
Interrupt Enable Status Register (Read/Write).....................................................................................23
Table 3.7 Interrupt Register....................................................................................................... 23
Module Location In System Register (Read Only).................................................................................24
Table 3.8 Location Register........................................................................................................ 24
Port Registers (Standard Mode Ports 0-5, Read/Write)........................................................................24
Write Mask Register & Enhanced Mode Select Register (Standard Mode Port 7, Read/Write) ............25
Table 3.9 Standard Mode Write Mask Register (Port 7) ............................................................. 25
Port Registers (Enhanced Mode Bank 0, Ports 0-5, Read/Write) ..........................................................25
Write Mask Register and Bank Select Register (Enhanced Mode Bank 0, Port 7, Read/Write) .............26
Table 3.10 Enhanced Mode Write Mask Register (Port 7) .......................................................... 26
Table 3.11 Enhanced Mode Bank Select ..................................................................................... 26
Event Sense Status & Clear Registers For I/O0-I/O47 (Enhanced Mode Bank 1, Ports 0-5, Read/Write)
............................................................................................................................................................27
Table 3.12 Port 0 Event Sense/Status Register (Ports 1-5 Similar).............................................. 27
Event Interrupt Status Register for Ports 0-5 (Enhanced Mode Bank 1, Port 6, Read Only) ..................28
Table 3.13 Event Interrupt Status Register for Ports 0-5............................................................. 28
Event Polarity Control Register For Ports 0-3 (Enhanced Mode Bank 1, Port 6, Write Only).................28
Table 3.14 Event Polarity Control Register For Ports 0-3 (Port 6) ............................................... 28
Event Polarity Control Register For Ports 4 & 5 (Enhanced Mode Bank 1, Port 7, Write Only)..............29
Table 3.14 Event Polarity Control Register For Ports 4&5 (Port 7).............................................. 29
Table 3.15 Bank Select Register (Write) ...................................................................................... 30
Bank Select Status Register 1 (Enhanced Mode Bank 1, Port 7, Read Only)..........................................30
Table 3.16 Bank Select Register (Read) ....................................................................................... 30
Debounce Control Register (Enhanced Mode Bank 2, Port 0, Read/Write) ..........................................30
Table 3.17 Debounce Control Register ...................................................................................... 30
Debounce Duration Register 0 (Enhanced Mode Bank 2, Port 1, Read/Write) .....................................31
Table 3.18 Debounce Duration Register 0:.................................................................................. 31
Table 3.19 Debounce Duration Clock Multiplier Selection.......................................................... 32
Debounce Duration Register 1 (Enhanced Mode Bank 2, Port 2, Read/Write) .....................................32
Table 3.18 Debounce Duration Register 0:.................................................................................. 32
Debounce Clock Select Register (Enhanced Mode Bank 2, Port 3, Write Only).....................................33
Bank Select (Write) & Status (Read) Register (Enhanced Mode Bank 2, Port 7, Read and Write) .........33
Table 3.19 Bank Select (Write) & Status (Read) Register ............................................................ 33
Software Reset Register (Accessible in Standard and Enhanced Mode) (Read/Write)..........................33
XADC Status/Control Register (Accessible in Standard and Enhanced Mode) (Read/Write).................34
XADC Address Register (Accessible in Standard and Enhanced Mode) (Write Only).............................34
Table 3.20: System Monitor Register Map .................................................................................. 34
Table 3.8: FPGA Voltage and Temperature Range ...................................................................... 35
Firmware Revision Register (Read Only) - (BAR0 + 0x0000 0200) .........................................................35

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The Effect of Reset ...............................................................................................................................36
Basic I/O Operation .............................................................................................................................36
Enhanced Operating Mode ..................................................................................................................36
Event Sensing.......................................................................................................................................37
Change-Of-State Detection ..................................................................................................................37
Debounce Control ................................................................................................................................37
Interrupt Generation ...........................................................................................................................38
Programming Example .........................................................................................................................39
4.0 THEORY OF OPERATION.......................................................................................... 42
4.1 Logic/Power Interface ................................................................................................42
4.2 I/O Ports ....................................................................................................................42
5.0 SERVICE AND REPAIR ............................................................................................... 43
5.1 Service and Repair Assistance .....................................................................................43
5.2 Preliminary Service Procedure ....................................................................................43
5.3 Where to Get Help......................................................................................................43
6.0 SPECIFICATIONS......................................................................................................... 44
6.1 Physical ......................................................................................................................44
6.2 Power Requirements ..................................................................................................44
6.3 Environmental Considerations ....................................................................................44
6.3.1 Operating Temperature.............................................................................................................44
6.3.2 Relative Humidity ......................................................................................................................45
6.3.3 Isolation ....................................................................................................................................45
6.3.4 Vibration and Shock Standards..................................................................................................45
6.3.5 EMC Directives ..........................................................................................................................45
6.4 Reliability Prediction ....................................................................................................45
6.5 Digital Inputs................................................................................................................46
6.6 Digital Outputs.............................................................................................................46
6.7 PCIe Bus Specifications ...............................................................................................46

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APPENDIX A .......................................................................................................................... 47
AP470 Functional Block Diagram........................................................................................47
APPENDIX B .......................................................................................................................... 48
AP-CC-01 Heatsink Kit Installation......................................................................................48
CERTIFICATE OF VOLATILITY ........................................................................................ 51
REVISION HISTORY ............................................................................................................ 52

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1.0 GENERAL INFORMATION
1.1 Intended Audience
This users’ manual was written for technically qualified personnel who will
be working with I/O devices using the AcroPack modules. It is not intended
for a general, non-technical audience that is unfamiliar with I/O devices and
their application.
1.2 Preface
The information contained in this manual is subject to change without
notice, and Acromag, Inc. (Acromag) does not guarantee its accuracy.
Acromag makes no warranty of any kind with regard to this material,
including, but not limited to, the implied warranties of merchantability and
fitness for a particular purpose. Further, Acromag assumes no responsibility
for any errors that may appear in this manual and makes no commitment to
update, or keep current, the information contained in this manual. No part
of this manual may be copied or reproduced in any form, without the prior
written consent of Acromag.
1.2.1 Trademark, Trade Name and Copyright Information
© 2016 by Acromag Incorporated.
All rights reserved. Acromag and Xembedded are registered trademarks of
Acromag Incorporated. All other trademarks, registered trademarks, trade
names, and service marks are the property of their respective owners.
1.2.2 Class A Product Warning
This is a Class A product. In a domestic environment this product may cause
radio interference, in which case the user may find it necessary to take
adequate corrective measures.
1.2.3 Environmental Protection Statement
This product has been manufactured to satisfy environmental protection
requirements where possible. Many components used (structural parts,
circuit boards, connectors, etc.) are capable of being recycled. Final
disposition of this product after its service life must be conducted in
accordance with applicable country, state, or local laws or regulations.

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1.3 AcroPack Information –All Models
AcroPack IO modules are based on the PCI Express Mini Card
Electromechanical specification and are 70mm in length with an additional
100 pin field I/O connector.
The AcroPack is 19.05mm longer than the full length mini PCIe card at
50.95mm. It has the same mPCIe board width of 30mm and uses the same
mPCIe standard board hold down standoff and screw keep out areas.
The AP470 module provides 48 channels of general-purpose digital inputs
and outputs. Inputs and outputs of this module are CMOS and TTL
compatible. Each of the I/O lines can be used as either an input, an output,
or an output with read-back capability. Each I/O line has built-in event sense
circuitry with programmable polarity and interrupt support. The inputs may
also operate as independent event sense inputs (without interrupts).
Outputs are open drain and may sink up to 15mA each. A 4.7K pull-up is
provided for each drain. Inputs include hysteresis and programmable
debounce. Interrupt, event, and debounce functionality applies to all 48
channels of this model. The AP470 utilizes state of the art Surface-Mounted
Technology (SMT) to achieve its wide functionality and is an ideal choice for
a wide range of industrial I/O applications that require a high-density, highly
reliable, high-performance interface at a low cost.
1.3.1 Ordering Information
The AcroPack ordering options are given in the following table.
Model Number
Description
Temp Range
AP470E-LF 1
48-Channel Digital I/O
-40oCto 85oC
Note 1: Applications requiring operating temperatures of 70°C to
85°C will require purchase of AcroPack Heatsink Accessory AP-CC-
01 with a minimum airflow of 200LFM. For temperatures below
70°C the module will require a minimum airflow of 200LFM.
AP-CC-01 AcroPack Conduction Cool Kit (See Appendix B for
installation instructions)
1.3.2 Key Features
High Channel Count - Provides programmable monitor and control
of 48 I/O points.
Programmable Polarity Event Interrupts (all 48 channels) -
Interrupts are software programmable for positive (low-to-high) or
negative (high-to-low) input level transitions on all 48 channels.
Using two channels per input signal, change-of-state transitions may
also be configured for up to 24 inputs.

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Programmable Debounce (all 48 channels) - The event sense input
circuitry includes programmable debounce times for all 48 channels.
Debounce time is the duration of time that must pass before the
input transition is recognized as valid. This helps prevent false event
detections and increases noise immunity.
CMOS (TTL Compatible) - Input threshold is at TTL levels and
includes hysteresis. I/O circuitry uses CMOS technology. As such,
output levels are CMOS compatible, even while sinking high current.
Output Read-back Function –Read-back buffers are provided that
allow the output port registers to be read back.
High Output Sink Capability - All outputs may sink up to 15mA with
a voltage drop ≤ 0.5V.
Outputs are “Glitch-Free” - Unlike some competitive units, the
outputs of this device do not “glitch” (momentarily turn on) upon
power-up or power-down for steady and safe control.
Open Drain Outputs Include Pull-ups - All outputs include 4.7K pull-
ups to +5V.
Overvoltage Protection - Individual I/O channels include over-
voltage clamps for increased ESD & transient protection.
High Impedance Inputs - High impedance inputs minimize input
current and loading of the input source.
No Configuration Jumpers or Switches - All configuration is
performed through software commands with no internal jumpers to
configure or switches to set.
1.3.3 Key Features PCIe Interface
PCIe Bus –The AP module includes a PCI Express Generation 1
interface operating at a bus speed of 2.5 Gbps with one lane in each
direction.
Compatibility –PCI Express Base Specification v2.1 compliant PCI
Express Endpoint.
1.4Signal Interface Products
This AcroPack Module will mate directly to all Acromag AP carriers. Once
connected, the module is accessed via a front panel connector on the carrier
board.
The cables and termination panels are also available. For optimum
performance with the AP470 digital I/O module, use of the shortest possible
length of shielded I/O cable is recommended.

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1.5Software Support
The AcroPack series products require support drivers specific to your
operating system. Supported operating systems include: Linux, Windows,
and VxWorks.
Windows
Acromag provides software products (sold separately) to facilitate the
development of Windowsapplications interfacing with AcroPack modules,
VPX I/O board products, and PCIe I/O Cards. This software (model APSW-
API-WIN) consists of low-level drivers and Dynamic Link Libraries (DLLs) that
are compatible with a number of programming environments. The DLL
functions provide a high-level interface to boards eliminating the need to
perform low-level reads/writes of registers, and the writing of interrupt
handlers.
VxWorks
Acromag provides a software product (sold separately) consisting of
VxWorkssoftware. This software (Model APSW-API-VXW) is composed of
VxWorks(real time operating system) libraries for all AcroPack modules,
VPX I/O board products, and PCIe I/O Cards. The software is implemented
as a library of “C” functions which link with existing user code to make
possible simple control of all Acromag AcroPack modules.
Linux
Acromag provides a software product consisting of Linuxsoftware. This
software (Model APSW-API-LNX) is composed of Linuxlibraries for all
AcroPack modules, VPX I/O board products, and PCIe I/O Cards. The
software is implemented as a library of “C” functions which link with existing
user code to make possible simple control of all Acromag AcroPack modules.
1.6 References
The following resources regarding AcroPack modules are available for
download on Acromag’s website or by contacting your sales representative.
PCI Express MINI Card Electromechanical Specification, REV 1.2
http://www.pcisig.com

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2.0 PREPARATION FOR USE
IMPORTANT PERSONAL AND PRODUCT SAFETY CONSIDERATIONS
It is very important for the user to consider the possible safety implications
of power, wiring, component, sensor, or software failures in designing any
type of control or monitoring system. This is especially important where
personal injury or the loss of economic property or human life is possible. It
is important that the user employ satisfactory overall system design. It is
understood and agreed by the Buyer and Acromag that this is the Buyer's
responsibility.
WARNING: This board utilizes static sensitive components and should only
be handled at a static-safe workstation. This product is an electrostatic
sensitive device and is packaged accordingly. Do not open or handle this
product except at an electrostatic-free workstation. Additionally, do not
ship or store this product near strong electrostatic, electromagnetic,
magnetic, or radioactive fields unless the device is contained within its
original manufacturer’s packaging. Be aware that failure to comply with
these guidelines will void the Acromag Limited Warranty.
2.1 Unpacking and Inspecting
Upon receipt of this product, inspect the shipping carton for evidence of
mishandling during transit. If the shipping carton is badly damaged or water
stained, request that the carrier's agent be present when the carton is
opened. If the carrier's agent is absent when the carton is opened and the
contents of the carton are damaged, keep the carton and packing material
for the agent's inspection.
For repairs to a product damaged in shipment, refer to the Acromag Service
Policy to obtain return instructions. It is suggested that salvageable shipping
cartons and packing material be saved for future use in the event the
product must be shipped.
This board is physically protected with packing material and electrically
protected with an anti-static bag during shipment. However, it is
recommended that the board be visually inspected for evidence of
mishandling prior to applying power.

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2.2 Installation Considerations
IMPORTANT: Adequate air
circulation must be provided to
prevent a temperature rise
above the maximum operating
temperature.
Refer to the specifications section for loading and power requirements. Be
sure that the system power supplies are able to accommodate the power
requirements of the system boards, plus the installed Acromag board,
within the voltage tolerances specified.
In an air cooled assembly, adequate air circulation must be provided to
prevent a temperature rise above the maximum operating temperature and
to prolong the life of the electronics. If the installation is in an industrial
environment and the board is exposed to environmental air, careful
consideration should be given to air-filtering.
In a conduction cooled assembly, adequate thermal conduction must be
provided to prevent a temperature rise above the maximum operating
temperature.
2.3 Non-Isolation Considerations
The board is non-isolated, since there is electrical continuity between the
PCIe bus and AcroPack module grounds. As such, the field I/O connections
are not isolated from the system. Care should be taken in designing
installations without isolation to avoid noise pickup and ground loops
caused by multiple ground connections.
2.4Field I/O Connector
A field I/O interface connector provides a mating interface between the AP
modules and the carrier board. The 100 pin ST5-50-1.50-L-D-P-TR Samtec
connector is used on the AcroPack card as board to board interconnect.
This connector will mate with the 100 pin SS5-50-3.00-L-D-K-TR Samtec
connector on the carrier. The stack height is 4.5mm.
Pin assignments are unique to each AP model. Table 2.1 lists signal pin
assignments for the module field I/O connector. Pins are left unconnected in
order to meet the minimum creepage distance required for 60 Volt
isolation.
For the most accurate pinout information, see the manual of the specific
carrier board model being used.

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Table 2.1 Field I/O Connector Pin Assignments
68 Pin Champ
Carrier Connector
50 Pin Champ
Carrier
Connector2
Ribbon Carrier
Connector1
Module P2 Pin
Number
Field I/O Signal
1
1
1
2
Field I/O 1
35
26
2
1
Field I/O 2
4
Reserved/isolation
3
Reserved/isolation
2
2
3
6
Field I/O 3
36
27
4
5
Field I/O 4
8
Reserved/isolation
7
Reserved/isolation
3
3
5
10
Field I/O 5
37
28
6
9
Field I/O 6
12
Reserved/isolation
11
Reserved/isolation
4
4
7
14
Field I/O 7
38
29
8
13
Field I/O 8
16
Reserved/isolation
15
Reserved/isolation
5
5
9
18
Field I/O 9
39
30
10
17
Field I/O 10
20
Reserved/isolation
19
Reserved/isolation
6
6
11
22
Field I/O 11
40
31
12
21
Field I/O 12
24
Reserved/isolation
23
Reserved/isolation
7
7
13
26
Field I/O 13
41
32
14
25
Field I/O 14
28
Reserved/isolation
27
Reserved/isolation
8
8
15
30
Field I/O 15
42
33
16
29
Field I/O 16
32
Reserved/isolation
31
Reserved/isolation
9
9
17
34
Field I/O 17
43
34
18
33
Field I/O 18
36
Reserved/isolation
35
Reserved/isolation
10
10
19
38
Field I/O 19
44
35
20
37
Field I/O 20
40
Reserved/isolation

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39
Reserved/isolation
11
11
21
42
Field I/O 21
45
36
22
41
Field I/O 22
44
Reserved/isolation
43
Reserved/isolation
12
12
23
46
Field I/O 23
46
37
24
45
Field I/O 24
48
Reserved/isolation
47
Reserved/isolation
13
13
25
50
Field I/O 25
47
38
26
49
Field I/O 26
52
Reserved/isolation
51
Reserved/isolation
14
14
27
54
Field I/O 27
48
39
28
53
Field I/O 28
56
Reserved/isolation
55
Reserved/isolation
15
15
29
58
Field I/O 29
49
40
30
57
Field I/O 30
60
Reserved/isolation
59
Reserved/isolation
16
16
31
62
Field I/O 31
50
41
32
61
Field I/O 32
64
Reserved/isolation
63
Reserved/isolation
17
17
33
66
Field I/O 33
51
42
34
65
Field I/O 34
68
Reserved/isolation
67
Reserved/isolation
18
18
35
70
Field I/O 35
52
43
36
69
Field I/O 36
72
Reserved/isolation
71
Reserved/isolation
19
19
37
74
Field I/O 37
53
44
38
73
Field I/O 38
76
Reserved/isolation
75
Reserved/isolation
20
20
39
78
Field I/O 39
54
45
40
77
Field I/O 40
80
Reserved/isolation
79
Reserved/isolation
21
21
41
82
Field I/O 41
55
46
42
81
Field I/O 42
84
Reserved/isolation

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83
Reserved/isolation
22
22
43
86
Field I/O 43
56
47
44
85
Field I/O 44
88
Reserved/isolation
87
Reserved/isolation
23
23
45
90
Field I/O 45
57
48
46
89
Field I/O 46
92
Reserved/isolation
91
Reserved/isolation
24
24
47
94
Field I/O 47
58
49
48
93
Field I/O 48
96
Reserved/isolation
95
Reserved/isolation
25
25
49
98
+5V (Fused)
59
50
50
97
GND
100
Reserved/isolation
99
Reserved/isolation

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Note 1: VPX4500-CC-LF is an
example of a carrier that uses the
ribbon cable connector. See
image of carrier.
Note 2: APCe7020E-LF is an
example of a carrier that uses the
Champ connector. See image of
carrier.
2.5 Logic Interface Connector
The AP module logic edge connector interfaces to the mating connector on
the carrier board. The pin assignments of this connector are standard for all
AP modules according to the PCI Express MINI Card Electromechanical
Specification, REV 1.2 (with exceptions shown in Table 2.2 and noted
below).
Power supplies +5, +12, and -12 Volt have been assigned to pins that are
reserved in the mini-PCIe specification. The ‘Present’signal is grounded on
the AP module. In addition, COEX1, COEX2 –wireless transmitter control
are reassigned to JTAG signals TMS and TCK. Lastly, UIM_C4, UIM_C8 –
reserved User Identity Module signals are reassigned to JTAG signals TDI and
TDO.

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Table 2.2 Logic Interface Connections
Pin #
Name
Pin #
Name
51
+5V1,2
52
+3.3V3
49
+12V1,2
50
GND
47
-12V1,2
48
N.C. (+1.5V)1
45
Present4
46
N.C. (LED_WPAN#)1
43
GND
44
N.C. (LED_WLAN#)1
41
+3.3V3
42
N.C. (LED_WWAN#)1
39
+3.3V3
40
GND
37
GND
38
N.C. (USB_D+)1
35
GND
36
N.C. (USB_D-)1
33
PETp0
34
GND
31
PETn0
32
SMB_DATA
29
GND
30
SMB_CLK
27
GND
28
N.C. (+1.5V)1
25
PERp0
26
GND
23
PERn0
24
+3.3V3
21
GND
22
PERST#
19
TDI (UIM_C4)1
20
N.C. (W_DISABLE#)1
17
TDO (UIM_C8)1
18
GND
15
GND
16
N.C. (UIM_VPP)1
13
RECLK+
14
N.C. (UIM_RESET)1
11
REFCLK-
12
N.C (UIM_CLK)1
9
GND
10
N.C. (UIM_DATA)1
7
CLKREQ#
8
N.C. (UIM_PWR)1
5
TCK (COEX2)1
6
N.C. (+1.5V)1
3
TMS (COEX1)1
4
GND
1
N.C. (WAKE#)1
2
+3.3V3
Note 1: Signals are not applicable for the AP470 implementation. Pins are
either “no connects” on the module or are repurposed for JTAG.
Note 2: +5V, +12V, and -12V power supplies have been assigned to pins that
are reserved in the mini-PCIe specification.
Note 3: All +3.3Vaux power pins are changed to +3.3V power.
Note 4: The ‘Present’signal is tied to circuit common on the AP module.

SERIES AP470 ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: [phone] - 16 -
http://www.acromag.com
- 16 -
www.acromag.com
3.0 PROGRAMMING INFORMATION
This Section provides the specific information necessary to program and
operate the AP470 module.
The PCIe bus is defined to address three distinct address spaces: I/O,
memory, and configuration space. The AcroPack module can be accessed
via the PCIe bus memory space and configuration spaces, only.
The AcroPack configuration registers are initialized by system software at
power-up to configure the card. The AP470 module is a Plug-and-Play PCIe
card. As a Plug-and-Play card the board’s base address and system interrupt
request are not selected via jumpers but are assigned by system software
upon power-up via the configuration registers. A PCIe bus configuration
access is used to access an AcroPack’s configuration registers.
When the computer is first powered-up, the computer’s system
configuration software scans the PCIe bus to determine what PCIe devices
are present. The software also determines the configuration requirements
of the PCIe card.
The system software accesses the configuration registers to determine how
many blocks of memory space the module requires. It then programs the
board’s configuration registers with the unique memory base address.
Since this board is not fixed in address space, its device driver must use the
mapping information stored in the board’s Configuration Space registers to
determine where the board is mapped in memory space.
The configuration registers are also used to indicate that the board requires
an interrupt request. The system software then programs the configuration
registers with the interrupt request assigned to the board.

SERIES AP470 ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: [phone] - 17 -
http://www.acromag.com
- 17 -
www.acromag.com
CONFIGURATION REGISTERS
The PCIe specification requires software driven initialization and
configuration via the Configuration Address space. This board provides 512
bytes of configuration registers for this purpose. It contains the
configuration registers shown in the following table to facilitate Plug-and-
Play compatibility.
The Configuration Registers are accessed via the Configuration Address and
Data Ports. The most important Configuration Registers are the Base
Address Registers which must be read to determine the base address
assigned to the board and the Interrupt Register which must be read to
determine the interrupt request that goes active on a board interrupt
request.
Table 3.1 Configuration
Registers
Reg.
Num.
D31 D24
D23 D16
D15 D8
D7 D0
0
Device ID
0x7016 AP470
Vendor ID
16D5
1
Status
Command
2
Class Code=118000
Rev ID=00
3
BIST
Header
Latency
Cache
4
64-bit Memory Base Address for Memory Accesses to PCIe
interrupt and I/O registers
4K Space (BAR0)
5:10
Not Used
11
Subsystem ID
0x7016 AP470
Subsystem Vendor ID
16D5
12
Not Used
13,14
Reserved
15
Max_Lat
Min_Gnt
Inter. Pin
Inter. Line
This board is allocated a 4K byte block of memory (BAR0), to access the PCIe
interrupt and I/O registers. The PCIe bus decodes 4K bytes for BAR0 for this
memory space.
The memory space address map for the AP470 is shown in Table 3.2. Note
that the base address for the board (BAR0) in memory space must be added
to the addresses shown to properly access these AP470 registers. Register
accesses as 32, 16, and 8-bit data in memory space are permitted. All the
registers of the AP470 are accessed via data lines D0 to D31.

SERIES AP470 ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: [phone] - 18 -
http://www.acromag.com
- 18 -
www.acromag.com
This board is addressable in the PCIe memory space to control the
configuration and status monitoring of 48 digital input or output channels.
This board operates in two modes: Standard Mode and Enhanced Mode.
Standard Mode provides simple monitor and control of 48 digital I/O lines. In
Standard Mode, each input line is configured as either an input, an output,
or an output with readback capability. Data is read from or written to one of
eight groups (ports) as designated by the address and read and write signals.
A Mask Register is used to disable writes to I/O ports designated as inputs to
prevent possible contention between an external input signal and the open-
drain output circuitry. Enhanced Mode includes the same functionality of
Standard Mode, but adds access to 48 additional event sense inputs
connected to each I/O point of ports 0-5. Thus, the Enhanced Mode allows
event triggered interrupts to be generated. Selectable hardware debounce
may also be applied in Enhanced Mode for noise free edge-detection of
incoming signals.
Memory is organized and addressed in separate banks of eight registers or
ports (eight ports to a bank). The Standard Mode of operation addresses the
first group of 8 registers or ports (ports 0-5 for reading/writing I/O0-47, Port
6 which is not used, and Port 7 which is the Mask Register). If the Enhanced
Mode is selected, then 3 additional banks of 8 registers are addressed to
cover the additional functionality in this mode. The first bank of the
Enhanced Mode (bank 0) is similar in operation to the Standard Mode. The
second bank (bank 1) provides event sense and interrupt control. The third
bank is used to configure the debounce circuitry to be applied to input
channels in the Enhanced Mode. Two additional mode-independent registers
are provided to enable the interrupt request line and generate a software
reset.
Standard (Default) Mode
Memory Map
Table 3.2 shows the memory map for the Standard Mode of operation. This
is the Default mode reached after power-up or system reset. Standard
Mode provides simple monitor and control of 48 digital I/O lines. In
Standard Mode, each I/O line is configured as either an input, or an output
(with readback capability), but not both. Data is read from or written to one
of eight groups (ports), as designated by the address and read and write
signals. A Mask Register is used to disable writes to I/O ports designated as
input ports. That is, when a port (group of 8 I/O lines) is used as an input
port, writes to this port must be blocked (masked) to prevent contention
between the output circuitry and any external device driving this line.
To switch to Enhanced Mode, four unique bytes must be written to port 7,
in consecutive order, without doing any reads or writes to any other port
and with interrupts disabled. The data pattern to be written is 07H, 0DH,
06H, and 12H, and this must be written after reset or power-up.

SERIES AP470 ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: [phone] - 19 -
http://www.acromag.com
- 19 -
www.acromag.com
Enhanced Mode Memory Map
Table 3.3 shows the memory maps used for the Enhanced Mode of
operation. Enhanced Mode includes the same functionality of Standard
Mode, but allows each input port’s event sense input and debounce logic to
be enabled.
In Enhanced Mode, a memory map is given for each of 3 memory banks.
The first memory bank (bank 0) has the same functionality as the Standard
Mode. Additionally, its port 7 register is used to select which bank to access
(similar to Standard Mode where port 7 was used to select the Enhanced
Mode). Bank 1 provides read/write access to the 48 event sense inputs.
Bank 2 provides access to the registers used to control the debounce
circuitry of these event sense inputs.
Table 3.3: Enhanced Mode
Bank 0 Memory Map
Notes:
BAR0 Base Address
Bit(s)
Description
0x0000 0000
7:0
Interrupt Register
0x0000 0004
7:0
Location in System Register
Table 3.2: Standard Mode
Memory Map
Notes:
1. The AP470 will respond to
addresses that are “Not
Used”. The board will
return “0” for all address
reads that are not used or
reserved.
2. Writing four unique bytes
(07H, 0DH, 06H, and 12H)
to port 7, in consecutive
order, will switch to
Enhanced Mode. Perform
this operation after reset or
power-up with interrupts
disabled. Do not read or
write to any other port
between writes.
BAR0 Base Address
Bit(s)
Description
0x0000 0000
7:0
Interrupt Register
0x0000 0004
7:0
Location in System Register
0x0000 0008
7:0
READ/WRITE –Port 0
I/O Register IO00-IO07
0x0000 000C
7:0
READ/WRITE –Port 1
I/O Register IO08-IO15
0x0000 0010
7:0
READ/WRITE –Port 2
I/O Register IO16-IO23
0x0000 0014
7:0
READ/WRITE –Port 3
I/O Register IO24-IO31
0x0000 0018
7:0
READ/WRITE –Port 4
I/O Register IO32-IO39
0x0000 001C
7:0
READ/WRITE –Port 5
I/O Register IO40-IO47
0x0000 0020
7:0
NOT USED1
0x0000 0024
7:0
READ/WRITE - Port 7
WRITE MASK REGISTER
AND
ENHANCED MODE SELECT REGISTER2
0x0000 0028→
0x00000040
31:0
NOT USED1