Adimtech APDCAM User manual

APDCAM User’s Guide
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APDCAM
Digital Avalanche Photodiode camera
User’s Guide
Version 1.01
Copyright © Adimtech Kft. 2010

APDCAM User’s Guide
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CONTENTS
1.Introduction................................................................................................................. 3
1.1.Using this document............................................................................................. 3
2.Using APDCAM......................................................................................................... 7
2.1.Power connection................................................................................................. 7
2.2.Operating environment......................................................................................... 7
2.3.Camera cooling .................................................................................................... 7
2.4.Configuration ....................................................................................................... 7
2.5.PC communication............................................................................................... 7
2.6.Software interface ................................................................................................ 8
2.7.Optical input interface.......................................................................................... 8
2.8.The detector and its operation.............................................................................. 9
2.9.Data acquisition.................................................................................................... 9
2.10.Controls and indicators................................................................................... 10
3.APDCAM Reference Manual.................................................................................. 12
3.1.System Overview ............................................................................................... 12
3.2.Detector and analog electronics ......................................................................... 13
3.3.Data Acquisition Unit......................................................................................... 15
3.3.1.ADC Timing ............................................................................................... 18
3.3.2.Filtering, resampling and channel selection................................................ 18
3.3.3.Triggering, overload protection.................................................................. 21
3.3.4.Data output format...................................................................................... 22
3.3.5.Offset control.............................................................................................. 22
3.4.Control unit ........................................................................................................ 23
3.4.1.Detector bias voltage setting....................................................................... 23
3.4.2.Temperature control.................................................................................... 23
3.4.3.Shutter and calibration light........................................................................ 24
3.5.Ethernet Communication.................................................................................... 26
3.6.Software interface .............................................................................................. 27
3.6.1.Received data memory map........................................................................ 31

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
1. Introduction
APDCAM is a 4x8 pixel Avalanche Photodiode Detector camera containing all detec-
tor infrastructure and data acquisition in one compact package. This type of detector is
designed for special applications where low light level has to be measured with extreme
high speed (up to several MHz). The detector pixels have large area (1.6x1.6 mm) com-
pared to CCD sensors therefore they are easier to match to low f-number optics used in
low light applications. All pixels of the detector are read out simultaneously; therefore the
throughput is not limited by readout time. The intrinsic gain of the detector allows meas-
urement under conditions where photodiodes would not be applicable. Stable gain is pro-
vided by the temperature stabilised detector and the calibration process is made easy by
the built-in shutter and calibration light source.
The digital part of the camera contains individual Analog to Digital Converters for all
32 channels. These ADCs continuously digitize data with 14 bit resolution and 10-50
MHz frequency. The resulting data stream can be digitally filtered and downsampled in
the camera to provide an output data stream with a frequency band matching the final
sampling rate. Various triggering and sampling schemes are available for the data acqui-
sition, including external, internal, post-trigger, external sample control. The resampled
data stream is transferred to a Personal Computer via standard 1 Gbit Ethernet communi-
cation, either over UTP or fibre cable. The same connection is used for camera control.
Technical specifications of the system are shown in Table 1 and Table 2. Figure 1.
shows photos of APDCAM where the location of its elements are indicated.
1.1. Using this document
Section 2 briefly describes the information needed for setting up and operating the
camera. Section 3. contains a detailed reference documentation intended for software
developers and for advanced users.

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Table 1. Technical specifications of APDCAM, part 1.
1Temperature range depends on ambient temperature.
2Standard setting. Sensitivity and bandwidth can be specified at order time. Selection affects noise level.
Detector
Detector type Avalanche Photodiode array
Hamamatsu S8550
Array size 4 x 8
Pixel size 1.6 x 1.6mm
Pixel pitch 2.3 mm
Spectral response range 300 to 1000 nm
Peak quantum efficiency 85% typical at 650 nm
Detector Gain Typical 50, max 100
Temperature control range1Typical 10...30 ºC
Temperature control type Peltier, cooling/heating
Optical interface
Lens mount Nikon F mount
Window material BK7 with antireflection coating
Shutter
Type Electromagnetically operated mechanical
Control Software or external input
Calibration light
Type Red LED with fibre coupling
Control DC set from software
Sensitivity and noise
Sensitivity @ Gain=100, 14 bit mode22.4 106 photon/s/digit
Noise equivalent photon flux @ no light2Typical 5 107 photon/s
Analog bandwidth21 MHz
Di
g
itizer
Internal sampling rate / bits 10-50 MHz / 14 bits
Digital filter 5-point FIR + 1point recursive
Output bits 14/12/8 (MSB from internal 14 bits)
Ring buffer 0...1024 samples/channel
Trigger Internal level/External TTL/software
Trigger delay 1µs....1000s
Resampling control Internal fixed divider or external TTL
input
Clock base Internal 20 MHz or external

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Table 2. Technical specifications of APDCAM, part 2.
3For typical PCIe computer card. For certain interface cards and computer configurations data rate might
be significantly lower.
Data transmission
Data and control interface Gigabit Ethernet over UTP and Fibre
Communication format UDP, both directions
Fibre interface Multimode, Duplex SC
Max. data rate @ 32 channels32 MHz/12bit
Power input
Power input 12 V DC, max. 6A
Power connector on power supply Lemo FFA.0S.302.CLAK68
Mechanical
Size (L,W,H) 36*16*19 cm
Weight without power supply 6.7 kg

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F-mount
Fans
Fibre
converter
Backplate
with
connectors
and indicators
Figure 1. View of APDCAM.

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2. Using APDCAM
2.1. Power connection
APDCAM is delivered with an external 12 V DC power adaptor. This unit has a re-
placeable power cord, please use one which matches your local mains outlet. The camera
needs a single 12 V DC input, maximum current is 6A. The power adaptor is usable from
100 to 230 V mains voltage.
2.2. Operating environment
Some effort might be needed in the setup to minimise noise pick up by the camera. Al-
though APDCAM is housed in a grounded Aluminium enclosure and the detector and
analog amplifiers are housed in an additional Faraday shield strong environmental elec-
trical noise sources might cause disturbances in the signals. To avoid such conditions
separate the camera ground from noise electronic equipment. The camera housing is con-
nected to electrical ground on the power supply mains connector.
2.3. Camera cooling
APDCAM has three independent fans on the top of the device which circulate air from
the openings on the lower part of the camera out through the fans. The openings should
be free to provide the necessary air flow. In the default setup the speed of the three fans is
controlled automatically, their speed will depend on the temperature of the internal com-
ponents. If this is not desirable the fans can also be set to fixed speed.
2.4. Configuration
The operating parameters of APDCAM are set up in two internal register tables, one for
the data acquisition and one for the camera control. Status of the camera can also be read
from these registers. Settings are stored in non-volatile memory, therefore after switching
off and on the camera the setup will remain the same. There are a few exceptions from
this rule:
Detector bias voltage is always off and disabled after switching on the camera.
The desired number of samples in the measurement are set to 0 on power-on.
The camera also contains configuration information which can only be read by the user.
An example is the maximum allowed detector bias voltage. These register values can be
changed by the manufacturer only.
2.5. PC communication
APDCAM can be connected to a PC either via UTP cable or fibre optics communica-
tions. In both cases Gigabit Ethernet is used with 100/10 Mbit as fallback. For using the
maximum data acquisition bandwidth it is essential to use a Gigabit interface card on the
PC side which connects to the internal bus via a PCI Express interface. A card connected
to the PCI bus will not deliver the maximum performance although camera operation at
lower acquisition speeds will not be affected.
If UTP (electrical) connection is intended simply connect a Gbit compatible UTP ca-
ble between the APDCAM UTP port and the PC interface card. In case of optical com-

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munication a media converter is needed on the PC side. Adimtech recommends D-Link
DMC-700SC media converters, which were extensively tested with APDCAM.
On the camera side the media converter is included in the camera. Connect a short
UTP cable between the camera UTP port and the camera Fibre module’s UTP port. Con-
nect the optical cable to the camera fibre converter optical connector. On the PC side
similarly connect the media converter between the PC Gigabit interface and the optical
cable.
To communicate with APDCAM the PC Ethernet interface IP address should be set up
to the same subnet as the camera. The default IP address of the camera is 10.123.13.101,
therefore the PC can be set up e.g. to 10.123.13.202. The netmask should be 255.0.0.0.
The camera Gigabit interface can be set up for a different IP address using a software
command over the internet connection; therefore it can also be connected to a local net-
work shared by other devices. However, in applications needing high data acquisition
performance this is not recommended as high network traffic can result in loss of data.
If the camera network address was set up in a wrong way or the address is not noted it
can happen that the PC cannot find the camera on the network. In such cases consult the
manufacturer for a solution.
2.6. Software interface
A user program can control APDCAM by sending UDP datagrams to the Gbit com-
munications module (Gigabit Ethernet Controller, ByteStudio, www.bytestudio.hu). The
control datagrams fall into two basic categories: control for the Gbit interface and register
read/write in one of the two internal modules of APDCAM: the data acquisition module
and the control module. The camera may answer to these UDP datagrams by sending one
ore more responding UDP datagrams.
For a standard setup the Gigabit interface parameters need not be modified. For spe-
cial settings please consult the separate Gigabit interface documentation.
Additionally to register read/write operations data form the camera are also sent to the
PC in UDP datagrams. This form of communication is optimal for sending large amounts
of data but it has no feedback to the sending device. This means that if a data packet is
lost the camera will not resend it. UDP packets are counted sequentially, therefore the
receiving program can detect when data loss occurred.
To ease usage a Windows library (CamControl.dll) is provided which can perform all
necessary register read/write and data stream control operations. The functions can be
called from C++ or IDL. Detailed description of the DLL functions and their use is pre-
sented in Section 3.6.
During data collection the PC might need a large amount of memory. These DLL
functions attempt to allocate this in a way which prevents it from being paged to virtual
memory. This possibility is by default not enabled for all users of a PC, and should be
enabled in the Windows Control Panel. For details see Section 3.6.
2.7. Optical input interface
APDCAM has a standard Nikon F-mount as optical input interface. A BK7 glass win-
dow is located in the F-mount therefore dust will not enter the detector housing. A shutter
is mounted between the window and the detector. The shutter can be opened either with a
software command or via an external TTL signal. A calibration light source is coupled to

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the detector surface which can be set up via software to emit various levels of constant
light on the detector, thus allowing calibration. The light level is not strictly proportional
to the setting and the illumination of the detector is not uniform, therefore the calibration
light cannot be used for calibrating the relative sensitivity of the pixels.
The calibration light is also useful for setting up the optical system. As APDCAM has
low spatial resolution viewing its image does not help in adjusting the lens focus. Instead
it can be done by illuminating the detector with the calibration light and observing its
image on a screen at the object.
2.8. The detector and its operation
The detector has 32 identical Avalanche Photodiode elements (pixels) biased from a
single voltage. The bias voltage determines the internal gain of the detector. The detector
bias voltage should be set between 200-400V using the appropriate control register. Al-
though the detector and electronics are protected from overload, damage cannot be ex-
cluded if e.g. only a single pixel is illuminated over an extensive period of time. To pro-
tect accidental switch-on of the bias voltage a voltage enable register is provided where
an appropriate code should be entered. Voltage can be switched on only after this.
An additional protection against overload is provided by the digital electronics. If en-
abled it can switch off the detector bias voltage when the signal level is above a certain
limit over a predefined time.
In order to stabilise the gain the detector temperature should be kept constant. This is
accomplished by a temperature control circuit. The standard detector temperature is 18 C
which under normal room temperature does not require too much cooling and prevents
condensation of humidity. If the environmental temperature is much lower or higher 20-
25 Celsius the detector reference temperature can be set to a different value.
2.9. Data acquisition
The logical scheme of the data acquisition is shown in Figure 2. This scheme is oper-
ating for all 32 channels independently; all channels can be enabled/disabled. The Analog
to Digital Converter (ADC) continuously samples the amplified detector signal to 14 bits
at a frequency between 10-50 MHz. A configurable digital filter provides high frequency
cutoff. The filtered signal is resampled at a lower frequency or using an external clock to
reduce data load to the computer. The data output can be controlled from external or in-
ternal trigger or software command. A ring buffer is also available which can store the
last maximum 1023 resampled data. When the trigger arrives data output starts with the
contents of the buffer, this post-trigger operation is possible. This is very useful in com-
ADC Digital filter Resampling Output control
Trigger
Fi
g
ure 2. Lo
g
ical scheme o
f
the basic data ac
q
uistion s
y
tem.

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bination with the internal trigger mode, as APDCAM can trigger itself on the incoming
light signal. The camera can also produce an output trigger when the output is started.
In the standard setup the data acquisition system timing is based on in internal quartz
oscillator. However, if needed this can be replaced by an external clock signal to provide
strictly synchronous operation between several cameras or other devices.
2.10. Controls and indicators
APDCAM has several indicator LEDs and input-output connectors mounted on its back-
plate. Their function is described in Table 3. The photo of the backplate where these units
are mounted is shown in Figure 3.
Figure 3. Photo of the backplate of APDCAM with the controls, connectors and
indicators.

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Controls
Power switch Switches the input power.
Reset button This depressed button can be operated with a pen or other pointed
device. Pressing it causes both the control unit and the data acquisi-
tion unit to return to factory default settings.
Connectors
Power connector Receives input 12 V DC power.
Clock in Reference TTL clock input. Synchronises clock base of APDCAM
to external source. (Signal standard 3.3 V CMOS)
Clock out Reference clock output. Can be used to synchronize clock base of
external device. (Signal standard 3.3 V CMOS)
Trigger in Data acquisition start trigger signal input.
(Signal standard 3.3 V CMOS)
Trigger out Outputs High level while data transmission is active.
(Signal standard 3.3 V CMOS)
Sample in Input resample clock. (Signal standard 3.3 V CMOS)
Opt Optional input-output. Can be selected among various internal sig-
nals in the factory.
Ethernet UTP connection to PC.
Optical Ethernet
UTP UTP cable connection from Ethernet connector of APDCAM if fibre communication is desired.
Optical Ethernet
fibre Fibre data connection to PC
LEDs
Temp. Red light means temperature alarm. Some element of the camera is
overheated.
Overload Red light means overload condition occurred, detector bias voltage
is switched off.
Comm. Green light flashes when control communication occurs between
PC and camera
ADC Data acquisition module state: Green indicates normal state, red
means error condition.
Control Control module state: Green indicates normal state, red means error
condition.
Calib. Yellow light means calibration light is on.
Shutter Yellow light means shutter is open
HV Blue light means detector bias voltage is on.
Ext. Clock Green light means external reference clock signal is accepted.
Data out Green light indicates data output to PC.
Gbit Ethernet interface is operating at Gigabit speed.
Table 3. List of controls, connectors and LED indicators of APDCAM.

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3. APDCAM Reference Manual
In this section a detailed description is given of the APDCAM system.
3.1. System Overview
The block scheme of APDCAM is shown in Figure 4. The APD array detector is
mounted on a copper tab which can be cooled/heated by a Peltier element. This way the
temperature of the detector is stabilised at a reference value which can be somewhat (max
~15 C) below or above the ambient temperature. Cooling the detector does not offer ad-
vantages in terms of noise, therefore the temperature control is provided only to stabilise
the gain. A shutter is mounted in front of the detector so that it can be coupled off from
the input light and can be calibrated using the calibration light. The DC current of the
calibration LED is set digitally while the light is coupled to the detector via four optical
fibres which illuminate the detector from 4 directions. The detector bias voltage is also
controlled digitally thus having the possibility of adjusting the detector gain to the re-
quirements.
The photocurrent from each of the 32 detector pixels is amplified by a sensitive low
noise amplifier. To compensate for the offset drift the output offset level of the amplifiers
can be controlled digitally through 32 Digital to Analog Converters (DAC). The final
analog output signal is digitized at 10-50 MHz/14 bit. The data stream can be digitally
filtered and finally it is resampled to produce the output data stream which is packed into
Gigabit
Ethernet Con-
troller
Data Acquisition
Unit (DAQ)
Analog
Amplifiers
Control and
Power Unit
Control
Detector bias voltage (HV)
Peltier
Temp.
sensors
Power input
(12 V DC)
Overload
Fans
Data
Calibration li
g
ht
Shutter
Detector
Detector temperature control
Shuter control
UTP-Fibre me-
dia converter
To PC
Gbit
Ethernet
(RJ-45)
Fi
g
ure 4. Block scheme o
f
APDCAM.

APDCAM User’s Guide
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UDP packets and transmitted through the Ethernet connection to the PC. Communication
with the PC can be done via the UTP connection. If needed fibre optics communication is
also possible through the built-in media converter.
The ADC works all the time, therefore it is possible to perform some triggering opera-
tions inside the camera. One possibility is internal triggering, where the data acquisition
starts when the signal reaches a certain level. The trigger level can be set individually for
all 32 channels. Another possibility is detector protection from extended periods of over-
load. If the signals are above a certain level over a specified time the bias voltage of the
detector is switched off. Details of the data acquisition operation are given in Section 3.2.
The Control and Power Unit provides power for all the other units and controls the de-
tector infrastructure: detector bias voltage, temperature, calibration light, shutter, fans.
The detector bias voltage can be set by the user up to a factory set limit in the range of
400-500 V. The exact limit is dependent on the individual detector. There is also a mini-
mum recommended detector bias voltage of 200 V, below that the crosstalk through the
pixels causes excessive noise. The control card also controls the detector temperature by
cooling or heating it via a Peltier element. No computer intervention is needed for the
control, only parameters can be set from the PC.
Operation parameters of the camera are set by setting registers in the ADC or the con-
trol unit. For a description of the register tables see Sections 3.2 and 3.4.
The communication between APDCAM and the host PC is performed by a general
purpose Gigabit communication card. It communicates with the two internal units via an
internal bus. The register tables of the camera can be written or read by sending UDP
datagrams to the Gigabit card. Acquired data is also sent via this card.
3.2. Detector and analog electronics
The detector has 32 identical Avalanche Photodiode elements (pixels) connected to a
common positive bias voltage. The arrangement and dimensions of pixels is shown in
Figure 5. The mapping to/from detector pixels to data acquisition is shown in Table 4.
Figure 5. Detector dimensions and arrangement of pixels viewing the detector from
the front of the camera. All dimensions are in mm.

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APD# Channel APD# Channel APD# Channel APD# Channel
A1 18 A2 19 A3 15 A4 14
B1 20 B2 17 B3 13 B4 12
C1 21 C2 22 C3 16 C4 11
D1 23 D2 24 D3 10 D4 9
E1 25 E2 26 E3 8 E4 7
F1 27 F2 32 F3 6 F4 5
G1 28 G2 29 G3 1 G4 4
H1 30 H2 31 H3 3 H4 2
Channel APD# Channel APD# Channel APD# Channel APD#
1 G3 9 D4 17 B2 25 E1
2 H4 10 D3 18 A1 26 E2
3 H3 11 C4 19 A2 27 F1
4 G4 12 B4 20 B1 28 G1
5 F4 13 B3 21 C1 29 G2
6 F3 14 A4 22 C2 30 H1
7 E4 15 A3 23 D1 31 H2
8 E3 16 C3 24 D2 32 F2
Table 4. Allocation of data acquisition channels for the detector pixels.
The detector bias voltage determines the internal gain of the pixels. The gain as a
function of the applied voltage is shown together with the Quantum efficiency (QE) in
Figure 6. Besides the gain the bias voltage also changes the detector capacitance, it de-
creases with increasing voltage. As all pixels are operated from a common bias voltage at
low voltage setting the crosstalk increases between channels which results in an increase
of the noise and its coherency between channels. Below about 150 V the 32 channel am-
plifier system oscillates between minimum and maximum output, therefore no measure-
ment can be done. The exact limit and the noise as a function of bias voltage depends on
the amplifier bandwidth but above 200 V bias voltage the detector is stable. The noise
level decreases slightly until about 300 V.
Figure 6. Detector typical Quantum Efficiency (QE) and Gain.
(Source: Hamamatsu S8550 datasheet.)

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The detector can be overloaded if high input light level is applied while the bias volt-
age is on. Although the detector and electronics is protected against overload under the
most unfavourable conditions about 0.4W heat can be generated in the detector which
might result in damage if present for an extensive time. To prevent damage the camera
electronics contains an overload protection function which switches off the detector bias
voltage if the output signal is above a limit for an adjustable time.
An additional measure to prevent overload is the two-step bias voltage switch-on pro-
cedure. When APDCAM is switched on the bias voltage is off. First a bias voltage enable
code should be written into the bias enable register and the voltage can be switched on
only after that. This procedure prevents accidental biasing die to any accidental software
error.
The detector is mounted on a temperature controlled tab. The reference temperature is
set in a register of the control module. This temperature can be either below or above the
environmental temperature. (The environmental temperature is measured on the base of
the camera and can be read from the register table.) Cooling the camera does not provide
specific advantage, but temperature changes affect the detector, therefore the aim of tem-
perature control is to provide a stable gain. 18 C is recommended for detector tempera-
ture as it is slightly below usual room temperature but it does not cause condensation of
air humidity on the detector. Please note that the temperature of the detector has an effect
on the gain as well. Applying the same bias voltage at lower temperature causes higher
gain. Please consult the Hamamatsu S8550 datasheet for details.
The analog electronics utilize two amplifier stages for each channel, their bandwidth is
from DC to a maximum frequency. Parameters of the first stage (feedback resistor and
capacitance) determine the bandwidth and also the noise level. For setting an optimal
Signal to Noise ratio some information on the expected light level is required. As default
the amplifier is set up for about 1010 photons/s light level and 1 MHz bandwidth. For
considerable different conditions the amplifier should be mounted with different compo-
nents, therefore a rough estimation of the light level and required bandwidth is necessary
at manufacturing time.
The high sensitivity amplifiers and the detector bias current can cause some drift in the
signal DC level. In order to compensate for this the analog electronics is equipped with a
DC offset input which can be set for each channel individually in the data acquisition
unit. The analog signals are negative in response to the input light, therefore the DC off-
set should be set to a high positive value to fit the signal into the 0-2V range of the digi-
tizer.
The detector is mounted directly on to the analog amplifier circuit board and cooled by
a cooling tab. The whole unit is mounted inside an Aluminium housing. The temperature
of the detector, the analog electronics and the housing are measured.
3.3. Data Acquisition Unit
The block scheme of the data acquisition unit (DAQ) is shown in Figure 7, while the
register map is in Table 5. and Table 6. After power-on different registers are set from
various sources as indicated in the table. Most of the registers recover their last data from
an on-board EEPROM memory, therefore they preserve their settings. Several of the reg-
isters will show the factory default value. This factory default can be regenerated for all

APDCAM User’s Guide
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registers by writing a code into the FACTORY_RESET register. This is identical to
pressing the reset button at the camera back.
Parameter R/W Offset
(byte) Size (byte) Value after start Description
BOARD_VERSION R 0 1 factory Board version code.
MC_VERSION R 1 2
factory Microcontroller program version code.
SERIAL R 3 2
factory Board unique serial No.
FPGA_VERSION R 5 2
factory FPGA program version code.
STATUS1 R 8 1
N/A Status flags, group 1
Bit 0: ADC PLL locked
Bit 1: Stream PLL locked
Bit 2-7: Reserved
STATUS2 R 9 1
N/A Bit 0: Reserved
Bit 1: Overload
Bit 2: External clock PLL locked
Bit 3: Reserved
Bit 4-7: ADC 1-4 sample enable
CONTROL R/W 11 1
EEPROM Various control bits:
Bit 0: External clock select
Bit 1: Clock out enable
Bit 2: External sample select
Bit 3: Sample out enable
Bit 4: Digital filter enable
Bit 5: Reserved
Bit 6: Reverse bit order in stream (1: LSB first)
Bit 7: Preamble enable
ADC_PLL_MULT R/W 12 1
EEPROM PLL multiplier for ADC clock generation.
Valid: 20...50
ADC_PLL_DIV R/W 13 1
EEPROM PLL divider for ADC clock generation.
Valid: 8...100
STREAM_PLL_MULT R/W 14 1 EEPROM PLL multiplier for ADC clock generation.
Valid: 20...50
STREAM_PLL_DIV R/W 15 1 EEPROM PLL divider for ADC clock generation.
Valid: 8...100
STREAM_CTRL R/W 16 1
0 The four lower bits enable the data output to the
four streams.
SAMPLE_NUMBER R/W 17 4 0 Requested number of samples. 0 for infinite.
CH_ENABLE R/W 21 4
EEPROM Enable bits for the 32 channels.
RINGBUFSIZE R/W 25 2
EEPROM Size of the ring buffer in samples per channel.
(Valid: 0...1023)
RESOLUTION R/W 27 1
EEPROM Output resolution.
0: 14 bit, 1: 12 bit, 2: 8 bit.
SAMPLEDIV_X_7 R/W 28 2 EEPROM Divider for generation of the sample clock from
7xADC_CLOCK. E.g. to take every second
sample write 14.
TRIGGER R/W 30 1
EEPROM Trigger enable bits.
Bit 0: Enable external trigger rising edge.
Bit 1: Enable external trigger falling edge.
Bit 2: Enable internal trigger. (For polarity see
INT_TRIG_LEVEL
Table 5. Register table of the DAQ unit, part one.

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Parameter
Parameter R/W Offset
(byte) Size (byte) Value after start Description
ADC_TEST_MODE R/W 32 4 EEPROM Each byte controls the mode of one ADC, first
is ADC 1. The codes in the lower 3 bits are:
0: Normal measurement
1: 10 0000 0000 0000
2: 11 1111 1111 1111
3: 00 0000 0000 0000
4: 10 1010 1010 1010, 01 0101 0101 0101
5: Long pseudorandom
(See Sect. 5.6 of ITU-T 0.150 (05/96) standard )
6: Short pseudorandom
(See Sect. 5.1 of ITU-T 0.150 (05/96) standard )
7: 11 1111 1111 1111, 00 0000 0000 0000
FACTORY_RESET W 37 1 N/A Writing hex CD into this register causes all
settings to return to factory reset.
BYTE_PER_SAMPLE R 40 4 N/A The ADC indicates here the number of bytes
per sample sent in one stream. The four bytes
correspond to the four streams, (See section
2.6)
CLOCK_PLL_MULT R/W 46 1 EEPROM External clock PLL multiplier. Valid: 2..33
CLOCK_PLL_DIV R/W 47 1 EEPROM External clock PLL divider. Valid: 1..32
OFFSET R/W 48 64
EEPROM These are the 32x2byte offset settings for the 32
analog channels. Standard values are 500..1000.
INT_TRIG_LEVEL R/W 112 64 EEPROM 32x2 bytes internal trigger setting for each
channel:
Bits 0...13: trigger level
Bit 14: 0: positive trigger (level)
1: negative trigger (level)
Bit 15: Enable trigger from this channel
ACT_SAMPLE R 176 16
0 4x4 byte indicating the number of acquired
samples per stream. As the sample timing is
identical for all channels these values are nor-
mally identical.
OVERLOAD_LEVEL R/W 192 2 EEPROM Overload condition setting for all channels:
Bits 0...13: level
Bit 14: 0: overload above level
1: overload below level
Bit 15: Overload enable.
OVERLD_STATUS R/W 194 1 0 Bit 0: overload status
Writing this register clears overload.
OVERLD_TIME R/W 195 2
EEPROM Overload time in 10 µs units.
TRIGGER_DELAY R/W 197 4 EEPROM Delay of data transmission start after any trigger
condition in units of the base clock period time.
FILTER_COEFF R/W 208 16
EEPROM Signed 16 bit integer coefficients for digital
filter. These should be written sequentially, they
are loaded into the FPGA when the last byte is
written.
Order of 2-byte coefficients:
COEFF_01...COEFF_05: FIR coefficients
COEFF_06: Recursive filter coefficient.
COEFF_07: Reserved
Coeff_08: Filter divide factor: 0...11.
Table 6. Register table of theDAQ unit, part two.

APDCAM User’s Guide
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At the beginning of the register map some registers describe the program and hard-
ware versions and the unique serial number of the ADC board.
After power-up the red-green bicolor ADC LED is lit green on the camera backplate.
If the ADC unit encounters a fatal problem this LED is red.
The DAQ unit is attached to the analog output signals at the backside of the detector
housing. The 32 input channels have an analog bandwidth of about 3 MHz, the input
voltage range is 0-2V. The input channels are grouped into 8-channel blocks, each block
is served by an 8-channel pipeline ADC chip. Data from one block is sent to one data
stream on the Gigabit communication card. The four streams are sent in separate UDP
datagrams on a single Gigabit connection to separate software ports in the PC.
3.3.1. ADC Timing
The timing is identical for all 32 channels and it is based on a single clock. This can be
either an internal 20 MHz oscillator or an external clock (clock in). Selection is done with
bit 0 in the CONTROL register. The external clock frequency is multiplied/divided by a
PLL (see CLOCK_PLL_MULT, CLOCK_PLL_DIV), therefore different input clock
frequencies can be accommodated in the 1...40 MHz range. The base clock generated
from the external clock should be between 19 and 40 MHz.
The ADC clock is generated from the selected base clock with a PLL (see
ADC_PLL_MULT, ADC_PLL_DIV), the resulting ADC clock must be between 10 and
50 MHz. An additional limitation is that the base clock multiplied by ADC_PLL_MULT
should be between 400 and 1000 MHz.
The status of the PLL units can be read from the STATUS1 and STATUS2 registers.
This is important especially if external clock is used. The external clock PLL status is
also shown on the camera backplate by the green Ext. Clock LED.
The 8-channel ADC blocks have a built-in test pattern generator which can be acti-
vated individually for all 4 blocks using the ADC_TEST_MODE register. This forces all
8 channels in one block to send the same test pattern.
3.3.2. Filtering, resampling and channel selection
The ADCs generate a data stream with 32x14 bits. A digital filter can be enabled in
the CONTROL register which filters all 32 channel data with identical settings. The lay-
out of one filter is shown in Figure 8. The 14 bit data is fed in from the left side. A 5-
stage FIR filter allows steep cut of the frequency band somewhat below the sampling
frequency of the ADC. An additional recursive filter is implemented after the FIR filter to
allow for lower frequency cut-off, albeit with less steep characteristic. The recursive filter
implementation with integer arithmetic deserves some attention as long integration times
can cause overflow in the data. To handle this situation some flexibility is provided at
the end of the filter where the output 8, 12 or 14 bit data is cut out: the location of the
output bits can be selected.
The following procedure is proposed for calculation of the filter coefficients. The de-
sired cutoff frequency of the recursive filter (frec) should be selected. From this the CO-
EFF_06 is
COEFF_06=ADCrec ff
e
 2
4096  .

APDCAM User’s Guide
Page 19/32
If the recursive filter is not to be used, COEFF_06=0. The impulse transfer function hi
of the FIR filter should be calculated at 5 points using 1/fADC as the time resolution of the
function. This can be done with some filter design toolbox. If the FIR filter is not to be
used h1is 1, all the others are 0. These hicoefficients should be normalised by their sums
and multiplied by (4096-c)/8 to yield the coefficients of the FIR filter:
COEFF_0i=


5
1ii
i
h
h(4096-COEFF_06)/8, i=1...5.
The two last coefficients should always have the same value:
COEFF_07 = 0, COEFF_08=9.
The filter coefficients are listed for selected cases in Table 7. Here the ADC frequency
is assumed to be 10 MHz. If a different ADC frequency is used all frequencies should be
scaled proportionally.
Filter Coefficients COEFF_01...COEFF_08
fREC
[
MHz
]
fFIR
[
MHz
]
01 02 03 04 05 06 07 08
50.0
50
00512 00000 00000 00000 00000 00000 00000 00009
50.0
20
00290 00202 00048 00000 00000 00000 00000 00009
50.0
10
00190 00164 00102 00042 00008 00000 00000 00009
0.5
50
00138 00000 00000 00000 00000 02991 00000 00009
0.5
20
00078 00054 00012 00000 00000 02991 00000 00009
0.5
10
00050 00044 00026 00010 00002 02991 00000 00009
0.1
50
00030 00000 00000 00000 00000 03846 00000 00009
0.1
20
00016 00012 00002 00000 00000 03846 00000 00009
0.1
10
00010 00010 00006 00002 00000 03846 00000 00009
Table 7. Filter coefficients for some selected cases.
Figure 8. Layout of the digital filter.

APDCAM User’s Guide
Page 20/32
Figure 9. shows the simulated frequency transfer functions of the same cases. From
these it is clear that the FIR filter is effective down to about 1/10-th of the ADC fre-
quency. For lower frequency cutoffs it can be used in combination with the recursive
filter. The recursive filter works at least down to 100 kHz, but at these low frequency cuts
the FIR filter has no effect.
After the filter the desired number of output bit resolution (8,12 or 14 bits, see RESO-
LUTION register) is selected by keeping the most significant bits.
The resulting amount of data could not be transferred through the Ethernet connection
when all the channels are operating, therefore some data reduction is needed. This can be
done either by reducing the number of active channels or by resampling the data (decima-
tion) to lower frequency.
Channels can be enabled individually, see CH_ENABLE register.
Resampling can be done for all active channels in the same way. The resampling clock
can be either a divided version of the ADC clock (see register SAMPLEDIV_X_7) or it can
be an external input clock. In this latter case it has to be noted, that the data acquisition
unit will not sample exactly at the time of the input clock pulse, but will take the latest
sample when the sample clock arrives. Depending on ADC clock This can result in
20...100 ns jitter.
Figure 9. Simulated frequency transfer functions of the filter cases listed inTable 7. Filter
coefficients for some selected cases.Table 7 .