
v PCIE-1760 User Manual
Contents
Chapter 1 Introduction..........................................1
1.1 Product Overview...................................................................................... 2
Figure 1.1 PCIE-1760 .................................................................. 2
1.2 Product Features....................................................................................... 2
1.2.1 Board ID........................................................................................ 2
1.3 Driver Installation ...................................................................................... 3
Figure 1.2 XNavi Installer ............................................................ 3
1.4 Software Utility .......................................................................................... 3
1.5 Software Development Using DAQNavi SDK ........................................... 4
1.6 FPGA Code Update .................................................................................. 4
1.7 Hardware Installation ................................................................................ 4
Figure 1.3 Device Manager ......................................................... 5
1.8 Accessories............................................................................................... 5
Chapter 2 Installation and Field Applications ....7
2.1 Signal Connection and Pin Assignments .................................................. 8
2.1.1 Isolated Digital Input Signal Connection ....................................... 8
Figure 2.1 Digital input signal connection with wet contact config-
uration......................................................................... 8
Figure 2.2 Digital input signal connection with dry contact configu-
ration........................................................................... 9
2.1.2 Relay Output Signal Connection................................................... 9
Figure 2.3 Relay output signal connection................................. 10
Figure 2.4 Digital input signal connection with dry contact configu-
ration......................................................................... 10
2.1.3 Counter Signal Connection ......................................................... 11
Figure 2.5 TTL type counter output signal connection............... 11
Figure 2.6 Sink type counter output signal connection .............. 12
2.1.4 Pin Assignment ........................................................................... 12
Figure 2.7 Pin assignment of PCIE-1760 .................................. 12
2.1.5 Switch and Jumper Settings ....................................................... 13
Chapter 3 Function Details.................................17
3.1 Digital Input ............................................................................................. 18
3.1.1 Digital Input Interrupt................................................................... 18
Figure 3.1 Digital input rising edge interrupts ............................ 18
Figure 3.2 Digital input falling edge interrupts ........................... 18
Figure 3.3 Digital input both edges interrupts ............................ 18
3.1.2 Digital Input Pattern Match Interrupt ........................................... 18
Figure 3.4 Digital input pattern match interrupt for pattern
“10xx0100”................................................................ 19
3.1.3 Digital Input Debounce Filter....................................................... 19
Figure 3.5 Digital input debounce filter ...................................... 19
3.1.4 Instant Digital Input Acquisition................................................... 19
Figure 3.6 Instant digital input acquisition.................................. 19
3.2 Digital Output .......................................................................................... 20
3.2.1 Static Digital Output Update........................................................ 20
Figure 3.7 Static digital output update ....................................... 20
3.3 Counter Output........................................................................................ 20
3.3.1 Event Counting ........................................................................... 20
Figure 3.8 Rising edge event counting ...................................... 20