Aiwa XP-ZR850 User manual
SERVICE MANUAL
FM/AM PORTABLE CD PLAYER
AEP Model
E Model
SPECIFICATIONS
XP-ZR850
Ver. 1.3 2005.10
Model Name Using Similar Mechanism NEW
CD Mechanism Type CDM-3325ERV
Optical Pick-up Name DAX-25EV
9-879-437-04
2005J05-1
© 2005.10
Sony Corporation
Personal Audio Division
Published by Sony Engineering Corporation
– Continued on next page –
US and foreign patents licensed from Dolby Laboratories.
•SonicStage and SonicStage logo are trademarks or registered trademarks of Sony
Corporation.
•OpenMG, Net MD, ATRAC, ATRAC3plus and their logos are trademarks of Sony
Corporation.
•“WALKMAN” is a registered trademark of Sony Corporation to represent Headphone
Stereo products. is a trademark of Sony Corporation.
•Microsoft, Windows, Windows NT and Windows Media are trademarks or registered
trademarks of Microsoft Corporation in the United States and /or other countries.
•IBM and PC/AT are registered trademarks of International Business Machines
Corporation.
•Macintosh is a trademark of Apple Computer, Inc. in the United States and/or other
countries.
•Pentium is a trademark or a registered trademark of Intel Corporation.
•All other trademarks and registered trademarks are trademarks or registered trademarks
of their respective holders. ™ and ® marks are omitted in this manual.
•CD and music-related data from Gracenote, Inc., copyright © 2000-2003 Gracenote.
Gracenote CDDB
®
Client software, copyright 2000-2003 Gracenote. This product and
service may practice one or more of the following U.S. Patents: #5,987,525; #6,061,680;
#6,154,773, #6,161,132, #6,230,192, #6,230,207, #6,240,459, #6,330,593, and other
patents issued or pending.
Gracenote and CDDB are registered trademarks of Gracenote. The Gracenote logo and
logotype, the Gracenote CDDB logo, and the “Powered by Gracenote” logo are
trademarks of Gracenote.
Program © 2001, 2002, 2003, 2004 Sony Corporation
Documentation © 2004 Sony Corporation
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2
XP-ZR850
SAFETY-RELATED COMPONENT WARNING!!
COMPONENTS IDENTIFIED BY MARK 0 OR DOTTED LINE
WITH MARK 0ON THE SCHEMATIC DIAGRAMS AND IN
THE PARTS LIST ARE CRITICAL TO SAFE OPERATION.
REPLACE THESE COMPONENTS WITH SONY PARTS WHOSE
PART NUMBERS APPEAR AS SHOWN IN THIS MANUAL OR
IN SUPPLEMENTS PUBLISHED BY SONY.
•Abbreviation
E/4 : Argentina model
E19 : South African, Singapore, Malaysia,
Vietnam and Indian model
E92 : Panama, Venezuelan and Caribbian
Can model
MX : Mexican model
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Ver. 1.1
• AEP*model
• E19*model
3
XP-ZR850
Notes on chip component replacement
•Never reuse a disconnected chip component.
•Notice that the minus side of a tantalum capacitor may be
damaged by heat.
Flexible Circuit Board Repairing
•Keep the temperature of the soldering iron around 270 ˚C
during repairing.
•Do not touch the soldering iron on the same conductor of the
circuit board (within 3 times).
•Be careful not to apply force on the conductor when soldering
or unsoldering.
CAUTION
Use of controls or adjustments or performance of procedures
otherthan those specifiedherein mayresultin hazardous radiation
exposure.
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TABLE OF CONTENTS
1. SERVICING NOTES ................................................ 4
2. GENERAL ................................................................... 6
3. DISASSEMBLY
3-1. Disassembly Flow ........................................................... 7
3-2. Cabinet (Upper) Assy, Cabinet (Lower) .......................... 7
3-3. JACK Board, Optical Pick-up Assy (CDM-3325ERV) ... 8
3-4. SWITCH Board ............................................................... 8
4. ELECTRICAL ADJUSTMENT ............................. 9
5. DIAGRAMS
5-1. Printed Wiring Board – EGL Board – ............................ 12
5-2. Schematic Diagram – EGL Board – ........................... 13
5-3. Printed Wiring Board
– JACK Board (Component Side) – ................................ 14
5-4. Printed Wiring Board
– JACK Board (Conductor Side) – .................................. 15
5-5. Schematic Diagram – JACK Board – ............................. 16
5-6. Printed Wiring Board – SWITCH Board – .................... 17
5-7. Schematic Diagram – SWITCH Board – ....................... 18
6. EXPLODED VIEWS
6-1. Cabinet (Upper) Section .................................................. 27
6-2. Cabinet (Upper) Assy Section ......................................... 28
6-3. Cabinet (Lower) Section.................................................. 29
6-4. Optical Pick-up Section (CDM-3325ERV) ..................... 30
7. ELECTRICAL PARTS LIST .................................. 31
4
XP-ZR850 SECTION 1
SERVICING NOTES
NOTES ON HANDLING THE OPTICAL PICK-UP
BLOCK OR BASE UNIT
The laser diode in the optical pick-up block may suffer electrostatic
break-down because of the potential difference generated by the
charged electrostatic load, etc. on clothing and the human body.
During repair, pay attention to electrostatic break-down and also
use the procedure in the printed matter which is included in the
repair parts.
The flexible board is easily damaged and should be handled with
care.
NOTES ON LASER DIODE EMISSION CHECK
The laser beam on this model is concentrated so as to be focused on
the disc reflective surface by the objective lens in the optical pick-
up block. Therefore, when checking the laser diode emission,
observe from more than 30 cm away from the objective lens.
LASER DIODE AND FOCUS SEARCH OPERATION
CHECK
During normal operation of the equipment, emission of the laser
diode is prohibited unless the upper lid is closed while turning ON
the S531. (push switch type)
The following checking method for the laser diode is operable.
•Method:
Emission of the laser diode is visually checked.
1. Open the upper lid.
2. With a disc not set, turn on the S531 with a screwdriver having
a thin tip as shown in Fig.1.
3. Press the u ENTER button.
4. Observing the objective lens, check that the laser diode emits
light.
When the laser diode does not emit light, automatic power
control circuit or optical pick-up is faulty.
In this operation, the objective lens will move up and down 2
times along with inward motion for the focus search.
NOTES ON REPLACEMENT OF EGL BOARD OR
EEPROM (IC1602)
When EGL board is replaced or EEPROM (IC1602) on the EGL
board is replaced, patch processing is needed.
Confirm about information of patch processing to each service
headquarters.
Fig. 1 Method to push the S531
UNLEADED SOLDER
Boards requiring use of unleaded solder are printed with the lead-
free mark (LF) indicating the solder contains no lead.
(Caution: Some printed circuit boards may not come printed with
the lead free mark due to their particular size)
: LEAD FREE MARK
Unleaded solder has the following characteristics.
•Unleaded solder melts at a temperature about 40 °C higher
than ordinary solder.
Ordinary soldering irons can be used but the iron tip has to be
applied to the solder joint for a slightly longer time.
Soldering irons using a temperature regulator should be set to
about 350 °C.
Caution: The printed pattern (copper foil) may peel away if
the heated tip is applied for too long, so be careful!
•Strong viscosity
Unleaded solder is more viscou-s (sticky, less prone to flow)
than ordinary solder so use caution not to let solder bridges
occur such as on IC pins, etc.
•Usable with ordinary solder
It is best to use only unleaded solder but unleaded solder may
also be added to ordinary solder.
OPERATION CHECK WHEN THE LID IS OPEN
Inperformingthe repair with the powersupplied tothe set, removing
the JACK board causes the set to be disabled.
In such a case, make a solder bridge to short SL501 (OPEN) on the
JACK board in advance.
– JACK Board (Component Side) –
SL501
(OPEN)
S531
lever (detection)
lever (detection)
JACK board
Ver. 1.3
5
XP-ZR850
Providing the required system environment
The following system environment is required in order to use the SonicStage Ver. 2.3.
This software is not supported by the following environments:
•OSs other than the indicated above
•Personally constructed PCs or operating systems
•An environment that is an upgrade of the original manufacturer-installed operating system
•Multi-boot environment
•Multi-monitor environment
•Macintosh
•We do not ensure trouble-free operation on all computers that satisfy the system requirements.
•The NTFS format of Windows XP/Windows 2000 Professional can be used only with the standard
(factory) settings.
•We do not ensure trouble-free operation of the system suspend, sleep, or hibernation function on all
computers.
•For Windows 2000 Professional users, install Service Pack 3 or later before using the software.
System requirements
Computer IBM PC/AT or Compatible
•CPU:Pentium II 400 MHz or higher (Pentium III 450 MHz or higher
is recommended.)
•Harddisk drive space: 200 MB or more (1.5 GB or more is
recommended) (The amount space will vary according to Windows
version and the number of music files stored on the hard disk.)
•RAM: 64 MB or more (128 MB or more is recommended)
Others
•CDdrive(capable of digital playback by WDM)
•Sound Board
•USBport (supports USB (previously USB 1.1))
Operating
System Factory installed:
Windows XP Media Center Edition 2005/Windows XP Media Center
Edition 2004/Windows XP Media Center Edition/Windows XP
Professional/Windows XP Home Edition/Windows 2000 Professional/
Windows Millennium Edition/Windows 98 Second Edition
Display High Color (16 bit) or higher, 800 u600 dots or better (1024 u768 dots
or better is recommended)
Others •Internet access: for Web registration, EMD services and CDDB
•WindowsMedia Player (version 7.0 or higher) installed for playing
WMA files
Notes
6
XP-ZR850 SECTION 2
GENERAL This section is extracted from
instruction manual.
'UIDETO0ARTSAND
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7
XP-ZR850
SECTION 3
DISASSEMBLY
•This set can be disassembled in the order shown below.
3-1. DISASSEMBLY FLOW
3-2. CABINET (UPPER) ASSY, CABINET (LOWER)
Note: Follow the disassembly procedure in the numerical order given.
3-2. CABINET (UPPER) ASSY , CABINET (LOWER)
(Page 7) 3-4. SWITCH BOARD
(Page 8)
3-3. JACK BOARD, OPTICAL PICK-UP ASSY (CDM-3325ERV)
(Page 8)
SET
1
Open the upper lid.
4
cabinet (lower)
5
flexible flat (12 core) cable
(CN801)
6
cabinet (upper) assy
S530
knob (hold)
Note: On installation of JACK board,
adjust the position of switch (S530)
and knob (hold).
3
two claws
3
two claws
3
two claws
2
two screws
2
four screws
8
XP-ZR850
3-3. JACK BOARD, OPTICAL PICK-UP ASSY (CDM-3325ERV)
3-4. SWITCH BOARD
1
OP flexible board
(CN601)
5
optical pick-up assy
(CDM-3325ERV)
3
JACK board
4
insulator
4
insulator
4
insulator
2
two connectors
(CN602, CN603)
1
Open the upper lid.
2
eight screws
4
cover (SW PWB)
5
flexible flat
(12 core) cable
(CN1002)
3
claw
q;
liquid crystal display panel (LCD1001)
8
SWITCH board
9
shield plate (LCD)
6
Remove the solder.
7
LCD flexible board (CN1001)
qs
button (operation)
qa
button (menu)
9
XP-ZR850
SECTION 4
ELECTRICAL ADJUSTMENTS
BEFOREHAND ADJUSTMENT
Connection:
Adjusting Procedure:
1. Connect the frequency counter toTP454 and TP103 (RFGND
(A)) or TP104 (RFGND (B)) on the JACK board.
2. Set the AM 531 kHz (except AEP model) or AM 530 kHz
(AEP model)
3. Adjust the RV401 so that the reading of frequency counter is
300 ±3 kHz.
0 dB=1 µV
[AM]
Setting:
Function: RADIO
Band: AM
[FM]
Setting:
Function: RADIO
Band: FM
•Repeat the procedures in each adjustment several times, and
the tracking adjustments should be finally done by the trimmer
capacitors.
( ): AEP model
AM IF ADJUSTMENT
Adjust for a maximum reading on level meter
T102 620 (621) kHz
( ): AEP model
AM FREQUENCY COVERAGE CONFIRMATION
Adjustment Part Frequency Display Reading in DigitalVoltmeter
Confirmation 531 (530) kHz 1.2 ±0.8 V
Confirmation 1,710 (1,602) kHz 7.2 (6.7) ±1.0 V
( ): AEP model
AM TRACKING ADJUSTMENT
Adjust for a maximum reading on level meter
T101 620 (621) kHz
CT101 1,400 (1,404) kHz
FM FREQUENCY COVERAGE CONFIRMATION
Adjustment Part Frequency Display Reading in DigitalVoltmeter
Confirmation 87.5 MHz 5.2 ±0.8 V
Confirmation 108 MHz 9.1 ±1.0 V
FM TRACKING ADJUSTMENT
Adjust for a maximum reading on level meter
L104 98 MHz
Adjustment and Connecting Location: JACK board
(See page 10)
+
–
frequency counter
TP454
TP103 (RFGND (A)) or
TP104 (RFGND (B))
JACK board
AM RF signal
generator
30% amplitude
modulation by
400 Hz signal
Output level:
as low as possible
Put the lead-wire
antenna close to
the set.
+
–
level meter
set
32
Ω
JACK board
TP103 (RFGND (A)) or
TP104 (RFGND (B))
JACK board
TP217 (TU_L) or
TP215 (TU_R)
FM RF signal
generator
22.5 kHz frequency
deviation by 1 kHz
signal
Output level:
as low as possible
+
–
level meter
set
32
Ω
0.01
µ
F
JACK board
TP101 (RF (A)) or
TP102 (RF (B))
JACK board
TP103 (RFGND (A)) or
TP104 (RFGND (B))
JACK board
TP103 (RFGND (A)) or
TP104 (RFGND (B))
JACK board
TP217 (TU_L) or
TP215 (TU_R)
digital voltmeter
TP111 (VT)
TP103 (RFGND (A)) or
TP104 (RFGND (B))
100 k
Ω
JACK board
10
XP-ZR850
Adjustment and Connecting Location:
TP217
(TU_L) TP215
(TU_R)
TP103
(RFGND (A))
TP101
(RF (A))
L104
FM Tracking Adjustment
AM Tracking
Adjustment
T101
CT101
T102
AM IF Adjustment
– JACK Board (Component Side) –
TP454
TP111
(VT)
TP104
(RFGND (B))
TP102
(RF (B))
RV401
Beforehand Adjustment
– JACK Board (Conductor Side) –
1111
XP-ZR850
XP-ZR850
SECTION 5
DIAGRAMS
Note on Printed Wiring Boards.
•X: parts extracted from the component side.
•Y: parts extracted from the conductor side.
•z: Through hole.
•W: indicates side identified with part number.
•f: internal component
•: Pattern from the side which enables seeing.
(The other layers' patterns are not indicated.)
•Note for PrintedWiring Boards and Schematic Diagrams
Caution:
Pattern face side: Partsonthepattern facesideseenfrom
(Conductor Side) the pattern face are indicated.
Parts face side: Parts on the parts face side seen from
(Component Side) the parts face are indicated.
•EGL board is multi-layer printed board.
However, the patterns of intermediate-layer have not been in-
cluded in the diagram.
Note on Schematic Diagrams.
•All capacitors are in µF unless otherwise noted. (p: pF)
50 WV or less are not indicated except for electrolytics
and tantalums.
•All resistors are in Ωand 1/4W or less unless otherwise
specified.
• f: internal tolerance.
•C: panel designation.
•A: B+ Line.
•H: adjustment for repair.
•Powervoltageisdc 1.5V andfedwith regulated dc power
supply from battery terminal.
•Voltages and waveforms are dc with respect to ground
under no-signal (detuned) conditions.
no mark : CD PLAY
( ) : FM
[ ] : AM
•Voltages are takenwithaVOM (Input impedance 10 MΩ).
Voltage variations may be noted due to normal produc-
tion tolerances.
•Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal produc-
tion tolerances.
•Circled numbers refer to waveforms.
•Signal path.
J: CD PLAY
F: FM
f: AM
•The voltage and waveform of CSP (chip size package)
cannot be measured, because its lead layout is different
from that conventional IC.
•Abbreviation
E/4 : Argentina model
E19 : South African, Singapore, Malaysia, Vietnam
and Indian model
E92 : Panama,Venezuelanand CaribbianCan model
MX : Mexican model
Caution:
Pattern face side: Partsonthepattern facesideseenfrom
(Side B) the pattern face are indicated.
Parts face side: Parts on the parts face side seen from
(Side A) the parts face are indicated.
•Lead Layouts
Lead layout of conventional IC CSP (chip size package)
surface
– EGL Board – – JACK Board –
1X602
500 mV/DIV, 20
n
s/DIV
45.5 ns 1.1 Vp-p
qs Q104 (Collector) (FM mode)
1 V/DIV, 50
n
s/DIV
195 ns 2.2 Vp-p
qs Q104 (Collector) (AM mode)
500 mV/DIV, 50
n
s/DIV
195 ns 1.2 Vp-p
qa IC101 qg (X_0) (FM mode)
1 V/DIV, 5
µ
s/DIV
13.3 µs1.6 Vp-p
qa IC101 qg (X_0) (AM mode)
200 mV/DIV, 5
µ
s/DIV
13.3 µs0.5 Vp-p
qd IC401 wd (SYNC)
(CD play mode)
1 V/DIV, 1
µ
s/DIV
2.8 µs2.1 Vp-p
2.8 µs2.7 Vp-p
qf IC401 ta (LO_2), ts (LO_1)
1 V/DIV, 1
µ
s/DIV
•Waverforms
Note: The components identified by mark 0or dotted
line with mark 0are critical for safety.
Replace only with part number specified.
Ver. 1.2
1212
XP-ZR850
XP-ZR850
5-1. PRINTEDWIRING BOARD – EGL BOARD – :Uses unleaded solder.
• Semiconductor
Location
Ref. No.
Location
D601 B-2
D602 B-1
IC603 D-7
IC604 G-3
IC1602 B-4
Q602 A-1
1-864-385- (12)
12
EGL BOARD (SIDE A)
Q602
R407
R620
R615
R617
R606
D602
C683
X602
R611
R612
D601
C639
R668
C695
R621
R624
R625
C617
R623
C632 C619
C631
C644
C629
C627
C662
C682
R647
C667
R631
C686
C687
R619
150
25 26
85
4
1
R616
C684
R406
-1
-2
1-864-385- (12)
12
EGL BOARD (SIDE B)
CN9001
R663
R667
VDR601
R618
R632
C607
C676
R662
C675
R602
R610
C678
C664
C646
C663
R613
R644
R653
R642
C659
C677
R604
C610
C603
R629
R638
R636 R637
R609
C608
C654
C653
C649
R628
R608
R639
C648
R634
C642 R635
C650
R656
R655
R650
R651
R649
C624 C626
C618
R669
C602 RB601
C601
R603
C694
CN601
C609
60 31
30
1
1
15
OPTICAL
PICK-UP
BLOCK
(DAX-25EV)
A
B
C
D
E
F
G
H
I
12345678910
JACK BOARD
CN901
(Page 14)
A
R614
IC604
IC1602
IC603
Ver. 1.3
When EGL board is replaced or EEPROM (IC1602) on the EGL board is
replaced, patch processing is needed.
Confirmaboutinformationof patch processing toeachserviceheadquarters.
1313
XP-ZR850
XP-ZR850
5-2. SCHEMATIC DIAGRAM – EGL BOARD – • See page 11 forWaveform. • See page 20 for IC Pin Function Description.
(Page 16)
C602
C694
R602
C601
R603
R608
R609
C609
R624 R623
R618
C629
R621
C631
C632
C695
C618
C617
C619
C624
C642
R638
R629
R628
R635
R636
R634
C650 C653
R637
C654
R639
R642
R649
R604
C610
C603
R653
R613
C667
R644
X602
C682
C683
R611
R612
D601
C684
D602
R615
R616
R617
Q602
R606
R631
R610
C686
C687
C662
IC1602
RB601
C627
C607
C677
C664
C675
C676
C663
R406
C649
R656
R655
CN601
CN9001
C608
R625
C648
R650
R651
C626 C646
C659
R647
C678
R619
C644
C639
R668 R407
R663
R667
R662
R669
R632
R620
VDR601
IC603
IC604
470p
0.1
0
22 6.3V
10
47k
22k
2200p
10k 10k
1k
0.1
1k
0.1
0.1
4700p
4700p
4700p
4700p
0.1
0.1
0
2.2k
2.2k
1M
100k
10k
4700p 0.47
220k
0.1
47k
47k
22k
10
0.1
100
4V
10k
0
0.1
10
22MHz
47p
100p
470k
470k
HVL375CM
0.1
HVL375CM
100k
470k
470k
RT3T67M
0
220k
100k
47
6.3V
0.1
0.1
AK6510CL-L
22k
22 6.3V
0.01
0.1
47
6.3V
0.1
0.1
0.1
0
0.47
100k
47k
15P
60P
22p
10k
0.1
100k
100k
0.1 0.1
0.1
1M
22
6.3V
0.1
0.1
100k 0
0
0
0
47k
0
R614 0
100k
CXR711260-218H2
MSM56X16160F-20T3
FE(A)
SE(B)
TE(F)
CE(E)
SFDR
SRDR
TFDR
TRDR
FFDR
FRDR
MDP
SYNC
POWERLT
SI0
SO0
XSCK0
COLDST
PG6
PG5
LCD_XRST
SEL_LINE_HP
OPEN
CHGMNT
BATMNT
AD_RMKEY
AD_KEY2
AD_KEY1
DCINMNT
CASINO_WAKE
XADEVENT
XRST
CLOCK_SHIFT
HOLD
X_METAL_DTC
PWMR
PWML
DAMPCLK
AOUTL
AOUTR
PWRSW
EN1
EN2
HP_LATCH
MUTE
SDA0
SDA1
SDA2
SDA3
SDA4
SDA5
SDA6
SDA7
SDA8
SDA9
SDA10
SDA11
SDCLK
SDCKE
SDXRAS
SDXCS
SDXCAS
SDUDQM
SDLDQM
SDDQ5
SDDQ1
SDDQ2
SDDQ3
SDDQ4
SDDQ6
SDDQ7
SDDQ8
SDDQ9
SDDQ10
SDDQ11
SDDQ12
SDDQ13
SDDQ14
SDDQ15
SDDQ16
LCD_XSCK_O
LCD_SDT_O
LCD_SDT_I
SI0
XSCK0
SO0
SI0
HP_LATCH
SEL_LINE_HP
AOUTR
AOUTL
BEEP
PWRSW
XRST
POWERLT
SO0
SXCK0
COLDST
XADEVENT
SYNC
CASINO_WAKE
MUTE
MDP
FG
SRDR
SFDR
TRDR
TFDR
FRDR
FFDR
LCD_SDT_I
LCD_SDT_O
LCD_XSCR_O
LCD_CS
LCD_XRST
AD_KEY2
AD_KEY1
CNGMNT
HOLD
OPEN
DCINMNT
AD_RMKEY
PG5
PG6
X_METAL_DTC
TSB
FE(A)
SE(B)
CE(E)
TE(F)
T+
T-
F-
F+
F+
F-
T+
T-
SDDQ1
SDDQ2
SDDQ3
SDDQ4
SDDQ5
SDDQ6
SDDQ7
SDDQ8
SDLDQM
SDXWE
SDXCAS
SDXRAS
SDXCS
SDA11
SDA10
SDA0
SDA1
SDA2
SDA3
SDDQ9
SDDQ10
SDDQ11
SDDQ12
SDDQ13
SDDQ14
SDDQ15
SDDQ16
SDUDQM
SDCLK
SDCKE
SDA4
SDA5
SDA6
SDA7
SDA8
SDA9
SDXWE
TSB
TU_CE
BATMNT
CLOCK_SHIFT
TC_CE
FG
BEEP
LCD_CS
OPGSW
A
B
RF
OPSTB
LD
PD
GND_A
VCC
E
F
F+
T-
T+
F-
F-
LINEOUT_DTC
TSB
LED1
LED2
D-R
GND_AU
D-L
AD_RMKEY
DCINMNT
VIN
OPEN
HOLD
VSTB1
VSTB2
CNGMNT
AD_KEY1
AD_KEY2
LCD_XRST
LCD_CS
LCD_CLOCK
LCD_DATA_O
LCD_DATA_I
FFDR
FRDR
TFDR
TRDR
SFDR
SRDR
FG
MDP
F+
T-
T+
MUTE
CASINO_WAKE
SYNC
WAKE
COLDST
CLOCK
LATCHB
GND
RSTB
VCC2
VAPC
PAPC
VCC0
VCC1
PWRSW
BEEP
A-L
A-R
GND
GND_A
SEL_LINE_HP
SI0/LCD_BL/XEXBAT
VG
TU_CE/OPOUT DTC
VCC
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
DQ8
VCCQ
LDQM
VSS
DQ16
DQ15
VSSQ
DQ14
DQ13
VCCQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VCCQ
NC
XWE
XRAS
XCS
A11
A10
A0
A1
A2
A3
VCC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
XCS
DO
WP
GND
VCC
HOLD
SCK
DI
-1-2
CLOCK SHIFT
XCAS
SD-RAM
EEPROM
HP_LATCH/DOUT
DATA_SO0
OPTICAL
PICK-UP
BLOCK
SYSTEM CONTROLLER,
DSP,LCD DRIVER
CSP
(Chip Size Package)
(DAX-25EV)
The components identified by mark 0or dotted
line with mark 0are critical for safety.
Replace only with part number specified.
Ver. 1.3
When EGL board is replaced or EEPROM (IC1602) on the EGL board is
replaced, patch processing is needed.
Confirmabout informationof patch processing to each serviceheadquarters.
1414
XP-ZR850
XP-ZR850
5-3. PRINTEDWIRING BOARD – JACK BOARD (COMPONENT SIDE) – :Uses unleaded solder.
• Semiconductor
Location
Ref. No.
Location
D401 H-8
D404 G-7
Q101 E-8
Q102 E-8
R102
C103
C102
C136
C161
CN602
CN603
L106
C145 C130
C129
C122
R115
R126
R120
R119
C126
C123
C128
C127
C116
C418
C414
CN901
L420
R471
L201
TH401
C403
FB405 FB404
S531
FB403
C406
C401
C201
C407
C502
C165
R501
VDR403
D401
C131
C408
R305
FB206
C210
D404
C133
C132
L107
Q102
C134
R118
R109
Q101
R114
R112
CT101
SL501
(OPEN)
C402
C146
L108
C423
C421
L414
L413
1
1
4
2
1
30
31
60
OPEN
1
V
WU
4
M603
(SLED)
M
M602
(SPINDLE)
TP101
(RF (A) )
TP103
(RFGND (A) )
TP215
(TU_R )
TP217
(TU_L)
EGL
BOARD
CN9001
(Page 12)
A
B
C
D
E
F
G
H
I
J
123456789 10
A
1-864-028- (13)
13
JACK BOARD
(COMPONENT SIDE)
1515
XP-ZR850
XP-ZR850
5-4. PRINTEDWIRING BOARD – JACK BOARD (CONDUCTOR SIDE) – :Uses unleaded solder.
• Semiconductor
Location
Ref. No.
Location
D101 C-2
D105 D-2
D106 D-3
D107 A-7
D108 B-7
D202 I-4
D203 I-4
D204 I-4
D402 F-7
D403 F-6
D411 C-7
D412 C-8
D413 C-8
D414 E-8
D415 E-8
IC101 E-3
IC201 G-3
IC401 E-7
IC501 F-6
Q103 E-4
Q104 B-10
Q401 D-8
Q403 E-6
Q402 E-6
Q404 F-6
Q410 C-9
Q411 C-9
1-864-028- (13)
13
(AEP)
(AEP)
1
12
1
4
8
5
C106 R101
R111
C120
C119
R125
C150
C118
C138
C142
C143
C125
C117
R110
R212
R211
R213
R214
R215
R221
R217
R216
R220
C228
R210
C229
C230 C234
C231
C235
C232 C226
C225
C220
C218
C215
C212
C211
R202
FB205
FB203
R201 C205
D204
D202
D203
FB204
C206
C202
C227
C224 C219
C217
C216
C221 R232
R231
C223
R230
C115
C121
C113
C114
R132
D105
C101
C104
S530
R107 C162
R130
R128
Q103
C156
C140
C135
C137
C141
R129
R131
R116
C164
L105
D106
D101
C110
R104
C148
C233
C155
TP102
(RF (B) )
R801
R802
R404
R405
R411
R466
R473
R474
R502
C501
R452
C454 C437
C410
R455
R477
R470
R469
C405
D402
Q402
R451
IC501
IC401
R476
R420
R412
L412
L411
L418
C438 C411
C412
C413
C442
C452
R464
R415
C433 L416
C431 C428
R419
L415 L419
R408
FB806
F401
R486 R478
R481
C432
C429
R124
C147
C144
R123
R121 R122
C139
C163
R482
C443
R414
R413
R467
R468 C435
C434
R475
R484 R479
R480
R454
FB801
FB802
FB803
FB804
C803
C804
C805
FB805
FB808
R418
R416
C415
R463
R407 C450
C416
CN801
C420 C417
C456
C419
L417
FB807
D412
D413
D414
D415
Q401
Q410
Q411
D108
D107
Q104
C409
C426
C436
C455
R410
R465
R483
R485
RV401
D403
Q404
Q403
D411
C404
R803
R804
IC201
111
12
23 22
33
34
44
IC101
1
3
6
4
HOLD
HOLD
OFF
T102
CF102
CF101
L101
AM
FERRITE-ROD
ANTENNA
L104
CF104
CF103
1
3
FL102
T103
DC/DC
CONVERTER
DC IN 3V
–+
J402
J301
i
T101
(AEP,E19)
(AEP,E19)
-1
-2
B
SWITCH
BOARD
CN1002
(Page 17)
TP454
TP111
(VT)
TP104
(RFGND (B) )
A
B
C
D
E
F
G
H
I
1 2 3 4 5 6 7 8 9 10
J
115
16
30
1
20
21 40
41
60
61
80
DRY BATTERY
SIZE “AA”
(IEC DESIGNATION LR6)
1PC. 1.5V
RECHARGEABLE
BATTERY
NH-AA-B2D
1PC. 1.2V 2300 mAh
JACK BOARD (CONDUCTOR SIDE)
Ver. 1.1
1616
XP-ZR850
XP-ZR850
5-5. SCHEMATIC DIAGRAM – JACK BOARD – • See page 11 forWaveforms. • See page 19 for IC Block Diagrams. • See page 20 for IC Pin Function Description.
(Page 13)
(Page 18)
IC201
R413
C211
C212
C220
C221
R201 R202
C206
D205
C219
TH401
D204
C218C217
C216
C205
R408
R107 C113
C150 R125
C164
C119
C120
R112
R115
R114
C139
R121
D108
R122
C146 C147 R124
C502
R502
C501
IC501
C102
C103
R101
R102
C106
D101
C233
C148
C121 C122
R129
R131
R118
R116
C138
C142
C162
C143
C140
C141
C137
C135
C134
C132
R119
C123
R109
C116
R132
C104
C101
C131
C117
R110
R128
C156
C228
R231
R230
C223
C227
C224
C406
C161
C401
FB403
C408
R404 C404
R466
R411
D403 R410 R476 RV401
Z403
C225
C226
D404
C235
R216
R220
R217
R221
R215
C234
R214
C229
C230
C231
C232
C145
C163
R481R482
R478
R484
Q410
C423
C428
C436
C426
C429
R464
C411
C412
C413
C438 R412
C405
C410
R407
R451
R477
R471
R455
C437
R416
C415
C435
C434
C421
C443
R467
D412
C417
C420
R463 C450
R418
CN801
CN603
D105
D106
C118
C144
T103 Q104
R123
R111
L108
S530
S531 SL501
T101
L104
FM
RF
C114
L106
IC101
C126
Q102
C125
L107
T102
CF101
C165
C201
C210
C215
L201
47µH
C202
D202
FB206
FB203
FB205
FB204
R232
F401
FB404
FB405
C403
D401
C407
J402 R405
R213
R211
R210
R212
C409
L415
L416
R419
D411
R414
C452
C431
C432
C433
R415
R452
D402
Q402
L418
C442
L414
R475
Q401
R454
D415
C418
D413
L413
C456
L417
D414
C419
R470
Q404
C454
R474
R473
L411L412
CN602
C414
M603
M
6
FB801
FB802
FB803
FB804
FB805
FB806
FB807
FB808
R469
L420
TP111
R130
C110
C155
R104
L101
CT101
C136
Q101
C129
C130
R126
C128
C127 C133
R120
C115
CF103
CF104
Q103
J301
Q411
L419
R468
IC401
FL102
L105
TP454
TP101
TP102
TP103 TP104
TP217
TP215
C402
VDR403
R420
Q403
R465
R483
R485
CF102
C455
R486
R479
R480
C416
R804
R803
R802
R801
C805
C804
CN901
C803
R501
D107
R305
TB2173FTG
47k
1
0.47
4.7
2.2
2.2 2.2
0.22
MA3J14700LSO
10
RSB6.8STE61
0.222.2
0.22
0.22
2.2M
470k 0.01
4p 4.7k
0.01
47p
100p
0
47k
22k
0.01
10k
1SS355TE-17
1k
4.7 0.01 220
4700p
1M
470p
RT8H055C
2200p
0.022
470k
1k
0.1
KV1610S
220p
0.022
0.01 4.7
4V 220
220
10k
4.7k
1
10p
5p
22p
0.47
0.47
0.022
0.022
0.1
0.1
2.2k
4.7 4V
10
47
4V
0
5p
220p
220p
0.1
470
4.7k
1
10
100k
100k
0.47
2.2
2.2
0.1
0.01
1
0
4.7
220k 0.22
220
47k
UDZSTE-174.7B 100k 100k 47k
0.22
0.47
RB521S-30FTE61 1000p
22k
47k
4.7k
47k
22k
1000p
4.7k
0.47
0.47
1
1
10
6.3V
100p
1k4.7
10k
0
2SC4154TP-IF
100 4V
47 6.3V
0.1
0.22
47
6.3V
10k
0.01
0.01
0.01
0.22 4.7k
10
0.01
100
100k
0
2.2k
100k
1
100
470p
1000p
220p
100
6.3V
0.01
220
RB521S
-30FTE61
0.47
1
100 100p
220
12P
2P
HVC306CTRU
HVC306
CTRU
0.01
5p
2SC4154TP-1F
100k
10k
AM OSC
0.01
TB2132FNG
470p
DTA114TUA-T106
0.1
1000p
1000p
220 4V
1
0.01
RSB6.8STE61
0
0
1.4A
32V
1
MA22D28
00LS0
147k
10
MA785-TX,(SO)
0
2.2
2.2
47
6.3V
4.7
47k
0
MA2YD23
00LS0
2SA1363
-T111-1E
47
6.3V
22k
NTHD4508N
0
UDZSTE-175.6E
47
4V
RB521S
-30FTE61
0.01
MA22D2800LS0
100
6.3V
0
DTC115TE
10
0
100k
4P
1000p
1k
(VT)
220
47p
100p
470k
2.2
2SK3019TL
0.01
0.22
47k
0.1
0.01 1
1k
1000p
75KHz
2SA2018TL
220
SC901591AFR2
27nH
(RF(A))
(RF(B))
(RFGND(A)) (RFGND(B))
220
6.3V
220
2SD2652-T106
0.47
0.47
0.22
1000p
47k
47k
22k
0.47
2p
2p
60P
100p
4.7k
MA8130-TX
0
HP_LATCH
DATA_SO0
CLOCK
A_MUTE
HP_PWR
BEEP
CD_R
CD_L
DCINMT
TU_CE
CLOCK
SI0
OPEN CASINO_WAKE
PAPC
VAPC
MDP
FG
AD_RMKEY
RS
COM
U
V
W
F+
F-
T-
T+
S-
S+
LATCH_B
CHGMNT
SFDR
SRDR
VG
TFDR
TRDR
FFDR
FRDR
RS
DATA_SO0
CLOCK
COLDST
WAKE
SYNC
RSTB
LCD_CLK
LCD_CS
DATA_O
DATA_I
LCD_XRST
AD_KEY1
AD_KEY2
AD_RMKEY
DCINMT
OPEN
HOLD
CHGMNT
FFDR
FRDR
TFDR
TRDR
SFDR
SRDR
FG
MDP
F+
F-
T-
T+
A_MUTE
WAKE
COLDST
CLOCK
DATA_SO0
RSTB
PAPC
HP_PWR
BEEP
CD_L
CD_R
HP_LATCH
VG
TU_CE
CASINO_WAKE
SYNC
HOLD
V
U
S+
S-
COM
W
VAPC
AD_RMKEY
SI0
LATCH_B
DATA_SO0
DATA_I
AD_KEY1
AD_KEY2
LCD_XRST
LCD_CS
LCD_CLK
DATA_O
CHGSW
CHGSW
∗
∗
∗
∗
∗
∗
∗
∗
IF
NC
VIN
VCC
GND
OUT
P2
P1
OUT-L
OUT-C
PW-GND
BP-L
OUT-R
BP-R
VCC2
BST-TC
AGC_I
BST_O
PNF-R
PNF-L
VDD
STB
DATA
CK
RESET
LPF2
BST-NF
LPF1
BIAS-O
RF
OUT-ADJ
BIAS-I
VCC1
BEEP-I
PW-SW
MUTE-SW
MUTE-T
MODE-T
FM-RF_O
FM/TV_I
GND
RF-VCC
AM-RF
FM/TV-OSC
AM-OSC
TU-CE
CLK
MIX_O
FM-IF_I
AGC
VCC
AM-IF_I
QUAD
DET-O
MPX_IN
VDD
LPF1
LPF2
DO
D_I/O
TV_O
L_O
FM_O
R_O
D-GND
X_O
X_I
C-SW
GND
TU-L
V_O-L
P_I-L
P_I-R
V_O-R
TU-R
CD-L
PRE-GND
RF
INM
PAPC
VAPC
GND
VREF
VIN
SW
VCP
VCC2
VSTB2
VSTB1
VCC1
APWM
PWM
FG
RMCRB
CPUI
CPVI
CPWI
COM
VMVW
GNDW
VMU
GNDUV
FO3
VM3
RO3
RO2
VM2
FO2
HBGND12
HBGND23
RO1
VM1
FO1
HBGND1
TEST
RSTB
SYNC
WAKE
COLDST
CLOCK
DATA_SO0
LATCHB
EXTRSTB
DCIN
CRF
CINM
BATM
CHGSW
RSOSCR
OSCC
R13
F13
R12
F12
INPVD
INP0
VD
VDLX
VD_T
VD_B
VCC0
L0_1
L0_2
PGND1
PGND2
C1L
C1H
CINP
VG
CHGMON
FI1
RI1
W
VU
COM
CLK_I
LCD_CS_I
DATA_O
DATA_I
VCC0_+2.7V
AD_KEY1
AD_KEY2
PS
SGND
LINEOUT_DTC
TSB
LED1
LED2
D-R
GND_AU
D_L
AD_RMKEY
DCINMNT
VIN
OPEN
HOLD
VSTB1
VSTB2
CHGMNT
AD_KEY1
AD_KEY2
LCD_XRST
LCD_CS
LCD_CLOCK
LCD_DATA_O
LCD_DATA_I
FFDR
FRDR
TFDR
TRDR
SFDR
SRDR
FG
MDP
F+
F-
T-
T+
MUTE
CASINO_WAKE
SYNC
WAKE
COLDST
CLOCK
DATA_SO0
LATCHB
GND
RSTB
VCC2
VAPC
PAPC
VCC0
VCC1
PWRSW
BEEP
A-L
A-R
GND
GND_A
SEL_LINE_HP
HP_LATCH/DOUT
VG
TU_CE/OPOUT_DTC
COM
W
V
U
S+
S-
DC/DC
CONVERTER
DC/DC
CONVERTER
S
LOW-PASS
FILTER
HOLD
HOLD
OFF
OPEN (OPEN)
VOLTAGE DETECT
AM
ANTENNA
FERRITE-ROD
1
FM/AM IF AMP,
FM/AM DET
FM MPX,PLL
TV-RF_O
TONE CONTROL
SWITCH
AM IFT
HEADPHONE AMP
AGC-D
DRY BATTERY
SIZE"AA"
(IEC DESIGNATION LR6)
DC IN 3V
∗R211,212
CD-R
-1-2
UMT1N-TN
Q410,411
RIPPLE
FILTER
S
S
SWITCHING
SIO/LCD_BL/XEXBAT
(SLED)
(
SPIND
L
LCD_XRST_I
VCC2_+2.1V
D_GND
2
3
FOCUS/TRACKING COIL DRIVE,
SPINDLE/SLED MOTOR DRIVE,
POWER CONTROL
L101
B+ SWITCH
B+ SWITCH
B+ SWITCH
CPV0
VO0
WO
VO
UO
(TU_L)
(TU_R)
(AEP)
CHARGE SWITCH
∗R210,213
1K(AEP)
4.7K(E19)
(AEP,E19)
47K(E/4,E92,MX)
4.7K(AEP,E19)
∗R801
1K
2.2K
∗R802,803
2.2K
4.7K
∗R804
470
1K
(AEP)
(EXCEPT AEP)
(AEP)
(EXCEPT AEP)
(AEP)
(EXCEPT AEP)
FM RF AMP,
FM/AM MIX AMP,
FM/AM OSC,
1PC. 1.5V
RECHARGEABLE BATTERY
NH-AA-B2D
1PC. 1.2V 2300mAh
47µH
10µH
100µH
10µH
47µH
47µH47µH
47µH
22µH
10µH
47µH
47µH
The components identified by mark 0or dotted
line with mark 0are critical for safety.
Replace only with part number specified.
Ver. 1.1
1717
XP-ZR850
XP-ZR850
5-6. PRINTEDWIRING BOARD – SWITCH BOARD – :Uses unleaded solder.
R1113
S1007
C1001
VDR1001
R1104
R1108
R1107
R1110
R1111
R1112
S1011
S1010
S1005
S1004
S1008
S1003
S1001
R1005
R1004
R1003
R1002
R1001
CN1002
R1135
R1102
R1103
R1101
R1105
R1109
R1114
R1106
S1009
C1008
CN1001
C1007
C1006
C1003
C1004
C1005
C1010
C1011
C1012
C1002
SWITCH BOARD
1-864-579-
123
LCD1001
LIQUID CRYSTAL DISPLAY
B
JACK
BOARD
CN601
(Page 15)
1
12
–
v
VOL+ +
VOL–
V
u
ENTER
DISPLAY
MENU
>B
SEARCH
b.
RADIO OFF/CHG
x
A
B
C
D
E
F
G
1 2 3 4 5 6 7 8
(12)
12
TUNE –
S1002
TUNE +
S1006
BAND
MEMORY
RADIO ON
R1131
C1014
C1013
1818
XP-ZR850
XP-ZR850
5-7. SCHEMATIC DIAGRAM – SWITCH BOARD –
(Page 16)
C1007
R1001
R1002
R1003
R1004
R1005
R1101
R1102 R1103
R1104
R1105
R1107
R1108 R1110
R1111
R1112
CN1002CN1001
VDR1001
R1109
R1113
R1114 R1106
C1002
C1001
S1005
S1004S1003
S1011
S1010 S1009 S1007
C1012
C1003
C1011
C1004
C1010
C1005
C1006
C1008
R1131
R1135
S1006
S1008
S1001 S1002
C1013 C1014
0.22
1k
1k
1k
1k
1k
10k
4.7k 2.2k
22k
2.2k
10k
22k 2.2k
2.2k
22k
12P23P
1k
47k
4.7k 4.7k
0.1
0.1
0.22
0.22
0.22
0.22
0.22
0.22
0.22
0.47
100
0
100p 100p
SCK
CSB
SDI
SDO
RSTB
VDD
VSS
VREF
VCIN
CP1
CN1
CP2
CN2
CP3
CN3
VSSL
VCOUT
VLCIN
V1
V2
V3
V4
V5
CLK_I
LCD_CS_I
DATA_O
DATA_I
LCD_XRST
D_GND
AD_KEY1
AD_KEY2
PS
SGND
SEARCH
-
ENTER
VOL -
VOL +
DISPLAY
MENU
LCD1001
LIQUID
CRYSTAL
DISPLAY
VCC2_+2.1V
VCC0_+2.7V
RADIO ON
BAND
MEMORY
RADIO OFF/CHG
TUNE - TUNE +
+
Ver. 1.1
19
XP-ZR850
•IC Block Diagrams
– JACK Board –
IC101 TB2132FNG
IC201 TB2173FTG
FM/TV RF IN
1
MIX OUT
3
GND
2
AGC
4
FM IFIN
5
FM
RF
TV
RF
FM/TV
MIX
AM
MIX
27
AM RFIN
17
PLL GND
21
PLL VCC
18
OUT1 (ST)
26
FM/TV OSC
28
RF VCC
29
TV RFOUT
30
FM RFOUT
FM
IF
AM IFIN
7
VCC
6
DET OUT
9
QUAD
8
MPX IN
10
LPF1
11
LPF2
12
AM
IF
AM
DET
FM
DET
L-CH
13
R-CH
14
XO
15
IF
BUFFER
AF
FM MPX
MUTE
OSC
25
AM OSC
16
XI
AM
OSC
1/2
1/4
1/16
AM
TV 1/8
FM 1/32
FM/TV 1/2
BUFFER
AM OSCIN
FM OSCIN
PROGRAM
COUNTER
REFERENCE
DIVIDER
IFIN
1/8
AM FM
FM/AM/TV
SWITCH
22
DATA
19
OUT2 (DO2)
20
DO
PHASE
COMPARATOR
23
CK
24
CE
PLL
AGC
34
MUTE SW
C-SW
OUTA
MODE
SWITCH
VOLUME
VOLUME/SWITCH
/PORT CONTORL
2
35
PW SW
36
RESET
37
CK
38
DATA
39
STB
43
P1
44
P2
40
VDD
41
PRE NFA
33
IN2A
31
PRE INA29
PRE INB28
VOL OUTA30
VOLUME IN2B
26
IN1A
25
VOL OUTB
27
GND
32
PRE GND
MODE TC
23
+
–
+
–
42
PRE NFB
BEEP OUTA 1
BEEP OUTB 6
VCC2 7
BST TC 8
AGC DET 9
AGC IN 10
OUTC 3
PW GND 4
OUTB 5
ATTENUATOR
IN1B
24ATTENUATOR
22
MUTE TC
21
BEEP
20
VCC1
19
BIAS IN
18
BEEP
OUT ADJ
17
RF
16
LPF1
14
LPF2
12
BST NF
13
BIAS OUT
15
BIAS
+
–
+
–
+
–
BST AGC
BST OUT 11
PORT
20
XP-ZR850
Pin No. Pin Name I/O Description
1PE6/SI1 I Serial data input from the liquid crystal display
2PE5/SO1 O Serial data output to the liquid crystal display
3 PE4/XSCK1 O Serial clock signal output to the liquid crystal display
4PE3 O Chip select signal output to the EEPROM
5VDIO0 — Power supply terminal (+2.1V)
6VSS0 — Ground terminal
7DVDD7 — Power supply terminal (+1.3V)
8PE2/DTCK I/O Not used
9PE1/RXD0 I Not used
10 PE0/TXD0 O Not used
11 EVA — Not used
12, 13 SDDQ16, SDDQ15 I/O Two-way data bus with the SD-RAM
14 TAPTDO — Not used
15, 16 SDDQ14, SDDQ13 I/O Two-way data bus with the SD-RAM
17 SCANEN — Not used
18, 19 SDDQ12, SDDQ11 I/O Two-way data bus with the SD-RAM
20 TEST2 — Not used
21, 22 SDDQ10, SDDQ8 I/O Two-way data bus with the SD-RAM
23 VDIOSD0 — Power supply terminal (+2.7V)
24 VSS1 — Ground terminal
25 to 28 SDDQ9, SDDQ6, I/O Two-way data bus with the SD-RAM
SDDQ7, SDDQ2
29 TEST3 — Not used
30, 31 SDDQ4, SDDQ3 I/O Two-way data bus with the SD-RAM
32 TEST0 — Not used
33 XSDWE O Write enable signal output to the SD-RAM
34 SDDQ1 I/O Two-way data bus with the SD-RAM
35 TEST1 — Not used
36 SDDQ5 I/O Two-way data bus with the SD-RAM
37 SDLDQM O Lower byte input/output mask signal output to the SD-RAM
38 VDIOSD1 — Power supply terminal (+2.7V)
39 VSS2 — Ground terminal
40 SDUDQM O Upper byte input/output mask signal output to the SD-RAM
41 XSDCAS O Column address strobe signal output to the SD-RAM
42 XSDCS O Chip select signal output to the SD-RAM
43 TEST5 — Not used
44 XSDRAS O Row address strobe signal output to the SD-RAM
45 SDCKE O Clock enable signal output to the SD-RAM
46 TEST6 — Not used
47 SDCLK O Clock signal output to the SD-RAM
48 SDA13 O Address signal output to the SD-RAM
49 XTRST — Not used
50 to 52 SDA12 to SDA10 O Address signal output to the SD-RAM
53 VDIOSD2 — Power supply terminal (+2.7V)
54 VSS3 — Ground terminal
55 DVDD0 — Power supply terminal (+1.3V)
56 TMS — Not used
• IC Pin Function Description
EGL BOARD IC603 CXR711260-218H2 (SYSTEM CONTROLLER, DSP, LCD DRIVER)
Ver. 1.3
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