Alinco Dr-235tmkiit User manual

DR-235TMkIIT

Service

Manual

CONTENTS

SPECIFICATIONS

PARTS

LIST

GING

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ciccrcaccadaviehareseedineyteuseed

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TRANSMIT

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ER:

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22-25

RECEIVE

Riscse2.dscaceratconssoce

races

2

Mechanical

Parts...............cccceceeeeeeees

25

Packing

Parts.........ccccsssccesseseeneenecnens

25

CIRCUIT

DISCRIPTION

ACCESSORIES

oy

seieswestcnutiaseueteiotenes

25

1)

Receiver

System

DR-235.............ccceeseeeeens

3,4

ACCESSORIES

(SCREW

SET)...........

25

2)

Transmitter

System

DR-235............0cceeeeees

4

TING

(dG)

oan

cau

eieeavaireaineesoninevaass

26

3)

PLL

Synthesizer

Circuit

DR-235................0.

5

TNC

(EJ41U)

Packing

Parts................

27

4)

CPU

and

Peripheral

Circuit........................

5,6

-

5)

Power

Supply

Circuit.......00.....000.:cccce

eee

6

DR-235

ADJUSTMENT

6)

M38268MCAO75GP

(XA1130)..........0....0..

7-9

1)

Adjustment

Spot................ccccee

eee

ee

eee

28

2)

VCO

and

RX

Adjustment

Specification...

29

SEMICONDUCTOR

DATA

3)

TX

Adjustment

Specification...............

30

1)

NJM7808FA

(XA0102)...........ccceceeeeceseeeeees

10

4)

RX

Test

Specification...........

eee.

31

2)

TC4S66F

(XA0115)..........cccseccecceesserecceeees

10

5)

TX

Test

Specification..............ccccceees

32

3)

AN8010M

(XA0119).............ccccecscscesessseers

10

4)

TC4W53FU(XA0348).....6...cccceeceeeeeeeeeeees

10

PC

BOARD

VIEW

5)

TA31136FN

(XA0404)...0.

0

cece

eee

ee

eee

11

1}

CPU

Unit

Side

A

DR-235

(UP0579)......

33

6)

LA4425A

(XA0410)........

cee

ces

cece

e

cee

ee

eee

eees

11

2)

CPU

Unit

Side

B

DR-235

(UP0579)......

33

7)

BR24L32FJ

(XAQ604Z).........

00.

cccec

cee

eee

scene

11

3)

MAIN

Unit

Side

A

DR-235

(UP0579).....

34

8)

L88MSOS5TLL

(XA0675).............

cc

ccec

ees

ee

eens

12

4)

MAIN

Unit

Side

B

DR-235

(UP0579)....

34

9)

S-816A50AMC

(XAQ9Q25).......000ccceseee

cesses

12

5)

TNC

Unit

Side

A(UP0402)

(option)......

35

10)

LM2904PWR

(XA1103)...........ccececeece

eee

eeees

12

6)

TNC

Unit

Side

B

(UP0402)

(option)......

35

14)

LM2902PWR

(XA1106).............e

cece

ee

eens

12

12)

MB15E07SR

(XA1107).......0....ccecee

eee

eeeee

13.

SCHEMATIC

DIAGRAM

13)

S-80845CLNB

(XA1120)...........ccceccecneeeeens

14

1)

CPU

Unit

DR-235.............

cee

cece

eee

36

14)

BU4052BCFV

(XA1229)........

cece

eseecavenens

14

2)

MAIN

Unit

DR-235.....0..0...

eee

cece

eee

es

37

45)

-S=AVAO

(KA

T2380

Msi

cectcwadwigiesaisetouces

ness

15

3)

TNC

Unit

(option)..................

cee

38

16}

Transistor,

Diode

and

LED

Outline

Drawing...

16

17)

LCD

Connection

(TTR3626UPFDHN)..........

17

BLOCK

DIAGRAM

BY

DR

20565

Baste

crake

nee

39

EXPLODED

VIEW

1)

LCDASSEMbDIY..............cccccceccesensceseeeeeees

18

2)

Top

and

Front

View...............c.cccceseeseee

eens

19

SO)

BOUGHT

VIOW:

cvisicticsscn

ais:

seeds

seccdcecatuesevaees

20

ALINCO,

INC.

SPECIFICATIONS

m@

General

DR-235

cs

ORB

idl

216.000

~

279.995MHz

(

RX

)

222.000

~

224.995MHz

(

TX

)

Number

of

memory

7

13.8V

DC

+/- 15%

(11.7

~

15.8

V

Transmit

H

Transmitter

Output

power

—

Hi

Mid

Low

Maximum

Frequency

+/-5kHz(

Wide

mode)

+/-

2.5kHz

(

Narrow

mode

)

deviation

M

Receiver

Inter-modulation

—_

rejection

60

dB

Spurious

and

image

rejection

ratio

Audio

output

power

70

dB

2.0

W

(80hm

,

10

%

THD

)

!

NOTE

:

All

specifications

are

subject

to

change

without

notice

or

obligation.

CIRCUIT

DESCRIPTION

1)

Receiver

System

DR-

235

The

receiver

system

is

a

double

superheterodyne

system

with

a

30.85

MHz

first

IF

and

a

455

kHz

second

IF.

1.

Front

End

2.

IF

Circuit

3.

Demodulation

Circuit

4.

Audio

Circuit

The

received

signal

at

any

frequency

in

the

216.000MHz

to

279.995MHz

range

is

passed

through

the

low-pass

filter

(L116,

L115,

L114,

L113,

C204,

C203,

C202,

C216

and

C215)

and

tuning

circuit

(L105,

L104

and

D105,

D104),

and

amplified

by

the

RF

amplifier

(Q107).

The

signal

from

Q107

is

then

passed

through

the

tuning

circuit

(L103,

L107,

L102,

and

varicaps

D103,

D107

and

D102)

and

converted

into

30.85

MHz

by

the

mixer

(Q106).

The

tuning

circuit,

which

consists

of

L105, L104,

varicaps

D105

and

D104,

L103,

L107,

L102,

varicaps

D103,

D107

and

D102,

is

controlled

by

the

tracking

voltage

form

the

VCO.

The

local

signal

from

the

VCO

is

passed

through

the

buffer

(Q145),

and

supplied

to

the

source

of

the

mixer

(Q106).

The

radio

uses

the

lower

side

of

the

superheterodyne

system.

The

mixer

mixes

the

received

signal

with

the

local

signal

to

obtain

the

sum

of

and

difference

between

them.

The

crystal

filter

(XF101A,

XF101B)

selects

30.85

MHz

frequency

from

the

results

and

eliminates

the

signals

of

the

unwanted

frequencies.

The

first

IF

amplifier

(Q105)

then

amplifies

the

signal

of

the

selected

frequency.

After

the

signal

is

amplified

by

the

first

IF

amplifier

(Q105),

it

is

input

to

16

of

the

demodulator

IC

(IC108),

The

second

local

signal

of

30.395

MHz

,

which

is

oscillated

by

the

internal

oscillation

circuit

in

1C108

and

crystal

(X104),

is

input

through

1

of

[C108.

Then,

these

two

signals

are

mixed

by

the

internal

mixer

in

1C108

and

the

result

is

converted

into

the

second

IF

signal

with

a

frequency

of

455

kHz.

The

second

IF

signal

is

output

from

3

of

1C108

to

the

ceramic

filter

(FL101

or

FL102),

where

the

unwanted

frequency

band

of

that

signal

is

eliminated,

and

the

resulting

signal

is

sent

back

to

the

1C108

through

pins

5.

The

second

IF

signal

input

via

5

is

demodulated

by

the

internal

limiter

amplifier

and

quadrature

detection

circuit

in

1C108,

and

output

as

an

audio

signal

through

9.

The

audio

signal

from

9

of

[C108

is

amplified

by

the

audio

amplifier

(1C120:A),and

switched

by

the

signal

switch

IC

(IC111}

and

then

input

it

to

the

de-emphasis

circuit.

and

is

compensated

to

the

audio

frequency

characteristics

in

the

de-emphasis

circuit

(R203,

R207, R213,

R209,

C191,

C218,

C217)

and

amplified

by

the

AF

amplifier

(1C120:B).

The

signal

is

then

input

to

volume

(VR1)

.

The

adjusted

signal

is

sent

to

the

audio

power

amplifier

(IC717)

through

1

to

drive

the

speaker.

5.

Squeich

Circuit

6.

AIR

Band

Reception

7.

WIDE/NARROW

Switching

circuit

2)

Transmitter

System

DR-

1.

Modulator

Circuit

2.

Power

Amplifier

Circuit

3.

APC

Circuit

The

detected

output

which

is

outputted

from

the

9

of

1C108

is

inputted

to

8

of

IC108

after

it

was

been

amplified

by

1C120:A

and

it

is

outputted

from

14

after

the

noise

component

was

been

eliminated

from

the

composed

band

pass

filter

in

the

built

in

amplifier

of

the

IC.

The

adjusted

voltage

level

at

VR101

is

delivered

to

the

comparator

of

the

CPU.

The

voltage

is

led

to

2

of

CPU

and

compared

with

the

setting

voltage.

The

squelch

will

open

if

the

input

voltage

is

lower

than

the

setting

voltage.

During

open

squelch,

30

(SQC)

of

the

CPU

becomes

"L”

level,

AF

control

signal

is

being

controlled

and

sounds

is

outputted

from

the

speaker.)

lf

it

is

made

air

band

receiving

mode,

IF

signal

is

demodulated

by

AM

decoder

of

1C108,

and

is

output

from

pin12

as

the

AF

signal.

The

2nd

IF

455

kHz

signal

which

passes

through

filter

FL101

(wide)

and

FL102

(narrow)

during

narrow,

changes

its

width

using

the

width

contro!

switching

D115

and

D116.

235

The

audio

signal

is

converted

to

an

electrical

signal

by

the

microphone,

and

input

it

to

the

microphone

amplifier

(Q6).

Amplified

signal

which

passes

through

mic-mute

control

IC109

is

adjusted

to

an

appropriate

mic-volume

by

means

of

mic-gain

adjust

VR7106.

IC114:C

and

D

consists

of

four

operational

amplifiers;

one

amplifier

(pins

12, 13,

and

14)

is

composed

of

pre-emphasis

and

IDC

circuits

and

the

other

(pins

8,

9,

and

10)

is

composed

of

a

splatter

filter.

The

maximum

frequency

deviation

is

obtained

by

VR107.

and

input

to

the

signal

switch

(1C113)

(9600

bps

packet

signal

input

switch)

and

input

to

the

cathode

of

the

varicap

of

the

VCO,

to

change

the

electric

capacity

in

the

oscillation

circuit.

This

produces

the

frequency

modulation.

The

transmitted

signal

is

oscillated

by

the

VCO,

amplified

by

the

drive

amplifier

(Q145)

and

younger

amplifier

(Q115),

and

input

to

the

final

power

module

(IC110).

The

signal

is

then

amplified

by

the

final

power

module

(1C110)

and

led

to

the

antenna

switch

(D110)

and

low-pass

filter

(L113,

L114,

L115,

L116,

C215,

C216,

C202,

C203

and

C204),

where

unwanted

high

harmonic

waves

are

reduced

as

needed,

and

the

resulting

signal

is

supplied

to

the

antenna.

Part

of

the

transmission

power

from

the

low-pass

filter

is

detected

by

D111,

converted

to

DC.

The

detection

voltage

is

passed

through

the

APC

circuit

(IC114:A,1C114:B),

then

it

controls

the

APC

voltage

supplied

to

the

younger

amplifier

Q115

and

the

final

power

module

IC110

to

fix

the

transmission

power.

3)

PLL

Synthesizer

Circuit

DR-

235

1.

PLL

2.

Reference

Frequency

Circuit

3.

Phase

Comparator

Circuit

4,

PLL

Loop

Filter

Circuit

5.

VCO

Circuit

The

dividing

ratio

is

obtained

by

sending

data from

the

CPU

(IC1)

to

10

and

sending

clock

pulses

to

9

of

the

PLL

IC

(IC116).

The

oscillated

signal

from

the

VCO

is

amplified

by

the

buffer

(Q134

and

Q135)

and

input

to

8

of

1C116.

Each

programmable

divider

in

IC116

divides

the

frequency

of

the

input

signal

by

N

according

to

the

frequency

data,

to

generate

a

comparison

frequency

of

5

or

6.25

kHz.

The

reference

frequency

appropriate

for

the

channel

steps

is

obtained

by

dividing

the

12.8

MHz

reference

oscillation

(X102)

by

4250

or

3400,

according

to

the

data

from

the

CPU

(IC1).

When

the

resulting

frequency

is

5

kHz,

channel

steps

of

5,

10, 15,

20, 25,

30,

and

50

kHz

are

used.

When

it

is

6.25

kHz,

the

12.5

kHz

channel

step

is

used.

The

PLL

(IC116)}

uses

the

reference

frequency,

5

or

6.25kHz.

The

phase

comparator

in

the

1C116

compares

the

phase

of

the

frequency

from

the

VCO

with

that

of

the

comparison

frequency,

5

or

6.25kHz,

which

is

obtained

by

the

internal

divider

in

IC116.

If

a

phase

difference

is

found

in

the

phase

comparison

between

the

reference

frequency

and

VCO

output

frequency,

the

charge

pump

output

(pin

5)

of

IC116

generates

a

pulse

signal,

which

is

converted

to

DC

voltage

by

the

PLL

loop

filter

and

input

to

the

varicap

of

the

VCO

unit

for

oscillation

frequency

control.

A

Colpitts

oscillation

circuit

driven

by

Q131

directly

oscillates

the

desired

frequency.

The

frequency

control

voltage

determined

in

the

CPU

(IC1)

and

PLL

circuit

is

input

to

the

varicaps

(D122

and

D123).

This

change

the

oscillation

frequency,

which

is

amplified

by

the

VCO

buffer

(Q134)

and

output

from

the

VCO

area.

4)

CPU

and

Peripheral

Circuits

1.

LCD

Display

Circuit

2.

Dimmer

Circuit

3.

Reset

and

Backup

The

CPU

turns

ON

the

LCD

via

segment

and

common

terminals

with

1/4

the

duty

and

1/3

the

bias,

at

the

frame

frequency

is

64Hz.

The

dimmer

circuit

makes

the

output

of

13

of

CPU

(IC1)

into

"H"

level

at

set

mode,

so

that

Q9

and

Q3

will

turn

ON

to

make

the

lamp

control

resistor

R84

short

and

make

its

illumination

bright.

But

on

the

other

hand,

if

the

dimmer

circuit

makes

13

into

"L"

level,

Q9

and

Q3

will

turn

OFF,

R84's

illumination

will

become

dimmer

as

its

hang

on

voltage

falls

down

in

the

working

LED

(D11,

D2,

D5,

D3

and

D6).

When

the

power

form

the

DC

cable

increases

from

Circuits

0

V

to

2.5

or

more,

"H"

level

reset

signal

is

output

form

the

reset

IC

(iC4)

to

33

of

the

CPU

(IC1),

causing

the

CPU

to

reset.

The

reset

signal,

however,

waits

at

100,

and

does

not

enter

the

CPU

until

the

CPU

clock

(X1)

has

stabilized.

4.

S

(Signal)

Meter

Circuit

5.

DIMF

Encoder

6.

Tone

Encoder

-

7.

DCS

Encoder

8.

CTCSS,

DCS

Decoder

5)

Power

Supply

Circuit

The

DC

potential

of

12

of

iC108

is

input

to

1

of

the

CPU

(IC1),

converted

from

an

analog

to

a

digital

signal,

and

displayed

as

the

S-meter

signal

on

the

LCD.

The

CPU

(IC1)

is

equipped

with

an

internal

DTMF

encoder.

The

DTMF

signal

is

output

from

10,

through

R35,

R34

and

R261

(for

level

adjustment),

and

then

through

the

microphone

amplifier

(IC114:D),

and

is

sent

to

the

varicap

of

the

VCO

for

modulation.

At

the

same

time,

the

monitoring

tone

passes

through

the

AF

circuit

and

is

output

form

the

speaker.

The

CPU

(IC1)

is

equipped

with

an

internal

tone

encoder.

The

tone

signal

(67.0

to

250.3

Hz)

is

output

from

9

of

the

CPU

to

the

varicap

(D120)

of

the

VCO

for

modulation.

The

CPU

(IC1)

is

equipped

with

an

internal

DCS

code

encoder.

The

code

(023

to

754)

is

output

from

9

of

the

CPU

to

the

PLL

reference

oscillator,

When

DCS

is

ON,

DCS

MUTE

circuit

(Q126-ON,

Q133-ON,

Q132-OFF)

works.

The

modulation

activates

in

X102

side

only.

The

voice

band

of

the

AF

output

signal

from

3

of

1C120:A

is

cut

by

sharp

active

filter

1C104:A

and

D

(VCVS)

and

amplified,

then

led

to

4

of

CPU.

The

input

signal

is

compared

with

the

programmed

tone

frequency

code

in

the

CPU.

The

squelch

will

open

when

they

match.

During

DCS,

Q108

is

ON,

C419

is

working

and

cut

off

frequency

is

lowered.

When

power

supply

is

ON,

there

is

a

"L"

signal

being

inputted

to

39

(PSW)

of

CPU

which

enables

the

CPU

to

work.

Then,

"H"

signal

is

outputted

from

the

41

(C5C)}

of

CPU

and

drives

ON

the

power

supply

switch

conirol

Q8

and

Q7

which

turns

the

5VS

ON.5VS

turns

ON

the

PLL

1C116,

main

power

supply

switch

Q127

and

Q122,

AF

POWER

IC117

and

the

8

V

of

AVR

(1C115).During

reception,

29

(R5)

of

CPU

outputs

"H"

level,

Q124

is

ON,

and

the

reception

circuits

supplied

by

8

V.While

during

transmission,

28

(T5)

of

CPU

outputs

"L”

level

which

is

reverse

by

Q11

so

that

the

output

in

Q128

will

be

"H"

level,

Q123

is

ON,

and

the

transmission

circuit

is

supplied

by

8

V.Or,

in

the

case

when

the

condition

of

PLL

is

UNLOCK,

"L"

level

is

outputted

from

14

of

IC116,

UNLOCK

switch

Q148

is

OFF,Q129is

ON,

transmission

switch

Q128

is

OFF

which

makes

the

transmission

to

stop.

1.

ACC

External

Power

Supply

Terminal

When

optional

power

supply

cord

DEC-37

etc.

is

connected

to

the

external

power

supply

terminal

JK101,

with

ACC

power

supply

ON,

switch

Q101

will

turn

ON,

5

V

of

AVR

IC101

2

(STB)

becomes

"L"

which

makes

C5V

to

turn

ON.

With

this,

it

can

turn

the

power

supply

of

the

radio

ON.

6)

M38268MCLO83GP#U0

(XA1130A)

CPU

Terminal

Connection

(TOP

VIEW)

2£94S/€

ld

=—

Lg

Sl«+—>

Add

9938/2

ld

«(2g

y2]~—>

Obd

GE9AS/

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~—>jE4)

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LINI/

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y£948/0ld

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€£948/20d

«—>[Sg

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2£93S/90d

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196

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5

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0X1

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~—>

[84]

BI]——>

11198/9rd

§293S/€0d

~—>

[6G

LI

~+—>

1AQUS/2bd

8293S/20d

~—>

[09

91}+—>

OWd/0Gd

L294S/10d

<—>[[9)

S1]-~<—>

LWikd/1Sd

9294S/00d

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[29

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G294S/2d

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8

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61934S/12d

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9

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219348

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GNV/S9d

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+—

[PL

[2

j-+—™

SNY/99d

€193d$

+—

[GL

|

j-+—>

JNV/29d

No.

|__

Terminal

P67/AN7

|__|

S-meter

input

P6es/ANG

|

SQL

|

1

__|

Noise

level

input

for

squelch

3

P65/AN5

BAT

|

1

_

|

Battery

voltage

input

4

P64/AN4

TIN

|

t

_|

CTCSS

tone

input

/

DCS

code

input

5

|

P63/SCLK22/AN3|__

BP1

|

1

|

Band

plan1

[6

[PeaiSclK2taN2|

_BP2

|

1

|Bandpln?

——~SOS~“‘—‘“‘—*S*S*~*~“‘—*~“—S~*~*~*~*~‘—s~s~*S*~S~S*S

7

[Petisourziant

|

Dcsw

|

0

|[DCSsignalmulo

—=—SOSC~—“—~S*~“—*~S*~—~—~—~—~S*~S

[e_|

PSO/sINZiANO

|

RE2

|

1

|

Rotary

enooderinpat

—S~S~<S~*~“—*~*~*~*~S~S~«*™

8

|

PSTIADTIDA2

|

TOUT

|

0

|

CTCSS

tone

output

/DOStone

output

——SCSC~C~*~S*S

Tao

|

PseA1

|

DOUT

|

oO

[DTWFowputsCSC—“~‘“‘sSCS*S*C*C‘~*‘“*~*~*”

Tt

|

PssicnTR?

|

SCL_|

O

|

Serialclock

for

EEPROM

—=~C~“~S*S*S*S*~S~S~*S

[42

P6acnTRO

|

TBST_|

O

|

Toneburstoutput__—=SCS—S—S

-18_|__PSiPWMT

|

CLK

|

0

|

Serial

clock

outputfor

PLL,

scramble

—=—SS~S~S

[te

PasiSCLKI

|

ST8_|_O

|StobeforPLICSSSC*”

UTX

|

©

|

UART

data

transmission

output

SSCS

20

|

PaafRXD

|

__RTX

|__|

UARTdatareception

output.

——SSSOS~S

22_[_pag/int2

|

SEC

|

1

|

Security

voltage

input

_-—=S~S~S~S~SsS

723[_PaviNT?

|

_RE1

|

1

[Rotary

enooderinput

——S~C~—~S~S~S

rea

|

_

P40

|

DSQ

|

1

[Digital

squelch

input

—S—S~—~—~SSSSS~S

ras

[_Pr7__|_pTt

| 1

[PiTinut——SSOSCSC—C—SSC‘CSC~S~;7<O;

[26

|

P76

|

SSTB

|

_O

|

Strobe

signal

to

scramble

IC/Securitymode

SS

p75_|

WN

|

0

|WideNarowSW

P28

|

p7a__+|

15

|

0

|

TX

power

ON/OFF

ouput’

——SC~—~S~S~S~S

p73

|

_R5__|

0

|

RX

power

ON/OFF

output

—S~S

"30

|

P72~|

~

sac

|

o

[SaoN/oreSOOC“CSC“CSCS

P71

cis

|

Digital

scramble

ONTOFF—=SC=C=“‘*~*~“~*~*~*S

[32[P7OINTO

|

BU

|

1

|

Backup

signal

detection

input

——S~SCSCS~SwT

[33|

RESET

|

RESET

|

1

[Resetipst

SS

SOSOC—~S—“CSC‘~S~S*~*™S

raat

XIN

|

xm

|

-

[-

OOOCOC—SSSOSOCOCOCSC“(CNSNNC#NC#Cd

3s

|_xcouT

|

xcout

|

-

[-SSSs—S—SSOSC‘;

OU

XIN

|

Xin

|__|

Mainclockinput

——S~CS<CSS*~*~*~*~S*~*™

“37

[|

xouT

|

Xout

|

_-

|

Main

clockoutput

——S—~—“—~—S—“—~—“—“—“—s~s—“—s~s~S*S*™

pas

[vss

|

GND

|

-

[cPUGND.——SOSC‘<;7C<SWtCt

[se

|

P27_|

-PSW

|

1

|

Powerswitchinput

—S=~CSCS

[40

[P26

|

SDA_|

O

|

SerialdataforEEPROM

—=~=~“~*S*S*~“~S~S~S~S~*S

a

|P25

|

C8C__|

O

|

CSV

power

ON/OFF

ouput

—S—=~“~*~—~*~*~*S

[42_|

P24

|

AIR

|

O

|

Airband

SW/Tx

middle

power

—SSSOSCS~S~S~S

(43

|

P23

|

LOW

|

0

|Txiowpower

SS

SSCSC“~“~*~“~*~*~*~“~S~S~S~S

44[

P22

|

EXP

|

O

|

Trunking/PacketdaiaSWsSS—~—CS~—~—~S

swe

|

1

_|Keysw6(SQl)SOSOC—SSSC“CSs~—~—~*~S~S

(46

[P20

+|

sWs

|

1

_[Keysw5(CALL)

—S=~“~“~S*~“—~S—C~S

sw4

|

_1_|Keyswa(TSQ)OSOSC—SCS~—CSCS

ras[

Pte

|

_swa

|

1

|Keysw3(MHz)—S=C=~“‘*‘“*S*~*“‘~*~“~*~“~“<SCS

-as_|

Pieiseeso__|

sW2

|

1

|

Keysw2(ViM)_—SsS~—~—SSCSC~S~SCS

50

|

Prasecss_|

_swi_|

1

[Keyswi(FUNC)——SSSSS—S—~—S

[No.[

Terminal

Signal

|

VO.|

Description

si

|

P1asEG37

|

DOWN

|

1

|Miodownipat

———S—~—“—~*~‘“‘“‘“~*~S*S*SCS

Vs2

|

praseesé

|

DUD

|

1

|

Digitalunitdetect

——SC~S~S—S~—~S~S

[83]

PH/SEG3s

|

SCR

|

1

|

Scramble

IC

ready

signal/

PTT

input

for

S600bps——

sa

|

Prosecsa

[UP

[1

|Micupinput

SCSC—‘“~S*~‘“~*~*~S

ss

|

Povsecss

|

s33_|

o |

se

|

Possecsz

|

sa

|

o

vs7

|

Possess

|

s31_|

o

Tse

|

Possess

|

ss

|

0

|

Tso

|

Pos/secza

|

s29

|

o |

reo

|

Povseczs

|

sz

|

0

|

Tei

|

Povsee27

|

s27_|

0

|

rez

|

Poo/sec2s

|

s26

|

0 |

"ea

|

Pa7sec2s

|

S25}

0

rea

|

Poeseczs

|

sz

|

_o_|

Des

|

Pesseczs

|

_s23_|

0 |

P66

|

Peasecze

|

sx

|

o

|

rer

|

Pawseczt

|

sa

|

o |

ree

|

Pazsee20

|

s20

|

0

|

(ea

|

_Povsecia

[sia

|

o

|

70

|

Psosecis

|

ste]

o

om

[|

_seci7

[|

_si7_

|

0

|

[2

[sects

|

ste

[0

|

[73

|

sects

|

sts_|o

|

m4

[seca

|

suo

|

rs

|

_secis

|

si

|

o

|

[76

[_seci2

|

sz

|

o

77

|

sesn_[

sn]

0

|

re

|

_secio

[sto

[0

79

[seco

|

so

[0

Teo

[secs

|

se

|

o|

=

a2

|

secs

|

se

|

o

|

ras

|

sees

=|

ss

~|

0

|

rea

[seca

[sa

fo

res

|

seca

|

s3_

|

o

|

ras

|

sea2

|

_s2

~~

o

rer

[seat

|

st

|

o

ree

[seco

|

so

| 0

ree

|

vec

|

voD_|

_-

|CPUpowertemminal

———=SC=“‘CSNCSC;™*~‘“*‘*~*S

ol

mean

ne

rot

|

_AVSS__|

_Avss_|-

|

AD

converter

GND

e2

[coms

|

coms

[0

[LOD

CoM

output.

——S~—~—“—~—~*~“s~“<~SCSCS*s*ét‘t~S~S*S

Coz

[0

[LCD

COM2

output

—S—~—S—S—S—S

[lea

[~~

comt_|

coma

0

[Lc

com

output.

——SOS—CS—CSCSCS

COMO

|

0

[LCDCOMOoutput

—=S—~—~—S—“‘“‘“<;72S;

SCS

ros

|

vis——«d|

Ss

|

[cD

power

supply

SCSC—C—‘“—“‘“‘“~CSs*st*~*~*~S~S~*S

(2

v2

[|

-

|

98

aed

38

|

Le

fara

LCD

segment

signal

|

wa

|

wa

|

LCD

power

supply

LCD

power

supply

SEMICONDUCTOR

DATA

1)

NJM7808FA

(XA0102)

8V

(1A)

Voltage

Regulator

780A

4.

INPUT

IRC

2.

COMMON

|

3,

OUTPUT

123

2)

TC4S66F

(XA0115)

Bilateral

Switch

1.

IN

/

OUT

2,

OUT

/IN

3.

VSS

4.

CONT

5.

VDD

3)

AN8010M

(XA0119)

10V

(50mA)

Voltage

Regulator

1.

OUTPUT

2,

COMMON

3.

INPUT

4)

TC4W53FU

(XA0348)

Multiplexer

/

De-multiplexer

1.

COMMON

2.

INH

3.

VEE

4.VSS

5.A

6.

ch

14

7.

chO

8.

VDD

CONT

|

Function

(IN-OUT)

Connect

(290ohm

typ.

Relerence

vol

lage

Start

un

circuit

protector

NONE

*

Don't't

care

Alinco DR-235TMkIIT User manual

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