Alpha Data ADM-XRC-9R1 User manual

ADM-XRC-9R1
User Manual
Document Revision: 1.7
16th Sept 0 0

ADM-XRC-9R1 User Manual
V1.7 - 16th Sept 0 0
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ADM-XRC-9R1 User Manual
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able Of Contents
1 Introduction ...................................................................................................................................... 1
1.1 Key Features ................................................................................................................................. 1
1.2 Order Code .................................................................................................................................... 2
1.3 References & Specifications .......................................................................................................... 2
Installation ........................................................................................................................................ 3
2.1 Hardware Installation ..................................................................................................................... 3
2.1.1 Handling Instructions ................................................................................................................. 3
2.1.2 Motherboard / Carrier Requirements ......................................................................................... 3
2.1.3 Cooling Requirements ............................................................................................................... 4
3 Functional Description .................................................................................................................... 5
3.1 Overview ........................................................................................................................................ 5
3.1.1 Switch Definitions ......................................................................................................................
3.1.2 LED Definitions .......................................................................................................................... 7
3.1.2.1 User LEDs ............................................................................................................................. 7
3.2 XMC Platform Interface ................................................................................................................. 8
3.2.1 IPMI I2C ..................................................................................................................................... 8
3.2.2 MBIST# ...................................................................................................................................... 8
3.2.3 MVMRO ..................................................................................................................................... 8
3.2.4 MRSTI# ...................................................................................................................................... 8
3.2.5 MRSTO# .................................................................................................................................... 8
3.2. MPRESENT# ............................................................................................................................. 8
3.3 JTAG Interface ............................................................................................................................... 9
3.3.1 On-board Interface ..................................................................................................................... 9
3.3.2 XMC Interface ............................................................................................................................ 9
3.3.3 JTAG Voltages ........................................................................................................................... 9
3.4 Clocks .......................................................................................................................................... 10
3.4.1 300MHz Reference Clocks (REFCLK300M and FABRIC_CLK) .............................................. 10
3.4.2 PCIe Reference Clocks (PCIEREFCLK) ................................................................................. 10
3.4.3 PN Reference Clock (PN _PCIEREFCLK) ............................................................................ 11
3.4.4 Programmable Clocks (PROGCLK 0-2) ................................................................................... 11
3.4.5 MGT Reference Clocks ............................................................................................................ 11
3.4. Digital System Oscillators ........................................................................................................ 12
3.4.7 RF Sampling Clocks ................................................................................................................ 12
3.4.7.1 Sysref Clocks ....................................................................................................................... 13
3.4.7.2 RF System FPGA Reference Clock ..................................................................................... 13
3.4.7.3 RF Clock Programming ....................................................................................................... 14
3.5 Zynq PS Block ............................................................................................................................. 15
3.5.1 Boot Modes .............................................................................................................................. 15
3.5.2 Quad SPI Flash Memory ......................................................................................................... 15
3.5.3 MicroSD Flash Memory ........................................................................................................... 15
3.5.4 PS DDR4 Memory ................................................................................................................... 15
3.5.5 PS MGT Links .......................................................................................................................... 15
3.5. Ethernet Interfaces .................................................................................................................. 1
3.5.7 Serial COM Ports ..................................................................................................................... 1
3.5.8 USB Interfaces ......................................................................................................................... 17
3. PL Interfaces ................................................................................................................................ 18
3. .1 I/O Bank Voltages .................................................................................................................... 18
3. .2 MGT Links ............................................................................................................................... 18
3. .3 Memory Interfaces ................................................................................................................... 19
3. .4 GPIO ........................................................................................................................................ 19
3.7 RF Interfaces ............................................................................................................................... 20
3.7.1 Front-Panel I/O ........................................................................................................................ 20

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3.7.2 RF Performance ...................................................................................................................... 22
3.8 Configuration ............................................................................................................................... 24
3.8.1 Power-Up Sequence ................................................................................................................ 24
3.9 System Monitoring ....................................................................................................................... 24
3.9.1 Automatic Temperature Monitoring .......................................................................................... 25
3.9.2 Microcontroller Status LEDs .................................................................................................... 25
3.9.3 System Monitor Interfaces ....................................................................................................... 2
Appendix A Rear Connector Pinouts ............................................................................................................... 7
A.1 Primary XMC Connector, P5 ........................................................................................................ 27
A.2 Secondary XMC Connector, P ................................................................................................... 28
A.2.1 Pn GPIO Pin Map .................................................................................................................. 29
A.3 PMC Connector P4 ...................................................................................................................... 30
List of ables
able 1 Build Options ..................................................................................................................................... 2
able 2 References ........................................................................................................................................ 2
able 3 Switch Definitions .............................................................................................................................. 6
able 4 LED Definitions .................................................................................................................................. 7
able 5 REFCLK300M Connections ............................................................................................................. 10
able 6 PCIEREFCLK Connections ............................................................................................................. 10
able 7 PN6_PCIEREFCLK Connections .................................................................................................... 11
able 8 PROGCLK Connections .................................................................................................................. 11
able 9 Reference clocks Connections ........................................................................................................ 12
able 10 RF Clock Connections ..................................................................................................................... 12
able 11 SysRef Connections ........................................................................................................................ 13
able 12 FPGA Reference Clock Connections ............................................................................................... 13
able 13 FPGA 4-Wire Connections ............................................................................................................... 14
able 14 Boot Mode Selection ........................................................................................................................ 15
able 15 Ethernet Status LEDs ...................................................................................................................... 16
able 16 arget FPGA IO Banks .................................................................................................................... 18
able 17 arget MG Links ............................................................................................................................ 18
able 18 Front panel I/O signals ..................................................................................................................... 20
able 19 Voltage and emperature Monitors .................................................................................................. 24
able 20 emperature Limits .......................................................................................................................... 25
able 21 Status LED Definitions ..................................................................................................................... 25
able 22 avr2util clock indexes ....................................................................................................................... 26
able 23 Pn5 Interface ................................................................................................................................... 27
able 24 Pn6 Interface ................................................................................................................................... 28
able 25 Pn6 GPIO Pin Map .......................................................................................................................... 29
able 26 Pn4 Interface ................................................................................................................................... 30
List of Figures
Figure 1 ADM-XRC-9R1 Block Diagram .......................................................................................................... 5
Figure 2 LED Locations ................................................................................................................................... 7
Figure 3 J AG Boundary Scan Chain .............................................................................................................. 9
Figure 4 On-Board Digital System Clocks ..................................................................................................... 10
Figure 5 MG Clocks ..................................................................................................................................... 11
Figure 6 ADM-XRC-9R1 RF sampling clock .................................................................................................. 12
Figure 7 CPLD Connections .......................................................................................................................... 14

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Figure 8 Ethernet Interfaces .......................................................................................................................... 16
Figure 9 Serial COM Ports ............................................................................................................................. 16
Figure 10 USB Interfaces ................................................................................................................................. 17
Figure 11 MG Links ....................................................................................................................................... 18
Figure 12 PL DRAM Banks .............................................................................................................................. 19
Figure 13 GPIO Block Diagram ....................................................................................................................... 19
Figure 14 Front Panel IO ................................................................................................................................. 20
Figure 15 ADM-XRC-9R1 ADC Performance .................................................................................................. 22
Figure 16 ADM-XRC-9R1 DAC Performance .................................................................................................. 23

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1 Introduction
he ADM-XRC-9R1 is a high-performance XMC for applications using Zynq Ultrascale+ RFSoC from Xilinx.
1.1 Key Features
Key Features
• Single-width XMC, compliant to VI A Standard 42.0, 42.3 and 42.10d12
• Support for Zynq Ultrascale+ XCZU27DR/XCZU28DR/XCZU47DR/XCZU48DR RFSoC in FFVE1156 and
FSVE1156 packages
• Processing System (PS) Block consisting of:
• Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5, Mali-400 GPU
• 1 bank of DDR4-2400 SDRAM 2GB
• Removable microSD Flash memory
• wo Quad SPI Flash memory, 512Mb each
• wo USB ports to rear P4 connector
• wo serial COM port interfaces to rear P4 connector
• One system monitor USB port to micro USB connector
• wo Gigabit Ethernet interfaces to rear P4 connector
• 4 lane PCI-Express Gen 2 interface on the P5 connector
• Programmable Logic (PL) block consisting of:
• 8 HSSIO links to the P6 connector
• 2 banks of DDR4-2400 SDRAM, 1GB per bank
• 19 GPIO pins
• RF Sampling block consisting of:
• 8 12-bit 4/5GSPS RF-ADCs
• 8 14-bit 6.5/10GSPS RF-DACs
• 8 soft-decision FECs (ZU28DR/ZU48DR only)
• Front Panel IO Interface with:
• 8 HF single ended ADC signals
• 8 HF single ended DAC signals
• Reference clock input for the RF sampling blocks
• Reference clock output from RF sampling blocks
• 2 digital GPIO
• Voltage and temperature monitoring
• Board management via USB.
• Air-cooled and conduction-cooled configurations
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1. Order Code
ADM-XRC-9R1/z-y(c)
Name Symbol Configurations
Device z ZU27 , ZU28 , ZU47 , ZU48
Speed Grade y 2
Cooling c blank = air cooled industrial
/CC1 = conduction cooled industrial
Table 1 : Build Options
Not all combinations are available. Please check with Alpha Data sales for details.
1.3 References & Specifications
ANSI/VI A 42.0 XMC Standard, December 2008, VI A, ISBN 1-885731-49-3
ANSI/VI A 42.2 XMC Serial RapidIO Protocol Layer Standard, Feb 2006, VI A, ISBN 1-885731-41-8
ANSI/VI A 42.3 XMC PCI Express Protocol Layer Standard, June 2006, VI A, ISBN 1-885731-43-4
ANSI/VI A 46.9 PMC/XMC Rear I/O Fabric Signal Mapping on 3U and U VPX Modules Standard,
November 2010, VI A, ISBN 1-885731-63-9
ANSI/IEEE 1386-2001 IEEE Standard for a Common Mezzanine Card (CMC) Family, October 2001, IEEE,
ISBN 0-7381-2829-5
ANSI/IEEE 1386.1-2001 IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards (PMC),
October 2001, IEEE, ISBN 0-7381-2831-7
ANSI/VI A 20-2001
(R2005) Conduction Cooled PMC, February 2005, VI A, ISBN 1-885731-26-4
Table : References
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Installation
.1 Hardware Installation
.1.1 Handling Instructions
he components on this board can be damaged by electrostatic discharge (ESD). o prevent damage, observe
SSD precautions:
- Always wear a wrist-strap when handling the card
- Hold the board by the edges
- Avoid touching any components
- Store in ESD safe bag.
.1. Motherboard / Carrier Requirements
he ADM-XRC-9R1 is a single width XMC.3 mezzanine with P6 and P4 connectors. he motherboard/ carrier
must comply with the XMC.3 (VI A 42.3) specification for the Primary XMC connector, J5.
he Secondary XMC connector, P6 has a pinout compatible with various XMC to VPX signal maps as defined by
VI A 46.9. Please consult the pinouts in this user-guide as-well as those of the carrier manufacturer prior to
installation. Assistance can be provided by Alpha Data.
IMPORTANT
Connector P6 on the card is not compatible with the VI A 42.10 (XMC GPIO) Standard. In particular, USB
VCC must not be applied on this connector.
he ADM-XRC-9R1 is compatible with either 5V or 12V on the "VPWR" power rail.
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.1.3 Cooling Requirements
he power dissipation of the board is highly dependent on the arget FPGA application. A power estimator
spreadsheet is available on request from Alpha Data. his should be used in conjunction with Xilinx power
estimation tools to determine the exact current requirements for each power rail.
he board is supplied with a passive air cooled or conduction cooled heat-sink according to the order number
given at time of purchase. It is the users responsibility to ensure sufficient airflow for air cooled applications and
metalwork for conduction cooled applications.
For more details on heat-sinks supplied with Alpha Data boards, please view the Alpha Data Environmental
Specification at Environmental Specifications on www.alpha-data.com .
he board features system monitoring that measures the board and FPGA temperature. It also includes a
self-protection mechanism that will clear the target FPGA configuration if an over-temperature condition is
detected.
See Section 3.9 for further details.
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