Alpha Data ADM-XRC-9R1 User manual

ADM-XRC-9R1
User Manual
Document Revision: 1.7
16th Sept 0 0

ADM-XRC-9R1 User Manual
V1.7 - 16th Sept 0 0
© 0 0 Copyright Alpha Data Parallel Systems Ltd.
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Data Parallel Systems Ltd.
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All trademarks are the property of their respective owners.

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able Of Contents
1 Introduction ...................................................................................................................................... 1
1.1 Key Features ................................................................................................................................. 1
1.2 Order Code .................................................................................................................................... 2
1.3 References & Specifications .......................................................................................................... 2
Installation ........................................................................................................................................ 3
2.1 Hardware Installation ..................................................................................................................... 3
2.1.1 Handling Instructions ................................................................................................................. 3
2.1.2 Motherboard / Carrier Requirements ......................................................................................... 3
2.1.3 Cooling Requirements ............................................................................................................... 4
3 Functional Description .................................................................................................................... 5
3.1 Overview ........................................................................................................................................ 5
3.1.1 Switch Definitions ......................................................................................................................
3.1.2 LED Definitions .......................................................................................................................... 7
3.1.2.1 User LEDs ............................................................................................................................. 7
3.2 XMC Platform Interface ................................................................................................................. 8
3.2.1 IPMI I2C ..................................................................................................................................... 8
3.2.2 MBIST# ...................................................................................................................................... 8
3.2.3 MVMRO ..................................................................................................................................... 8
3.2.4 MRSTI# ...................................................................................................................................... 8
3.2.5 MRSTO# .................................................................................................................................... 8
3.2. MPRESENT# ............................................................................................................................. 8
3.3 JTAG Interface ............................................................................................................................... 9
3.3.1 On-board Interface ..................................................................................................................... 9
3.3.2 XMC Interface ............................................................................................................................ 9
3.3.3 JTAG Voltages ........................................................................................................................... 9
3.4 Clocks .......................................................................................................................................... 10
3.4.1 300MHz Reference Clocks (REFCLK300M and FABRIC_CLK) .............................................. 10
3.4.2 PCIe Reference Clocks (PCIEREFCLK) ................................................................................. 10
3.4.3 PN Reference Clock (PN _PCIEREFCLK) ............................................................................ 11
3.4.4 Programmable Clocks (PROGCLK 0-2) ................................................................................... 11
3.4.5 MGT Reference Clocks ............................................................................................................ 11
3.4. Digital System Oscillators ........................................................................................................ 12
3.4.7 RF Sampling Clocks ................................................................................................................ 12
3.4.7.1 Sysref Clocks ....................................................................................................................... 13
3.4.7.2 RF System FPGA Reference Clock ..................................................................................... 13
3.4.7.3 RF Clock Programming ....................................................................................................... 14
3.5 Zynq PS Block ............................................................................................................................. 15
3.5.1 Boot Modes .............................................................................................................................. 15
3.5.2 Quad SPI Flash Memory ......................................................................................................... 15
3.5.3 MicroSD Flash Memory ........................................................................................................... 15
3.5.4 PS DDR4 Memory ................................................................................................................... 15
3.5.5 PS MGT Links .......................................................................................................................... 15
3.5. Ethernet Interfaces .................................................................................................................. 1
3.5.7 Serial COM Ports ..................................................................................................................... 1
3.5.8 USB Interfaces ......................................................................................................................... 17
3. PL Interfaces ................................................................................................................................ 18
3. .1 I/O Bank Voltages .................................................................................................................... 18
3. .2 MGT Links ............................................................................................................................... 18
3. .3 Memory Interfaces ................................................................................................................... 19
3. .4 GPIO ........................................................................................................................................ 19
3.7 RF Interfaces ............................................................................................................................... 20
3.7.1 Front-Panel I/O ........................................................................................................................ 20

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3.7.2 RF Performance ...................................................................................................................... 22
3.8 Configuration ............................................................................................................................... 24
3.8.1 Power-Up Sequence ................................................................................................................ 24
3.9 System Monitoring ....................................................................................................................... 24
3.9.1 Automatic Temperature Monitoring .......................................................................................... 25
3.9.2 Microcontroller Status LEDs .................................................................................................... 25
3.9.3 System Monitor Interfaces ....................................................................................................... 2
Appendix A Rear Connector Pinouts ............................................................................................................... 7
A.1 Primary XMC Connector, P5 ........................................................................................................ 27
A.2 Secondary XMC Connector, P ................................................................................................... 28
A.2.1 Pn GPIO Pin Map .................................................................................................................. 29
A.3 PMC Connector P4 ...................................................................................................................... 30
List of ables
able 1 Build Options ..................................................................................................................................... 2
able 2 References ........................................................................................................................................ 2
able 3 Switch Definitions .............................................................................................................................. 6
able 4 LED Definitions .................................................................................................................................. 7
able 5 REFCLK300M Connections ............................................................................................................. 10
able 6 PCIEREFCLK Connections ............................................................................................................. 10
able 7 PN6_PCIEREFCLK Connections .................................................................................................... 11
able 8 PROGCLK Connections .................................................................................................................. 11
able 9 Reference clocks Connections ........................................................................................................ 12
able 10 RF Clock Connections ..................................................................................................................... 12
able 11 SysRef Connections ........................................................................................................................ 13
able 12 FPGA Reference Clock Connections ............................................................................................... 13
able 13 FPGA 4-Wire Connections ............................................................................................................... 14
able 14 Boot Mode Selection ........................................................................................................................ 15
able 15 Ethernet Status LEDs ...................................................................................................................... 16
able 16 arget FPGA IO Banks .................................................................................................................... 18
able 17 arget MG Links ............................................................................................................................ 18
able 18 Front panel I/O signals ..................................................................................................................... 20
able 19 Voltage and emperature Monitors .................................................................................................. 24
able 20 emperature Limits .......................................................................................................................... 25
able 21 Status LED Definitions ..................................................................................................................... 25
able 22 avr2util clock indexes ....................................................................................................................... 26
able 23 Pn5 Interface ................................................................................................................................... 27
able 24 Pn6 Interface ................................................................................................................................... 28
able 25 Pn6 GPIO Pin Map .......................................................................................................................... 29
able 26 Pn4 Interface ................................................................................................................................... 30
List of Figures
Figure 1 ADM-XRC-9R1 Block Diagram .......................................................................................................... 5
Figure 2 LED Locations ................................................................................................................................... 7
Figure 3 J AG Boundary Scan Chain .............................................................................................................. 9
Figure 4 On-Board Digital System Clocks ..................................................................................................... 10
Figure 5 MG Clocks ..................................................................................................................................... 11
Figure 6 ADM-XRC-9R1 RF sampling clock .................................................................................................. 12
Figure 7 CPLD Connections .......................................................................................................................... 14

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Figure 8 Ethernet Interfaces .......................................................................................................................... 16
Figure 9 Serial COM Ports ............................................................................................................................. 16
Figure 10 USB Interfaces ................................................................................................................................. 17
Figure 11 MG Links ....................................................................................................................................... 18
Figure 12 PL DRAM Banks .............................................................................................................................. 19
Figure 13 GPIO Block Diagram ....................................................................................................................... 19
Figure 14 Front Panel IO ................................................................................................................................. 20
Figure 15 ADM-XRC-9R1 ADC Performance .................................................................................................. 22
Figure 16 ADM-XRC-9R1 DAC Performance .................................................................................................. 23

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1 Introduction
he ADM-XRC-9R1 is a high-performance XMC for applications using Zynq Ultrascale+ RFSoC from Xilinx.
1.1 Key Features
Key Features
• Single-width XMC, compliant to VI A Standard 42.0, 42.3 and 42.10d12
• Support for Zynq Ultrascale+ XCZU27DR/XCZU28DR/XCZU47DR/XCZU48DR RFSoC in FFVE1156 and
FSVE1156 packages
• Processing System (PS) Block consisting of:
• Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5, Mali-400 GPU
• 1 bank of DDR4-2400 SDRAM 2GB
• Removable microSD Flash memory
• wo Quad SPI Flash memory, 512Mb each
• wo USB ports to rear P4 connector
• wo serial COM port interfaces to rear P4 connector
• One system monitor USB port to micro USB connector
• wo Gigabit Ethernet interfaces to rear P4 connector
• 4 lane PCI-Express Gen 2 interface on the P5 connector
• Programmable Logic (PL) block consisting of:
• 8 HSSIO links to the P6 connector
• 2 banks of DDR4-2400 SDRAM, 1GB per bank
• 19 GPIO pins
• RF Sampling block consisting of:
• 8 12-bit 4/5GSPS RF-ADCs
• 8 14-bit 6.5/10GSPS RF-DACs
• 8 soft-decision FECs (ZU28DR/ZU48DR only)
• Front Panel IO Interface with:
• 8 HF single ended ADC signals
• 8 HF single ended DAC signals
• Reference clock input for the RF sampling blocks
• Reference clock output from RF sampling blocks
• 2 digital GPIO
• Voltage and temperature monitoring
• Board management via USB.
• Air-cooled and conduction-cooled configurations
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1. Order Code
ADM-XRC-9R1/z-y(c)
Name Symbol Configurations
Device z ZU27 , ZU28 , ZU47 , ZU48
Speed Grade y 2
Cooling c blank = air cooled industrial
/CC1 = conduction cooled industrial
Table 1 : Build Options
Not all combinations are available. Please check with Alpha Data sales for details.
1.3 References & Specifications
ANSI/VI A 42.0 XMC Standard, December 2008, VI A, ISBN 1-885731-49-3
ANSI/VI A 42.2 XMC Serial RapidIO Protocol Layer Standard, Feb 2006, VI A, ISBN 1-885731-41-8
ANSI/VI A 42.3 XMC PCI Express Protocol Layer Standard, June 2006, VI A, ISBN 1-885731-43-4
ANSI/VI A 46.9 PMC/XMC Rear I/O Fabric Signal Mapping on 3U and U VPX Modules Standard,
November 2010, VI A, ISBN 1-885731-63-9
ANSI/IEEE 1386-2001 IEEE Standard for a Common Mezzanine Card (CMC) Family, October 2001, IEEE,
ISBN 0-7381-2829-5
ANSI/IEEE 1386.1-2001 IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards (PMC),
October 2001, IEEE, ISBN 0-7381-2831-7
ANSI/VI A 20-2001
(R2005) Conduction Cooled PMC, February 2005, VI A, ISBN 1-885731-26-4
Table : References
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Installation
.1 Hardware Installation
.1.1 Handling Instructions
he components on this board can be damaged by electrostatic discharge (ESD). o prevent damage, observe
SSD precautions:
- Always wear a wrist-strap when handling the card
- Hold the board by the edges
- Avoid touching any components
- Store in ESD safe bag.
.1. Motherboard / Carrier Requirements
he ADM-XRC-9R1 is a single width XMC.3 mezzanine with P6 and P4 connectors. he motherboard/ carrier
must comply with the XMC.3 (VI A 42.3) specification for the Primary XMC connector, J5.
he Secondary XMC connector, P6 has a pinout compatible with various XMC to VPX signal maps as defined by
VI A 46.9. Please consult the pinouts in this user-guide as-well as those of the carrier manufacturer prior to
installation. Assistance can be provided by Alpha Data.
IMPORTANT
Connector P6 on the card is not compatible with the VI A 42.10 (XMC GPIO) Standard. In particular, USB
VCC must not be applied on this connector.
he ADM-XRC-9R1 is compatible with either 5V or 12V on the "VPWR" power rail.
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.1.3 Cooling Requirements
he power dissipation of the board is highly dependent on the arget FPGA application. A power estimator
spreadsheet is available on request from Alpha Data. his should be used in conjunction with Xilinx power
estimation tools to determine the exact current requirements for each power rail.
he board is supplied with a passive air cooled or conduction cooled heat-sink according to the order number
given at time of purchase. It is the users responsibility to ensure sufficient airflow for air cooled applications and
metalwork for conduction cooled applications.
For more details on heat-sinks supplied with Alpha Data boards, please view the Alpha Data Environmental
Specification at Environmental Specifications on www.alpha-data.com .
he board features system monitoring that measures the board and FPGA temperature. It also includes a
self-protection mechanism that will clear the target FPGA configuration if an over-temperature condition is
detected.
See Section 3.9 for further details.
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3 Functional Description
3.1 Overview
Figure 1 : ADM-XRC-9R1 Block Diagram
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3.1.1 Switch Definitions
here is a set of eight DIP switches placed on the rear of the board. heir functions are described in Switch
Definitions.
Note:
SW1-5 and SW1-8 are OFF by default. Factory Configuration switch must be in the OFF position for normal
operation.
Switch Ref. Function ON State Off State
SW1-1 BootMode 0 See able 14
SW1-2 BootMode 1 See able 14
SW1-3 BootMode 2 See able 14
SW1-4 BootMode 3 See able 14
SW1-5 Factory
Configuration - Normal Operation
SW1-6 XMC J AG
Enable XMC J AG interface is enabled XMC J AG interface is disabled
SW1-7 XMC PCIE
reset enable Zynq PS will be reset by the XMC PCIE reset signal Zynq PS will not be reset by the XMC PCIE reset signal
SW1-8 PS Reset PS is held in reset Normal Operation
Table 3 : Switch Definitions
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3.1. LED Definitions
he position and description of the board status LEDs are shown in LED Locations:
D1D2
D3
D4
D5
D6
D16D11 D10D12
D7
Figure : LED Locations
Comp. Ref. Function ON State Off State
D7(Amber) MVMRO Inhibit writes to non-volatile memories Enable writes to non-volatile memories
D10(Red) Power Fault Power supply fault Normal operation
D11(Green) Status 0 See Status LED Definitions
D12(Red) Status 1 See Status LED Definitions
D16(Green) Done FPGA is configured FPGA is unconfigured
D2(Red) PS Error PS error occurred No PS error
D1(Green) PS Status PS is in secure lockdown state PS is operating normally
D3(Green) User Controlled Pin high Pin low
D4(Green) User Controlled Pin high Pin low
D5(Green) User Controlled Pin high Pin low
D6(Green) User Controlled Pin high Pin low
Table 4 : LED Definitions
3.1. .1 User LEDs
he user LEDs are attached to the CPLD and use an SPI interface to control them. he ADM-XRC-9R1
reference design provides VHDL code to control this interface.
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3. XMC Platform Interface
3. .1 IPMI I C
A 2 Kbit I2C EEPROM (type M24C02) is connected to the XMC IPMI. his memory contains board information
(type, voltage requirements etc.) as defined in the XMC based specification.
3. . MBIST#
Built-In Self est. his output signal is connected to FPGA pin K10. It is not driven by default.
3. .3 MVMRO
XMC Write Prohibit. his signal is an input from the carrier. When asserted (high), all writes to non-volatile
memories are inhibited. his is indicated by the Amber LED, D9.
he MVMRO signal has a 100KΩ pull-up resistor fitted by default.
his signal cannot be internally driven or over-ridden. A buffered version of the signal is connected to the PS at
pin K19.
3. .4 MRSTI#
XMC Reset In. his signal is an active low input from the carrier. A this signal connected to the PS at pin J12.
his signal can also drive the PS power-on-reset pin depending on SW1-7
A buffered version of MRS I# is also connected to the FPGA at pin G21.
3. .5 MRSTO#
XMC Reset Out. his optional output signal is driven from the FPGA pin K12.
3. .6 MPRESENT#
Module Present. his output signal is connected directly to GND.
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3.3 JTAG Interface
3.3.1 On-board Interface
A J AG boundary scan chain is connected to header U12. his allows the connection of the Xilinx J AG cable for
FPGA debug using the Xilinx ChipScope tools.
he scan chain is shown in J AG Boundary Scan Chain:
Target FPGA
XCZU27DR
FFVE1156
CPLD
XC2C64A
CPG56
VREF (3.3V)
HDR_TDI
HDR_TDO
Buffer
3.3V
En#
XMC
Con
(Pn5)
Header
U12
XMC_TDI
XMC_TDO
XMC_ TAG_EN# SW1 6
Figure 3 : JTAG Boundary Scan Chain
If the boundary scan chain is connected to the interface at the XMC connector (SW1-X is ON), Header U12
should not be used.
3.3. XMC Interface
he J AG interface on the XMC connector is normally unused and XMC_ DI connected directly to XMC_ DO.
he interface can be connected to the on-board interface (through level-translators) by switching SW1-X ON.
See Switch Definitions
3.3.3 JTAG Voltages
he on-board J AG scan chain uses 3.3V. he Vcc supply provided on U12 to the J AG cable is +3.3V and is
protected by a poly fuse rated at 350mA.
he J AG signals at the XMC interface use 3.3V signals and are connected through level translators to the
on-board scan chain.
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3.4 Clocks
he ADM-XRC-9R1 provides a wide variety of clocking options. he board has a user-programmable clock
generator. hese clocks can be combined with the FPGA's internal PLLs to suit a wide variety of communication
protocols.
An overview of the clock routing on the ADM-XRC-9R1 is given in On-Board Digital System Clocks. A description
of each clock follows.
Figure 4 : On-Board Digital System Clocks
3.4.1 300MHz Reference Clocks (REFCLK300M and FABRIC_CLK)
he fixed 300MHz reference clocks REFCLK300M and FABRIC_CLK are differential LVDS signals.
REFCLK300M is used as the input clock for both DDR4 SDRAM interfaces.
FABRIC_CLK is used as the reference clock for the IO delay control block (IDELAYC RL).
Signal Frequency arget FPGA Input IO Standard "P" pin "N" pin
REFCLK300M 300 MHz IO_L11_ 1U_GC_66 LVDS AP11 AP10
REFCLK300M 300 MHz IO_L11_ 1U_GC_65 LVDS AJ16 AJ15
FABRIC_CLK 300 MHz IO_L7P_HDGC_89 LVDS F10 F9
Table 5 : REFCLK300M Connections
3.4. PCIe Reference Clocks (PCIEREFCLK)
he 100MHz PCI Express reference clock is provided by the carrier card through the Primary XMC connector,
P5 at pins A19 and B19. his clock is buffered into two PCIe Express reference clocks that are forwarded to the
PS G R and PL G Y transceivers.
Signal Frequency FPGA Input IO Standard "P" pin "N" pin
PCIEREFCLK0 100 MHz PS_MG REFCLK0_505 LVDS Y29 Y30
PCIEREFCLK1 100 MHz MG REFCLK1_128 LVDS K28 K29
Table 6 : PCIEREFCLK Connections
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3.4.3 PN6 Reference Clock (PN6_PCIEREFCLK)
he reference clock "PN6_PCIEREFCLK" is a differential clock provided by a carrier card through the Secondary
XMC connector P6 at pins A19 and B19. his board connects this pair to an MG clock input.
Signal Frequency FPGA Input IO Standard "P" pin "N" pin
PN6_PCIEREFCLK 100 MHz MG REFCLK1_129 LVDS F28 F29
Table 7 : PN6_PCIEREFCLK Connections
3.4.4 Programmable Clocks (PROGCLK 0- )
here is one programmable clock source that is forwarded throughout the FPGA. his clock is programmable
through the USB system monitor. PROGCLK[2:0] is generated by a dedicated programmable clock generator IC
and offer extremely high frequency resolutions (1ppm increments). PROGCLK[2:0] are all buffered copies of the
same clock signal.
Signal Frequency arget FPGA Input IO Standard "P" pin "N" pin
PROGCLK0 5 - 312.5 MHz PS_MG REFCLK1_505 LVDS V29 V30
PROGCLK1 5 - 312.5 MHz MG REFCLK0_128 LVDS M28 M29
PROGCLK2 5 - 312.5 MHz IO_L8P_HDGC_89 LVDS G11 G10
Table 8 : PROGCLK Connections
3.4.5 MGT Reference Clocks
he PS and PL MG s can be clocked by sources from the P5, P6 or on-board clock sources
Zynq Ultrascale
MGT Banks
MGT129
REFCLK0
REFCLK1
MGT128
XMC
P
XMC
P6
PCIe
REFCLK
Buffer
Programmable
Clock Source
REFCLK0
REFCLK1
MGT 0
REFCLK2
REFCLK0
REFCLK1
Figure 5 : MGT Clocks
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3.4.6 Digital System Oscillators
here are four fixed oscillators on the board for the digital system. he USB and Ethernet reference clocks are
used internally by the PHYs.
Signal Frequency FPGA pin
PS Ref Clock 50MHz M25
Si5338 Ref Clock 25MHz -
USB Ref Clock 24MHz -
Ethernet Ref Clock 25MHz -
Table 9 : Reference clocks Connections
3.4.7 RF Sampling Clocks
he RF reference clocks are generated with a dual-loop jitter cleaner PLL. he RF sampling clocks are provided
by three LMX2594 RF clock synthesisers.
Figure 6 : ADM-XRC-9R1 RF sampling clock
Signal Frequency arget FPGA Input "P" pin "N" pin
ADC_CLK_224 Variable ADC_CLK_224 AD5 AD4
ADC_CLK_225 Variable ADC_CLK_225 AB5 AB4
ADC_CLK_226 Variable ADC_CLK_226 Y5 Y4
ADC_CLK_227 Variable ADC_CLK_227 V5 V4
DAC_CLK_228 Variable DAC_CLK_228 L5 L4
DAC_CLK_229 Variable DAC_CLK_229 J5 J4
Table 10 : RF Clock Connections
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3.4.7.1 Sysref Clocks
he sysref clocks provide the sysref functionality to synchronize the RF DACs and ADCs. hey are provided by
the RF clock generators. hey are connected to the PL and the RF sampling block.
Signal Frequency arget FPGA Input "P" pin "N" pin
FPGA Sysref Clock Variable IO_L6_HDGC_88 G12 F12
RF Sysref Clock Variable SYSREF_228 N5 N4
Table 11 : SysRef Connections
3.4.7. RF System FPGA Reference Clock
he RF system FPGA reference clock is a differential clock signal from the RF clock generation circuit, and is
connected to an HDGC input on the PL.
Signal Frequency arget FPGA Input "P" pin "N" pin
RF System FPGA
Reference Clock Variable IO_L5P_HDGC_88 F14 F13
Table 1 : FPGA Reference Clock Connections
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3.4.7.3 RF Clock Programming
he RF reference clocks are programmed from the PL using SPI (LMX2594) or uWire (LMK04208). o minimise
FPGA IO pin usage, a CPLD is used to multiplex a single 4-wire IO interface to the FPGA to each of the 4
devices. here are two control bits to select which clock device is active. Both writing and readback are
supported for all devices. CPLD Connections shows the required chip select value to access each device.
LMK04208
0
CPLD
LMX2594
1
LMX2594
2
LMX2594
3
ADC_CLK_224 (AD5,AD4)
ADC_CLK_225 (AB5, AB4)
ADC_CLK_226 (Y5,Y4)
ADC_CLK_227 (V5, V4)
DAC_CLK_228 (L5,L4)
DAC_CLK_229 (J5, J4)
FPGA
4-Wire
Interface
2-bit
Chip Select
uWire
SPI
SPI
SPI
RF Power
Supply Status
Figure 7 : CPLD Connections
Signal FPGA Pin IO Standard Description
CLK H13 LVCMOS33 4-Wire interface clock
CS_L G13 LVCMOS33 4-Wire interface chip select
SDI E14 LVCMOS33 4-Wire interface data to device (from FPGA)
SDO D14 LVCMOS33 4-Wire interface data from device (to FPGA)
SPI_SEL[0] J14 LVCMOS33 Chip select bit 0
SPI_SEL[1] J13 LVCMOS33 Chip select bit 1
PREREG_PGOOD H15 LVCMOS33 Power good signal from RF power supplies.
LDO_PGOOD H14 LVCMOS33 Power good signal from RF power supplies.
Table 13 : FPGA 4-Wire Connections
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