Alpha Data XRM(2)-DAC-D4/1G User manual

XRM(2)-DAC-D4/1G User Guide
Document Revision: 2.2
Mar , 201

XRM(2)-DAC-D4/1G User Guide
V2.2 - Mar , 201
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Table Of Contents
1 Introduction ...................................................................................................................................... 1
1.1 Block Diagram ............................................................................................................................... 1
1.2 XRM and XRM2 ............................................................................................................................. 4
1.2.1 Signalling Voltage ...................................................................................................................... 4
1.3 Build Level ..................................................................................................................................... 4
1.4 Alpha Data SDK Versions .............................................................................................................. 4
1.5 Xilinx Tool Versions ........................................................................................................................ 4
1. ISE Projects ................................................................................................................................... 4
1. .1 Structure .................................................................................................................................... 4
1.7 Vivado Projects ..............................................................................................................................
1.7.1 Vivado Folder Structure .............................................................................................................
2 Hardware .......................................................................................................................................... 9
2.1 Hardware Operation ...................................................................................................................... 9
2.2 Connector Signals ......................................................................................................................... 9
2.3 DAC Serial Interface ...................................................................................................................... 9
2.4 DAC Programming ....................................................................................................................... 10
2.5 Synthesiser Serial Interface ......................................................................................................... 10
2. Synthesiser Programming ........................................................................................................... 10
2.7 DAC Selftest ................................................................................................................................ 11
2.7.1 Pattern testing .......................................................................................................................... 11
2.7.2 Fifo Test ................................................................................................................................... 11
2.7.3 Selftest ..................................................................................................................................... 11
2.8 DAC DLL Control ......................................................................................................................... 11
2.9 DAC Sync .................................................................................................................................... 11
2.10 Multiple DAC synchronisation ...................................................................................................... 12
2.11 Clocking on Virtex4, Virtex5 ......................................................................................................... 12
2.11.1 Low Frequency Operation ....................................................................................................... 13
2.12 Clocking on Virtex , Kintex7 and Virtex7 ..................................................................................... 14
2.13 Data Generation .......................................................................................................................... 15
2.14 Performance ................................................................................................................................ 15
2.15 Board Layout ............................................................................................................................... 1
3 VHDL Structure .............................................................................................................................. 1
3.1 Introduction .................................................................................................................................. 18
3.2 Major HDL Components .............................................................................................................. 18
3.2.1 Clock generation and alignment .............................................................................................. 18
3.2.2 Data Generation and Output .................................................................................................... 18
3.2.3 Local bus interface ................................................................................................................... 19
3.2.3.1 Virtex4, Virtex5 ..................................................................................................................... 19
3.2.3.2 Virtex , Virtex7, Kintex7 ....................................................................................................... 19
3.2.4 Serial Control ........................................................................................................................... 19
3.2.5 Digital I/O ................................................................................................................................. 20
3.2. General Purpose I/O ................................................................................................................ 20
3.2.7 Host Access via Local Bus ....................................................................................................... 20
3.2.7.1 Virtex4, Virtex5 ..................................................................................................................... 20
3.2.7.2 Virtex , Virtex7, Kintex7 ....................................................................................................... 21
3.3 Waveform Generator Operation .................................................................................................. 22
3.3.1 Sine Waveform Generator ....................................................................................................... 22
3.3.2 Ramp Waveform Generator ..................................................................................................... 23
3.3.3 Triangle Waveform Generator .................................................................................................. 23
3.3.4 Square/Pulse Waveform Generator ......................................................................................... 24
3.3.5 Arbitrary Waveform Generator ................................................................................................. 24
3.3. Self Test Pattern ..................................................................................................................... 25

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3.3.7 Sine Test ................................................................................................................................. 25
4 Register Description ...................................................................................................................... 26
4.1 FPGA_CNTRL_REG (0x00) ........................................................................................................ 28
4.2 FPGA_STATUS_REG (0x01) ...................................................................................................... 30
4.3 CNTR_STAT_REG (0x02) ........................................................................................................... 32
4.4 I_DDS_REG (0x03) ..................................................................................................................... 34
4.5 Q_DDS_REG (0x04) ................................................................................................................... 3
4. I_INC_REG (0x05) ....................................................................................................................... 38
4.7 Q_INC_REG (0x0 ) ..................................................................................................................... 40
4.8 SYNTH_CNTRL_REG (0x07) ...................................................................................................... 42
4.9 SYNTH_STRB_REG (0x08) ........................................................................................................ 44
4.10 IDAC_CNTRL_REG (0x09) ......................................................................................................... 4
4.11 IDAC_STRB_REG (0x0A) ........................................................................................................... 48
4.12 QDAC_CNTRL_REG (0x0B) ....................................................................................................... 50
4.13 QDAC_STRB_REG (0x0C) ......................................................................................................... 52
4.14 DEVICE_REG (0x0D) .................................................................................................................. 54
4.15 I_DDSINIT_REG(0x0E) ............................................................................................................... 5
4.1 Q_DDSINIT_REG(0x0F) ............................................................................................................. 58
4.17 IPATTERN_REG (0x10) ............................................................................................................... 0
4.18 QPATTERN_REG (0x11) ............................................................................................................. 2
4.19 IPATTERN_REG2 (0x12) ............................................................................................................. 4
4.20 QPATTERN_REG2 (0x13) ...........................................................................................................
4.21 MEAS0_VAL_REG (0x14) ........................................................................................................... 8
4.22 MEAS1_VAL_REG (0x15) ........................................................................................................... 70
4.23 MEAS2_VAL_REG (0x1 ) ........................................................................................................... 72
4.24 FREERUN_CNT_REG (0x17) ..................................................................................................... 74
4.25 I_ARBWRITE_REG (0x18) .......................................................................................................... 7
4.2 Q_ARBWRITE_REG (0x19) ........................................................................................................ 78
4.27 ARB _CNTRL_REG (0x1A) ......................................................................................................... 80
4.28 ARB _TICK_REG (0x1B) ............................................................................................................. 82
4.29 AUXCNTRL_REG (0x1E) ............................................................................................................ 84
4.30 PHASE_VALUE_REG (0x1F) ...................................................................................................... 8
List of Tables
Table 1 SMA and UFL Connectors .............................................................................................................. 17
Table 2 Clock Muxing ( 25, 24) .................................................................................................................. 29
List of Figures
Figure 1 Block iagram ................................................................................................................................... 3
Figure 2 efault Project Structure .................................................................................................................... 5
Figure 3 Vivado Project Structure .................................................................................................................... 6
Figure 4 Vivado Files ....................................................................................................................................... 8
Figure 5 Virtex 4 Virtex 5 Clocking Scheme ................................................................................................... 12
Figure 6 Low frequency clocking scheme ...................................................................................................... 14
Figure 7 Kintex 7 Virtex 7 Clocking Scheme .................................................................................................. 15
Figure 8 XRM(2)- AC- 4-1G Layout ............................................................................................................ 16
Figure 9 Waveform Selection iagram .......................................................................................................... 22

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1 Introduction
Alpha ata provide three variants of a fast analogue signal generation card operating at sampling frequencies
up to 1 GHz, based on the AC5681, AC5681Z and AC5682Z devices from Texas Instruments.
The AC5681 provides a non-interpolating architecture for wideband signal generation.
The AC5681Z implements an interpolating architecture and provides filtering and mixing circuitry and is
essentially a single-channel version of the AC5682Z.
The AC5682Z also has an interpolating architecture and provides filtering and mixing circuitry for the two ACs
contained within the package. Note that in this case the second AC output in each package is not accessible,
although the data can be processed and combined internally as two channels.
All versions utilise a common circuit board with build options being used to match the board configuration to the
AC fitted.
These boards differ only in the following aspects:
a) The AC fitted - the AC5681/ AC5681Z version uses a single channel AC normally aimed at
producing wide bandwidth signals. The AC5682Z has 2 full AC channels, which allows signal
generation from complex data streams.
b) Minor differences in pin functions.
c) Register addresses and bit allocations for the internal AC registers in the AC581Z and AC5682Z are
supersets of those in the AC5681.
d) Inclusion of a PLL on the interpolating devices ( AC5681Z, AC5682Z) for AC sample clock generation
from a reference clock. In normal circumstances this facility is not used since because of the limited set of
frequencies that can be produced, but if used the high-frequency clocks required for the FPGA must be
synthesised in the FPGA fabric using MMCM or CM.
These XRM modules are compatible with Alpha- ata's family of FPGA cards fitted with Virtex 4, Virtex 5, Virtex
6, Kintex 7 and Virtex 7 devices.
Both configurations are referred to in this document by the generic title XRM(2)- AC- 4-1G; where required,
any AC-specific differences will be made explicit.
The code and hardware descriptions given below reflect the functions implemented at the date of this document.
1.1 Block Diagram
The block diagram (see Figure Block iagram) shows the major components of the XRM(2)- AC- 4-1G board.
The AC has its own dedicated power supplies and uses a mixture of single-ended (serial control) and
differential (data, clocks and synchronisation) signals to/from the FPGA. A clock synthesis/distribution circuit is
included to provide flexible clock generation options.
edicated serial interfaces are implemented in the VH L code to communicate with the AC and the
synthesiser. These interfaces are initialised automatically by the FPGA as part of the reset sequence.
AC sample data is transferred to each AC from the FPGA via 16 LV S pairs plus synchronisation (SYNC)
and data clock ( CLK) differential pairs. The data clock ( CLK), synchronous with the data, is generated from a
half-rate copy of the AC clock ( ACCLK). The CLK signal runs at 0.5 * the AC clock rate present on the
clock input connector. Within the FPGA the CLK is further divided by 2 for use as a global clock (FABRCLK) for
data generation, so runs at 0.25 * ACCLK.
The synthesiser/distribution circuit provides three options for clocking the AC.
a) Internal reference, internally synthesised clock, giving integer sub-divisions, including 1, of 1GHz.
b) Externally generated clock, integer sub-divisions, including 1.
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c) External reference, internally synthesised clock, giving integer sub-divisions of 1GHz.
A pair of LVTTL outputs ('TRIG' and 'AUX') is provided (3V3 signal levels) via SMA connectors. In addition, two
direct connections to FPGA pins via UFL connectors are also available for fast signalling interconnect between
multiple AC cards or other devices.
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Figure 1 : Block Diagram
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1.2 XRM and XRM2
The latest generation of FPGA cards from Alpha ata use a modified version of the XRM interface originally
implemented on legacy FPGA (Virtex4, Virtex5) cards. From a user viewpoint these two interfaces are identical
so references to 'XRM' signals refer also to XRM2 implementations. Where any differences between the two
interfaces are relevant to the operation of the XRM module they will be explicitly stated in the text.
On the XRM(2)- AC- 4 the principal difference lies in how the I/O voltages for the banks connected to the XRM
are set.
1.2.1 Signalling Voltage
The signals to the AC are mainly LV S, with some single-ended signals for serial interfaces etc. ifferential
termination is used in the FPGA for clocks etc. which requires that the signalling voltage is set to a suitable level
on the host FPGA card. FPGA cards using the XRM2 interface (e.g. Virtex6, Virtex7 etc.) this voltage is set
automatically. On the XRM interface (boards fitted with Virtex4 or Virtex5) this should be set manually to 2v5.
This voltage level is required solely to ensure correct termination values in the FPGA; the AC board will not be
damaged if this voltage is inadvertently set to 3v3.
Single-ended signals are all level-translated to hsift signals to/from the device signalling levels to theat of the
FPGA I/O bank supply being used.
1.3 Build Level
The description in this document refer to release 5.0 of the xrm_dac_d4_1g code, dated 15/11/17. Current board
hardware revision is rev 6 and this code supports rev 3 and later builds. Contact the factory for support for board
versions earlier than rev 3.
1.4 Alpha Data SDK Versions
All VH L code for legacy boards is built using Alpha ata's S K version 4.9.3. This S K version is frozen at this
revision.
All VH L code for current boards uses Alpha ata's A MXRCG3S K version 1.7.0.
1.5 Xilinx Tool Versions
The VH L can be synthesised using either ISE or Vivado. Only FPGA cards fitted with Virtex7 or Kintex7 FPGAs
are supported in Vivado.
The currently supported version of ISE for synthesis and bitfile generation is version 14.7.
The currently supported version of Vivado for synthesis and bitfile generation is version 2017.2.
1.6 ISE Projects
1.6.1 Structure
The example code for ISE builds runs this in batch mode, using makefiles to control the various steps that are
required, based on the methodology used in the both variants of Alpha ata S Ks. The files required for each
FPGA card type are defined in a file with the extension 'prj'; the switches necessary for guiding synthesis, map,
place and route, and bit file generation are defined for each FPGA type in files with the 'scr' extension.
The file paths defined in the prj file reflect the structure of the example code; any changes to the project structure
must be reflected in the paths defined in the prj file.
The default project structure is shown below; this includes the additional folder for the Vivado version of the
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project (highlighted).
Figure 2 : Default Project Structure
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1.7 Vivado Projects
1.7.1 Vivado Folder Structure
The additional folder present in the standard release 'FPGA' folder for producing bitfiles using Vivado is
highlighted. In the case shown, this additional folder is called 'vivado' and is referred to as the main Vivado folder
in this discussion. This folder name be any legal name as long as the paths (relative and absolute) to the S K
files, the project source and the project core files is preserved. In other words it should be at the same level of
the folder hierarchy as the 'source' and 'cores' folders. Any change in these paths will require modifications to
paths defined in TCL scripts.
The generation of project files for Vivado uses scripts based on those in the Vivado examples provided by the
S K. The TCL files automate the generation of Vivado project(s), which ensures that the xpr files produced
include all settings required for correct configuration of both synthesis and post-synthesis file generation.
Specifying these options manually is unlikely to set all options correctly so it is strongly recommended that the
TCL files are used to generate project files and folder structures.
This uses the same 'design-model-device' syntax as the Alpha ata S K examples, where the 'design' equates
to the XRM type, the 'model' equates to the A MXRC board type and the 'device' equates to the specific FPGA
on the FPGA card. In this case the 'device' field is fixed since these designs are for a specific XRM.
Figure 3 : Vivado Project Structure
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The main Vivado folder contains three files - genxpr.bat, genxpr.tcl, makexpr.tcl plus a folder named after each
supported model of board; currently there are only two models supported, the 7K1 and the 7V1.The model
folders contain TCL files that are specific to the design.
Each model folder contains a ‘vivado-scripts’ folder and an xdc file. The xdc file specifies the XRM(2)-to-admxrc
connections for that model. Each 'design-model-device.tcl' file in the ‘vivado-scripts’ folder corresponds to the
scr file for ISE; the 'design-model.tcl' file in the same folder performs a similar function to the prj file. In this file
the required source files (.vhd and .ngc) and the paths to them relative to the main Vivado folder are defined.
All of these files ( xdc, TCL) are provided as part of the release. Normally only the 'design-model.tcl' file is ever
altered and then that only when path names need to be corrected. Note that additional (standard) xdc files from
the S K are required in order to build the bit file correctly and these are also referenced in the 'design-model.tcl'
file.
Once the batch file has been run, the main Vivado folder will contain a third folder which is created by Vivado as
part of the script. This folder is named 'vivado' (note that this is at a level below the main Vivado folder) and the
sub-folders within, named from a combination of the valid model-device variables, are used as the location for
working folders when projects are run.
Genxpr.bat accepts command line parameters to allow projects for single boards, single board types or all
supported boards to be generated. The absence of any command line parameters is interpreted as a command
to make all projects. Using the batch file allows parameters to be passed to the script, something that is not
possible when using the standard TCL ‘source’ command from within Vivado (or other TCL interpreters).
The batch file runs genxpr.tcl in Vivado using batch mode; note that any existing xpr file is not overwritten unless
over-write permission is explicitly specified on the command line. Genxpr.tcl subsequently invokes makexpr.tcl
for each required model and device specified via the command line, creating the working folders for each model/
design combination specified.
Genxpr.tcl is based on the file of the same name that can be found in the S K Vivado projects. In the S K case,
the script allows all S K design examples ( simple, uber etc.) to be generated; in the XRM case there is only a
single design, the one for the XRM(2)-dac-d4. Furthermore, in most cases the top-level entity name (reflected in
the vhdl file name) is not the same as the design name so an extra function has been added (gen_design_top)
to handle this.
The folders thus created for each of the model types contains the xpr and a ‘design-model-device_bit_post.tcl’
for that model. The projects are run from the Vivado GUI by opening the required xpr file; any files produced by
Vivado are stored in the same folder to keep things neat. The ‘design-model-device_bit_post.tcl’ specifies some
post-processing of the bit file necessary to produce the bitfile name expected by the S K application.
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Figure 4 : Vivado Files
It is strongly recommended to retain the folder structure shown in the main Vivado folder in order to ensure that
TCL files provided work correctly. Alterations to this structure will entail the need for extensive modification of
paths/files embedded in the scripts.
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2 Hardware
2.1 Hardware Operation
The application must first configure the FPGA with the bit stream using the standard functions provided in the
S K before any hardware or FPGA registers can be accessed via the local bus .
The various system blocks must be configured in the correct sequence in order to generate analogue signals
correctly. First the clock source must be established, the synthesiser configured, then the FPGA clock
generation circuitry. Once a stable CLK signal has been established, the AC internal registers can be
configured to suit the operating frequency required.
efault register settings are written to the AC and synthesiser following system reset/ FPGA configuration, but
the stability of the clocks during this period cannot be guaranteed so the full clock configuration sequence should
be explicitly run by the application prior to use.
The AC initialisation sequence, which must be run for any change in clock frequency requiring alteration of the
control bits for the AC LL, defaults to the sequence for the AC5681. This can be easily changed in the VH L
to default to the AC5682Z sequence. In both cases the assumed AC clock frequency is 1GHz. Any change in
the clock speed from this value is used to re-configure the clock multiplexing, the settings for the CM clock
used by the FPGA and the AC registers. This application also provides code to interrogate the AC type and
implement the correct settings.
As shown in the Block iagram, the AC sample clock fed to AC I and AC Q run at the full rate (1GHz
maximum); the relevant CLK clocks are at half this rate, since the data interface is R. A total of four
differential clock ports are available to capture the data clock reference. In practice, only three are used since the
pinout of the FPGA requires a maximum of three clock regions in order to support the range of Virtex 4 and
Virtex 5 boards. The fourth is connected to a counter for diagnostic purposes.
2.2 Connector Signals
There are five external connectors accessible on the 4-1G board plus a further two which are used for fast
signalling. Of these, only the TRIG and AUX ports have any significant protection whilst the clock input has
limited overdrive protection.
The AC outputs are ac coupled and present a 50R output impedance, both of which factors give some limited
protection.
The two UFL connectors used for fast signalling are connected directly to FPGA pins. Any signals outwith normal
2v5 LVCMOS signalling levels may cause permanent damage to the FPGA.
2.3 DAC Serial Interface
The reset state of the AC configures the serial interface for 3-wire operation. The example code uses a 4-wire
interface so the first operation following a hardware reset of the AC ( via the RESETB pin of the AC) must be
a write to AC register CONFIG5 which sets 7 to ensure that the AC is set to operate in 4-wire mode.
The Status and Func ports have no function on the AC interface.
The maximum speed of the serial interface is 10 MHz (100 ns). The example code runs the state machine at
LCLK/10, controlled by the EN _CNT generic. This results in the interface clock running at LCLK/20, limiting the
interface to less than 4 MHz for all settings of LCLK. The default rate is 1.6 MHz for LCLK= 33 MHz (virtex4,
Virtex 5) or LCLK=80 MHz (Virtex6, Virtex 7, Kintex 7).
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2.4 DAC Programming
The register values following a reset of the AC require to be modified for correct operation. Firstly the interface
must be set to operate in 4-wire mode as noted above. For the AC 5681 this is essentially all that needs to be
done, since the clock is set up explicitly by the application, which in turn configures the LL settings and re-starts
the AC LL.
The AC5682Z and the AC5681Z require that the PLL, FIR and CMIX blocks are disabled; the AC5682Z also
requires that the output of the second (B channel) is disabled. This requires a read of the "device id" bits to
determine the device fitted to the board.
The operation of any of the ACs requires a hardware reset each time the clock frequency is changed in order to
achieve lock of the AC LL, so this reset sequence must be followed each time.
2.5 Synthesiser Serial Interface
The synthesiser (A 9510) is programmed using a 4-wire interface which is virtually identical to that for the AC.
The maximum operating speed of the serial interface is 25 MHz. The example code has the EN _CNT generic
set to a value of 2, forcing the clock rate on the interface to be 0.25 *LCLK rate (~ 8 MHz for the default LCLK of
33 MHz).
The reset state of the synthesiser/distribution circuit results in incorrect divider values for the AC and the FPGA
clocks so the synthesiser's internal registers must be set explicitly to the required values.
The STATUS port on the serial interface can be used to provide real-time monitoring of various signals within the
synthesiser; this is normally set to the synthesiser lock signal.
The FUNC port provides a real-time control input for the synthesiser. Note that the synthesiser treats this pin as
an active-low reset by default, which must be removed in order to program the synthesiser. For this reason, this
port is normally pulled high and should default high at FPGA reset if used in an application, otherwise the default
configuration data will be ignored by the device.
2.6 Synthesiser Programming
The synthesiser (A 9510) provides three main functions:
a) Clock synthesis
b) Clock routeing and division
c) Clock output type
The output type is configured to suit the requirements of the AC and FPGA clock inputs and should not be
altered, although unused buffer outputs can be disabled to reduce power consumption. The clock dividers prior to
the buffer outputs are normally configured via the application code but can be customised if required.
In normal use, the AC clock input, driven by the synthesiser, is programmed to run at twice the FPGA clock
input rate, although for low frequency operation this could be modified but this would probably also require
modification of the FPGA code to suit the new clock ratios. There is a 125MHz lower limit on the operating
frequency of the LL, equivalent to a data rate of 250MSps. Lower clock rates may be used by disabling the LL
but are currently not supported. See needs a link :type:target:description thing here- this section Low Frequency
Operationcauses a warning for more information.
Note that the output counters must be re-synchronised using the appropriate command following any
re-programming of the clock circuit; this is built in to the example code.
For clock synthesis, the 1GHz VCXO is controlled by the synthesiser using a 100MHz internal reference. The
clock distribution provides the capability for integer divisions of the VCXO frequency to be used as the AC clock
and the related FPFGA clocks. An external reference can also be used so that the VCXO (and therefore the AC
clock) are locked to this reference. The PLL provides only integer-N synthesis so only integer divisions of 1GHz
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can be used in this mode.Consult the factory for the availability of custom VCXO frequencies for applications
requiring other frequencies.
The external signal source can be used in place of the VCXO as the clock driving the distribution section for the
AC so can be used as the AC clock directly or integer divisions of this source can be used.The maximum
input frequency is 1.2 GHz
See the A 9510 data sheet for further information.
2.7 DAC Selftest
The AC has a number of self-test capabilities built in which are implemented in the example code.
2.7.1 Pattern testing
This consists of writing values of 0xAAAA and 0X5555 in succession. Error flags can be interrogated via the
serial interface to determine the success or otherwise of the data transfers and thereby test the FPGA- AC
interface.
2.7.2 Fifo Test
The AC provides the facility to check for FIFO overruns, which normally should not occur. For applications
where low-level control of register bits has been implemented ( e.g. FIFO_offset position), this provides
confirmation of correct fifo operation.
2.7.3 Selftest
This runs an internal self-test algorithm which requires 400,000 ACCLK cycles, so completes in < 1ms for a
1GHz clock frequency. Pass/fail flags can be interrogated via the serial interface
2. DAC DLL Control
The AC uses a LL to align its input registers with CLK and hence with the data. Any change in the AC
clock frequency (thus CLK and FABRCLK) requires the LL control bits in AC register CONFIG10 to be set
appropriately and the LL re-aligned. This in turn requires the application of a hardware reset as part of the
initialisation sequence so any existing settings will be lost. These settings must be explicitly re-written as part of
the sequence.
The LL control register (address 0xA) in the AC has several different bit fields listed in the data sheet.
Effectively these can be treated as a single bit field since the values to be used for each frequency are fixed
( see "Electrical Characteristics" in the relevant device data sheet). Note that the frequency break points for the
AC5682Z changed from (200,300) and (300,500) to (200,325) and (325,500) in the March 09 data sheet.
AC5681 CLK
(MHz) AC5681Z CLK (MHz) AC5682Z CLK (MHz) Setting
125-150 125-150 125-150 0xC
150-175 150-175 150-175 0xCE
175-200 175-200 175-200 0xCF
200-325 200-325 200-325 0xC8
325-500 325-500 325-500 0xC0
2.9 DAC Sync
The AC configuration sequence requires a rising edge to be generated on the internal SYNC signal to instigate
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data output. This signal is normally controlled by the hardware pin (see register description below), but can be
controlled via the serial interface. SYNC is set low prior to clock adjustment ( and the FPGA-generated data
forced to output a zero level) to minimise transients on the AC outputs. The configuration sequence for the
AC does produce some transients however, a feature of the AC itself rather than the board design.
2.10 Multiple DAC synchronisation
Multiple AC synchronisation requires the use of the hardware SYNC pin; in addition the internal FIFOs of the
ACs to be synchronised must also be aligned with each other. This is achieved by ensuring that bits 5 and 4
of AC register CONFIG5 are initially cleared and the SYNC pin is pulsed high then low. Following this, 5 is set
high and the drive to the AC SYNC pin then set high. This synchronises the AC outputs to within ± 1 AC
clock cycle. See the relevant device data sheet for further information.
2.11 Clocking on Virtex4, Virtex5
CLK, SYNC and data must be produced synchronously for the AC. At maximum speed, the data rate required
is 500 MHz R. This is possible by using the 4:1 OSER ES components on Virtex4 and Virtex5 FPGAs.
On the XRC cards using Virtex4 and Virtex5 FPGAs, only regional clock inputs are available to XMC modules so
global clocks must be generated using these inputs since the data input pins typically span multiple regions.
There is an unknown (and unconstrainable) delay between the I/O pin and the BUFG input which must be taken
into account when doing this.
Figure 5 : Virtex 4 Virtex 5 Clocking Scheme
This delay is eliminated as shown in Figure Clocking Scheme. The clock input is fed to a pair of CMs which
generates the clock required by the OSER ES circuitry. Two CMs are required because of the input and
output clock restrictions of the CM and the range of frequencies ( 125 MHz to 500MHz) which must be
produced. Each CM uses a divide-by-2 pre-scaler to produce FABRCLK at the correct rate.
The output side of the OSER ES is clocked using a copy of the FPGA clock, appropriate to the clock region
occupied by the OSER ES. This is routed via a BUFIO to the OSER ES. The input side of the OSER ES is
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driven by the BUFR signal derived from the BUFIO clock to maintain timing alignment. The global clock signal
which drives the data generation hardware (FABRCLK) runs at the same speed as this. The CM aligns the
global clock with these clocks and a constraint on the path lengths when crossing the clock domains ensures that
data has the required setup and hold.
The BUFR's and BUFIO's required for each FPGA type are automatically instantiated by the clock mapping code;
in most cases only two sets of BUFR's and BUFIO's are used.
Note that the clock(s) produced by the CM do not drive the AC directly, ensuring that any clock jitter added by
the CM is not transferred to the AC.
Clock alignment is controlled by a few state machine components. The "ClockTest" block samples the image of
the incoming clock signal via a R register over a number of cycles and compares the register output with the
value expected for alignment, setting a pass or fail flag accordingly. The "PhaseAdjust" block shifts the CM
phase under the control of the "AlignControl" block.
When triggered via the local bus, the "AlignControl" block samples the pass/fail flag from "Clocktest" for the full
range of phase shifts, determines the optimum setting and then implements this phase offset using
"PhaseAdjust". Once completed, AlignControl signals back to the user application the result of the alignment
operation.
This scheme also ensures that all clocks are constrained within the limits imposed by the various components in
the FPGA for all speed grades of the FPGA. The CM clock runs at half the rate of the CLK rate. Hence for
1GHz AC operation, the BUFIO clock ( CLK) runs at 500 MHz maximum whilst the CM clock (FABRCLK)
runs at 250 MHz maximum.
The BUFR clocks are used to provide diagnostic confirmation of the presence of the clock signals, in the same
way as the spare clock signal noted above. In these cases the "divide-by-2" attribute must be set since the
frequency limit for BUFR signals is 300 MHz maximum.
2.11.1 Low Frequency Operation
The above scheme is suitable for operation down to roughly 100 MHz. Below this frequency the use of the CM
becomes more problematic (e.g. lower frequency limit of 30 MHz). Interpolation techniques could be used to
maintain the clock above the CM limits whilst generating data at a much lower speed, but a simpler clocking
scheme (shown in Figure Low frequency clocking scheme) can be used, which also has the benefit of
simplifying the data generation requirements.
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Figure 6 : Low frequency clocking scheme
Here the data generation in the FPGA runs at the same speed as the AC sample clock fed to the ACs, so the
FPGA generates 1 sample per AC sample clock cycle instead of 4 samples at 0.25 * AC sample clock cycle.
This removes the need for OSER ES, R registers etc and simplifies the interface to the AC and the data
generation.
CM alignment is no longer required since all data generation and output uses the same global clock. The
unconstrained delay which results from using the clock-capable input appears as a simple phase offset, which is
irrelevant since the AC synchronises to the CLK signal generated synchronously with the data via a toggling
bit; data still changes on each edge of this clock. The AC LL Bypass bit is normally set when running in this
mode since the operating speed is typically less than 125 MHz.
Clearly there is some overlap in the clock speed ranges which these two architectures can support which is also
dependent on FPGA speed; the user should choose the one best suited to the application. Code for this style of
operation is not included in the example code.
On Virtex6 and later boards, this restriction does not apply as there is no MMCM used.
2.12 Clocking on Virtex6, Kintex7 and Virtex7
On the A MXRC cards using Virtex6, Kintex7 and Virtex7 FPGAs, clock distribution is simpler. Only one regional
clock input is used as the clock source, selected to be the clock pair which can drive the clock regions above and
the below the one directly clocked by the selected clock pair. This routed via a BUFMR and the BUFRs
(configured to divide by 2) to clock these additional regions and the OSER ES components. The incoming
clocks (at the half the AC clock rate) are distributed via BUFIOs to drive the OSER ES components. The
master BUFR clock is also routed through a global clock buffer to provide the clock for the data generation
circuitry in the FPGA fabric.
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Figure 7 : Kintex 7 Virtex 7 Clocking Scheme
The remaining clock inputs are used for clock monitoring and diagnostic purposes only
2.13 Data Generation
Each AC receives data via a 16-bit R interface, plus CLK, generated by the data source synchronously
with the data. Clock speed restrictions in the FPGA force the use of OSER ES components in order to be able
to run at the full rate (1G sample per second) This in turn means that the data generation circuitry must provide
4 consecutive data samples on each FABRCLK clock cycle.
In the example code this is implemented by instantiating four identical data sources for each type of waveform
produced, each offset by the appropriate amount in order to provide the correct signal for each time slot.
2.14 Performance
Typical performance when producing a 125 MHz sine wave using the internal 1GHz clock is shown below. Note
that the figure shows both the fundamental frequency (Ffund) and the image frequency (Fsample-Ffund) of the
fundamental caused by sampling. The image frequency and higher components are normally filtered out by a
low-pass filter which has a cut-off frequency Fcutoff <= Fsample /2, the midpoint of the figure.
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2.15 Board Layout
Figure : XRM(2)-DAC-D4-1G Layout
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