Alpha Data XRM(2)-DAC-D4/1G User manual

XRM(2)-DAC-D4/1G User Guide
Document Revision: 2.2
Mar , 201

XRM(2)-DAC-D4/1G User Guide
V2.2 - Mar , 201
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XRM(2)-DAC-D4/1G User Guide
V2.2 - Mar , 201
Table Of Contents
1 Introduction ...................................................................................................................................... 1
1.1 Block Diagram ............................................................................................................................... 1
1.2 XRM and XRM2 ............................................................................................................................. 4
1.2.1 Signalling Voltage ...................................................................................................................... 4
1.3 Build Level ..................................................................................................................................... 4
1.4 Alpha Data SDK Versions .............................................................................................................. 4
1.5 Xilinx Tool Versions ........................................................................................................................ 4
1. ISE Projects ................................................................................................................................... 4
1. .1 Structure .................................................................................................................................... 4
1.7 Vivado Projects ..............................................................................................................................
1.7.1 Vivado Folder Structure .............................................................................................................
2 Hardware .......................................................................................................................................... 9
2.1 Hardware Operation ...................................................................................................................... 9
2.2 Connector Signals ......................................................................................................................... 9
2.3 DAC Serial Interface ...................................................................................................................... 9
2.4 DAC Programming ....................................................................................................................... 10
2.5 Synthesiser Serial Interface ......................................................................................................... 10
2. Synthesiser Programming ........................................................................................................... 10
2.7 DAC Selftest ................................................................................................................................ 11
2.7.1 Pattern testing .......................................................................................................................... 11
2.7.2 Fifo Test ................................................................................................................................... 11
2.7.3 Selftest ..................................................................................................................................... 11
2.8 DAC DLL Control ......................................................................................................................... 11
2.9 DAC Sync .................................................................................................................................... 11
2.10 Multiple DAC synchronisation ...................................................................................................... 12
2.11 Clocking on Virtex4, Virtex5 ......................................................................................................... 12
2.11.1 Low Frequency Operation ....................................................................................................... 13
2.12 Clocking on Virtex , Kintex7 and Virtex7 ..................................................................................... 14
2.13 Data Generation .......................................................................................................................... 15
2.14 Performance ................................................................................................................................ 15
2.15 Board Layout ............................................................................................................................... 1
3 VHDL Structure .............................................................................................................................. 1
3.1 Introduction .................................................................................................................................. 18
3.2 Major HDL Components .............................................................................................................. 18
3.2.1 Clock generation and alignment .............................................................................................. 18
3.2.2 Data Generation and Output .................................................................................................... 18
3.2.3 Local bus interface ................................................................................................................... 19
3.2.3.1 Virtex4, Virtex5 ..................................................................................................................... 19
3.2.3.2 Virtex , Virtex7, Kintex7 ....................................................................................................... 19
3.2.4 Serial Control ........................................................................................................................... 19
3.2.5 Digital I/O ................................................................................................................................. 20
3.2. General Purpose I/O ................................................................................................................ 20
3.2.7 Host Access via Local Bus ....................................................................................................... 20
3.2.7.1 Virtex4, Virtex5 ..................................................................................................................... 20
3.2.7.2 Virtex , Virtex7, Kintex7 ....................................................................................................... 21
3.3 Waveform Generator Operation .................................................................................................. 22
3.3.1 Sine Waveform Generator ....................................................................................................... 22
3.3.2 Ramp Waveform Generator ..................................................................................................... 23
3.3.3 Triangle Waveform Generator .................................................................................................. 23
3.3.4 Square/Pulse Waveform Generator ......................................................................................... 24
3.3.5 Arbitrary Waveform Generator ................................................................................................. 24
3.3. Self Test Pattern ..................................................................................................................... 25

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3.3.7 Sine Test ................................................................................................................................. 25
4 Register Description ...................................................................................................................... 26
4.1 FPGA_CNTRL_REG (0x00) ........................................................................................................ 28
4.2 FPGA_STATUS_REG (0x01) ...................................................................................................... 30
4.3 CNTR_STAT_REG (0x02) ........................................................................................................... 32
4.4 I_DDS_REG (0x03) ..................................................................................................................... 34
4.5 Q_DDS_REG (0x04) ................................................................................................................... 3
4. I_INC_REG (0x05) ....................................................................................................................... 38
4.7 Q_INC_REG (0x0 ) ..................................................................................................................... 40
4.8 SYNTH_CNTRL_REG (0x07) ...................................................................................................... 42
4.9 SYNTH_STRB_REG (0x08) ........................................................................................................ 44
4.10 IDAC_CNTRL_REG (0x09) ......................................................................................................... 4
4.11 IDAC_STRB_REG (0x0A) ........................................................................................................... 48
4.12 QDAC_CNTRL_REG (0x0B) ....................................................................................................... 50
4.13 QDAC_STRB_REG (0x0C) ......................................................................................................... 52
4.14 DEVICE_REG (0x0D) .................................................................................................................. 54
4.15 I_DDSINIT_REG(0x0E) ............................................................................................................... 5
4.1 Q_DDSINIT_REG(0x0F) ............................................................................................................. 58
4.17 IPATTERN_REG (0x10) ............................................................................................................... 0
4.18 QPATTERN_REG (0x11) ............................................................................................................. 2
4.19 IPATTERN_REG2 (0x12) ............................................................................................................. 4
4.20 QPATTERN_REG2 (0x13) ...........................................................................................................
4.21 MEAS0_VAL_REG (0x14) ........................................................................................................... 8
4.22 MEAS1_VAL_REG (0x15) ........................................................................................................... 70
4.23 MEAS2_VAL_REG (0x1 ) ........................................................................................................... 72
4.24 FREERUN_CNT_REG (0x17) ..................................................................................................... 74
4.25 I_ARBWRITE_REG (0x18) .......................................................................................................... 7
4.2 Q_ARBWRITE_REG (0x19) ........................................................................................................ 78
4.27 ARB _CNTRL_REG (0x1A) ......................................................................................................... 80
4.28 ARB _TICK_REG (0x1B) ............................................................................................................. 82
4.29 AUXCNTRL_REG (0x1E) ............................................................................................................ 84
4.30 PHASE_VALUE_REG (0x1F) ...................................................................................................... 8
List of Tables
Table 1 SMA and UFL Connectors .............................................................................................................. 17
Table 2 Clock Muxing ( 25, 24) .................................................................................................................. 29
List of Figures
Figure 1 Block iagram ................................................................................................................................... 3
Figure 2 efault Project Structure .................................................................................................................... 5
Figure 3 Vivado Project Structure .................................................................................................................... 6
Figure 4 Vivado Files ....................................................................................................................................... 8
Figure 5 Virtex 4 Virtex 5 Clocking Scheme ................................................................................................... 12
Figure 6 Low frequency clocking scheme ...................................................................................................... 14
Figure 7 Kintex 7 Virtex 7 Clocking Scheme .................................................................................................. 15
Figure 8 XRM(2)- AC- 4-1G Layout ............................................................................................................ 16
Figure 9 Waveform Selection iagram .......................................................................................................... 22

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1 Introduction
Alpha ata provide three variants of a fast analogue signal generation card operating at sampling frequencies
up to 1 GHz, based on the AC5681, AC5681Z and AC5682Z devices from Texas Instruments.
The AC5681 provides a non-interpolating architecture for wideband signal generation.
The AC5681Z implements an interpolating architecture and provides filtering and mixing circuitry and is
essentially a single-channel version of the AC5682Z.
The AC5682Z also has an interpolating architecture and provides filtering and mixing circuitry for the two ACs
contained within the package. Note that in this case the second AC output in each package is not accessible,
although the data can be processed and combined internally as two channels.
All versions utilise a common circuit board with build options being used to match the board configuration to the
AC fitted.
These boards differ only in the following aspects:
a) The AC fitted - the AC5681/ AC5681Z version uses a single channel AC normally aimed at
producing wide bandwidth signals. The AC5682Z has 2 full AC channels, which allows signal
generation from complex data streams.
b) Minor differences in pin functions.
c) Register addresses and bit allocations for the internal AC registers in the AC581Z and AC5682Z are
supersets of those in the AC5681.
d) Inclusion of a PLL on the interpolating devices ( AC5681Z, AC5682Z) for AC sample clock generation
from a reference clock. In normal circumstances this facility is not used since because of the limited set of
frequencies that can be produced, but if used the high-frequency clocks required for the FPGA must be
synthesised in the FPGA fabric using MMCM or CM.
These XRM modules are compatible with Alpha- ata's family of FPGA cards fitted with Virtex 4, Virtex 5, Virtex
6, Kintex 7 and Virtex 7 devices.
Both configurations are referred to in this document by the generic title XRM(2)- AC- 4-1G; where required,
any AC-specific differences will be made explicit.
The code and hardware descriptions given below reflect the functions implemented at the date of this document.
1.1 Block Diagram
The block diagram (see Figure Block iagram) shows the major components of the XRM(2)- AC- 4-1G board.
The AC has its own dedicated power supplies and uses a mixture of single-ended (serial control) and
differential (data, clocks and synchronisation) signals to/from the FPGA. A clock synthesis/distribution circuit is
included to provide flexible clock generation options.
edicated serial interfaces are implemented in the VH L code to communicate with the AC and the
synthesiser. These interfaces are initialised automatically by the FPGA as part of the reset sequence.
AC sample data is transferred to each AC from the FPGA via 16 LV S pairs plus synchronisation (SYNC)
and data clock ( CLK) differential pairs. The data clock ( CLK), synchronous with the data, is generated from a
half-rate copy of the AC clock ( ACCLK). The CLK signal runs at 0.5 * the AC clock rate present on the
clock input connector. Within the FPGA the CLK is further divided by 2 for use as a global clock (FABRCLK) for
data generation, so runs at 0.25 * ACCLK.
The synthesiser/distribution circuit provides three options for clocking the AC.
a) Internal reference, internally synthesised clock, giving integer sub-divisions, including 1, of 1GHz.
b) Externally generated clock, integer sub-divisions, including 1.
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c) External reference, internally synthesised clock, giving integer sub-divisions of 1GHz.
A pair of LVTTL outputs ('TRIG' and 'AUX') is provided (3V3 signal levels) via SMA connectors. In addition, two
direct connections to FPGA pins via UFL connectors are also available for fast signalling interconnect between
multiple AC cards or other devices.
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Figure 1 : Block Diagram
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1.2 XRM and XRM2
The latest generation of FPGA cards from Alpha ata use a modified version of the XRM interface originally
implemented on legacy FPGA (Virtex4, Virtex5) cards. From a user viewpoint these two interfaces are identical
so references to 'XRM' signals refer also to XRM2 implementations. Where any differences between the two
interfaces are relevant to the operation of the XRM module they will be explicitly stated in the text.
On the XRM(2)- AC- 4 the principal difference lies in how the I/O voltages for the banks connected to the XRM
are set.
1.2.1 Signalling Voltage
The signals to the AC are mainly LV S, with some single-ended signals for serial interfaces etc. ifferential
termination is used in the FPGA for clocks etc. which requires that the signalling voltage is set to a suitable level
on the host FPGA card. FPGA cards using the XRM2 interface (e.g. Virtex6, Virtex7 etc.) this voltage is set
automatically. On the XRM interface (boards fitted with Virtex4 or Virtex5) this should be set manually to 2v5.
This voltage level is required solely to ensure correct termination values in the FPGA; the AC board will not be
damaged if this voltage is inadvertently set to 3v3.
Single-ended signals are all level-translated to hsift signals to/from the device signalling levels to theat of the
FPGA I/O bank supply being used.
1.3 Build Level
The description in this document refer to release 5.0 of the xrm_dac_d4_1g code, dated 15/11/17. Current board
hardware revision is rev 6 and this code supports rev 3 and later builds. Contact the factory for support for board
versions earlier than rev 3.
1.4 Alpha Data SDK Versions
All VH L code for legacy boards is built using Alpha ata's S K version 4.9.3. This S K version is frozen at this
revision.
All VH L code for current boards uses Alpha ata's A MXRCG3S K version 1.7.0.
1.5 Xilinx Tool Versions
The VH L can be synthesised using either ISE or Vivado. Only FPGA cards fitted with Virtex7 or Kintex7 FPGAs
are supported in Vivado.
The currently supported version of ISE for synthesis and bitfile generation is version 14.7.
The currently supported version of Vivado for synthesis and bitfile generation is version 2017.2.
1.6 ISE Projects
1.6.1 Structure
The example code for ISE builds runs this in batch mode, using makefiles to control the various steps that are
required, based on the methodology used in the both variants of Alpha ata S Ks. The files required for each
FPGA card type are defined in a file with the extension 'prj'; the switches necessary for guiding synthesis, map,
place and route, and bit file generation are defined for each FPGA type in files with the 'scr' extension.
The file paths defined in the prj file reflect the structure of the example code; any changes to the project structure
must be reflected in the paths defined in the prj file.
The default project structure is shown below; this includes the additional folder for the Vivado version of the
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project (highlighted).
Figure 2 : Default Project Structure
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1.7 Vivado Projects
1.7.1 Vivado Folder Structure
The additional folder present in the standard release 'FPGA' folder for producing bitfiles using Vivado is
highlighted. In the case shown, this additional folder is called 'vivado' and is referred to as the main Vivado folder
in this discussion. This folder name be any legal name as long as the paths (relative and absolute) to the S K
files, the project source and the project core files is preserved. In other words it should be at the same level of
the folder hierarchy as the 'source' and 'cores' folders. Any change in these paths will require modifications to
paths defined in TCL scripts.
The generation of project files for Vivado uses scripts based on those in the Vivado examples provided by the
S K. The TCL files automate the generation of Vivado project(s), which ensures that the xpr files produced
include all settings required for correct configuration of both synthesis and post-synthesis file generation.
Specifying these options manually is unlikely to set all options correctly so it is strongly recommended that the
TCL files are used to generate project files and folder structures.
This uses the same 'design-model-device' syntax as the Alpha ata S K examples, where the 'design' equates
to the XRM type, the 'model' equates to the A MXRC board type and the 'device' equates to the specific FPGA
on the FPGA card. In this case the 'device' field is fixed since these designs are for a specific XRM.
Figure 3 : Vivado Project Structure
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