Alpha Data ADM-VPX3-9Z5-RTM User manual

ADM-VPX3-9Z5-RTM
User Manual
Document Revision: 1.1
1 th August 2022

ADM-VPX3-9Z5-RTM User Manual
V1.1 - 1 th August 2022
© 2022 Copyright Alpha Data Parallel Systems Ltd.
All rights reserved.
This publication is protected by Copyright Law, with all rights reserved. No part of this
publication may be reproduced, in any shape or form, without prior written consent from Alpha
Data Parallel Systems Ltd.
Head Office
Address: Suite L4A, 160 Dundee Street,
Edinburgh, EH11 1DQ, UK
elephone: [phone]
Fax: [phone]
email: [email protected]
website: http://www.alpha-data.com
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10822 West oller Drive, Suite 250
Littleton, CO 80127
[phone]
[phone] - toll free
[email protected]
http://www.alpha-data.com
All trademarks are the property of their respective owners.

ADM-VPX3-9Z5-RTM User Manual
V1.1 - 1 th August 2022
able Of Contents
1 Introduction ...................................................................................................................................... 1
1.1 Key Features ................................................................................................................................. 1
1.2 eferences & Specifications .......................................................................................................... 2
2 Installation ........................................................................................................................................ 3
2.1 Software Installation ...................................................................................................................... 3
2.2 Hardware Installation ..................................................................................................................... 3
2.2.1 Handling Instructions ................................................................................................................. 3
3 Functional Description .................................................................................................................... 4
3.1 Block Diagram ............................................................................................................................... 4
3.2 Assembly Drawing ......................................................................................................................... 5
3.3 Connector Definitions .................................................................................................................... 6
3.4 LED Definitions .............................................................................................................................. 7
3.5 JTAG Interface ............................................................................................................................... 7
3.5.1 On-board Interface ..................................................................................................................... 7
3.5.2 JTAG Voltages ........................................................................................................................... 7
3.6 HS MIO Interfaces ......................................................................................................................... 8
3.7 Ethernet Phy Interface Signals ...................................................................................................... 8
3.8 Display Port AUX signals ............................................................................................................... 8
3.9 SATA Connectors ........................................................................................................................... 9
3.10 FireFly Connectors ........................................................................................................................ 9
3.11 CAN BUS Header .......................................................................................................................... 9
3.12 S232 Dtype ............................................................................................................................... 10
3.13 GPIO Headers ............................................................................................................................. 10
List of ables
able 1 References ........................................................................................................................................ 2
able 2 Connector Definitions ........................................................................................................................ 6
able 3 LED Definitions .................................................................................................................................. 7
able 4 MDIO pins .......................................................................................................................................... 8
able 5 DPAUX pins ....................................................................................................................................... 8
able 6 SA A Connections ............................................................................................................................. 9
able 7 Firefly Connectors .............................................................................................................................. 9
able 8 Header J12 ........................................................................................................................................ 9
able 9 Header J5 ........................................................................................................................................ 10
able 10 Header J1 ........................................................................................................................................ 10
able 11 Header J2 ........................................................................................................................................ 11
able 12 Header J15 ...................................................................................................................................... 11
List of Figures
Figure 1 ADM-VPX3-9Z5-R M ........................................................................................................................ 1
Figure 2 ADM-VPX3-9Z5-R M Block Diagram ................................................................................................ 4
Figure 3 ADM-VPX3-9Z5-R M op View ......................................................................................................... 5
Figure 4 LED Locations ................................................................................................................................... 7
Figure 5 HS-MIO Configuration ....................................................................................................................... 8

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ADM-VPX3-9Z5-RTM User Manual
V1.1 - 1 th August 2022
1 Introduction
he ADM-VPX3-9Z5-R M is a 3U, VPX, Rear ransition Module (R M) designed to interface with Alpha Data
ADM-VPX3-9Z5 Zynq Ultrascale+ FPGA board.
he ADM-VPX3-9Z5-R M provides complete breakout of all backplane signals providing the user with complete
flexibility during development and debug.
Figure 1 : ADM-VPX3-9Z5-RTM
1.1 Key Features
PS GTR IO
• IO Connectors from the G R lanes from the PS side of the ADM-VPX3-9Z5:
• One Gigabit Ethernet RJ45 port, available on the front panel
• 1 SA A interface, via an internal standard connector
• 1 DisplayPort interface, 2 lanes wide, available via the front panel
• 1 Serial COM port interfaces, available on the front panel
• 1 Serial CAN BUS interfaces, available on an internal header
• R C Battery connection header
• GPIOs routed to an internal header which can be looped back via jumper links (for internal testing).
• 12 HSSIO differential pairs - connected to G H lanes on the PL side of the ADM-VPX3-9Z5:
• wo Firefly connectors (8 HSSIO pairs)
• 4 SA A interfaces, via internal standard connectors (4 HSSIO pairs)
• Xilinx J AG programming header
Page 1Introduction
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1.2 References & Specifications
ANSI/VI A 46.0 VPX Baseline Standard, October 2007, VI A, ISBN 1-885731-44-2
ad_ug_1341 ADM-VPX3-9Z5 User Manual, June 2021, Alpha Data, -
Table 1 : References
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2 Installation
2.1 Software Installation
Please refer to the ADM-VPX3-9Z5 area on the Alpha-Data support site for access to system monitoring utilities,
documentation and FPGA reference designs.
2.2 Hardware Installation
2.2.1 Handling Instructions
he components on this board can be damaged by electrostatic discharge (ESD). o prevent damage, observe
ESD precautions:
- Always wear a wrist-strap when handling the card
- Hold the board by the edges
- Avoid touching any components
- Store in ESD safe bag.
Page 3Installation
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3 Functional Description
3.1 Block Diagram
Figure 2 : ADM-VPX3-9Z5-RTM Block Diagram
Page 4 Functional Description
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3.2 Assembly Drawing
FM3
R1
R2
FM4
BT1
R25
R67
R24
R23
C1
C2
R77
D1
R76
R96
R87
R86
C154
C153
C139
C138
J12
C140 R78
U13
R89
R88
C156
C155
C113C111
U5
R79
C67
U6
R53
C119
D3
U9
J15
C44
C69 C51
C73
C87
C46
C93 C89
C43
C45
R91
R90
C158
C157
C112
C122
C121
C120
C50
C52
C68
C115
C114
D2
R52R55
C42
L5
R43
U7
R46
C104
C110
C109
C108
C107
R93
R92
C160
C159
R73R72 R74 R75
C116
U4
FM2
C137
U12
C133 C132
C130
C136
F1
U2
C161
FM1
R66
R65
R94
R40
R63
R64
C134 C135
D4
D5
R95
RP2
RP1
RP0
K2
K1
JP1
J13 J7
J4
JP2
J14 J6
J16
J1
J17
J3
J18
J11
J8
J19
H2
J10
H1
J5
R97R98
R99
R100
R101
TP1TP2 TP3
TP4
TP5
LP1
1
A
K
Figure 3 : ADM-VPX3-9Z5-RTM Top View
Page 5Functional Description
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3.3 Connector Definitions
he description of the connectors on the board status shown below:
Comp. Ref. Function
JP1 NVMRO - not required on ADM-VPX3-9Z5
JP2 GPIO Enable. position 1-2 = GPIO Headers Disabled : 2-3 = Enabled
J12 CANBUS Header
J10 DisplayPort Connector
B 1 R C Battery Holder
J1+J3 GPIO Headers
J11 Xilinx Programming cable Connector
J4 PS side SA A interface
J16-J19 PL side SA A connectors
J5 RS232 Serial Port
J6-J7 Firefly Connector 0
J13-J14 Firefly Connector 1
J8 Ethernet
J15 GPIO Header
Table 2 : Connector Definitions
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3.4 LED Definitions
he position and description of the board status LED is shown in LED Locations:
D3
D4 D5
Figure 4 : LED Locations
Comp. Ref. Function ON State Off State
D3(Green) Display Port 3.3V Supply Status Normal operation Fault
D4(Green) PSMIO31 LED PSMIO=Logic Low PSMIO=Logic High
D5(Green) 3.3V Supply Status Normal operation Power Off
Table 3 : LED Definitions
3.5 JTAG Interface
3.5.1 On-board Interface
he J AG boundary scan chain can be accessed via a standard header (J11).
his allows the connection of the Xilinx J AG cable for FPGA debug and Flash programming via the Xilinx
toolchain.
3.5.2 JTAG Voltages
he Vcc supply provided to the J AG cable on the config header is +3.3V and is protected by a poly fuse rated at
350mA.
Page 7Functional Description
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3.6 HS MIO Interfaces
he ADM-VPX3-9Z5-R M allows support for the following PS G R interfaces: displayport, ethernet and SA A.
In order for the interfaces to be routed out correctly he PS G R serial interfaces should be configured as
highlighted in the table below:
Figure 5 : HS-MIO Configuration
3.7 Ethernet Phy Interface Signals
he reset_n pin of the Ethernet Phy is connected directly to the VPX system reset.
he Ethernet Phy MDIO BUS interface should be configured as shown in the table below:
Signal Name FPGA Pin
MDC PSMIO76 (AH31)
MDIO PSMIO77 (AG31)
Table 4 : MDIO pins
3. Display Port AUX signals
he Display Port AUX interface should be configured as shown in the table below:
Signal Name FPGA Pin
DP_AUX_OU PSMIO34 (P27)
DP_HPD PSMIO35 (N29)
DP_OE PSMIO36 ( 27)
DP_AUX_IN PSMIO37 (N30)
Table 5 : DPAUX pins
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ADM-VPX3-9Z5-RTM User Manual
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3.9 SATA Connectors
he ADM-VPX3-9Z5-R M board has five standard right angle SA A receptacles for use with SA A compliant
storage devices.
One of the SA A devices is connected to the PS side and the remainder are connected to the PL side.
Connector Signal FPGA Bank "P" pin "N" pin
PS_SA A (J4) PS_ X0 PS Bank 505 AH39 AH40
PS_RX0 PS Bank 505 AG41 AG42
PL_SA A0 (J16) DP2_C2M MG Quad 226 AL6 AL5
DP2_M2C MG Quad 226 AM4 AM3
PL_SA A1 (J17) DP3_C2M MG Quad 226 AK8 AK7
DP3_M2C MG Quad 226 AL2 AL1
PL_SA A2 (J18) DP2_C2M MG Quad 226 AJ6 AJ5
DP2_M2C MG Quad 226 AK4 AK3
PL_SA A3 (J19) DP3_C2M MG Quad 226 AH8 AH7
DP3_M2C MG Quad 226 AJ2 AJ1
Table 6 : SATA Connections
3.10 FireFly Connectors
Connector Ref Des FPGA Bank
0 J6-J7 MG Quad 227
1 J13-J14 MG Quad 228
Table 7 : Firefly Connectors
3.11 CAN BUS Header
he CAN BUS interface should be configured to PSMIO40/PSMIO41 (pins P28/P30) on the PS side of the FPGA
on the ADM-VPX3-9Z5 board.
Pin Signal Name
1 GND
2 GND
3 CAN_GND
4 CAN_H
5 CAN_L
6 CAN_GND
7 CAN_L
8 CAN_H
Table : Header J12
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3.12 RS232 Dtype
Pin Signal Name FPGA Pin
1 - -
2 XD PSMIO39 (P29)
3 RXD PSMIO38 (R27)
4 - -
5 GND -
6 - -
7 - -
8 - -
9 - -
Table 9 : Header J5
3.13 GPIO Headers
Pin Signal Name FPGA Pin
1 P1_GP_1V8_P_10 AU11
2 P1_GP_1V8_P_9 AW11
3 P1_GP_1V8_N_10 AV11
4 P1_GP_1V8_N_9 AW10
5 GP4_1V8_P AJ15
6 GP3_1V8_P AM13
7 GP4_1V8_N AK15
8 GP3_1V8_N AN13
9 GP2_1V8_P AN14
10 GP1_1V8_P AJ14
11 GP2_1V8_N AP14
12 GP1_1V8_N AK14
Table 10 : Header J1
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Pin Signal Name FPGA Pin
1 P1_GP_1V8_P_12 BB5
2 P1_GP_1V8_P_11 AV12
3 P1_GP_1V8_N_12 BB4
4 P1_GP_1V8_N_11 AW12
5 GP8_1V8_P AM11
6 GP7_1V8_P AM10
7 GP8_1V8_N AN11
8 GP7_1V8_N AN10
9 GP6_1V8_P AL15
10 GP5_1V8_P AL14
11 GP6_1V8_N AM15
12 GP5_1V8_N AM14
Table 11 : Header J2
Pin Signal Name FPGA Pin
1 GP_SE_3V3_5 D2
2 GP_SE_3V3_2 C3
3 GP_SE_3V3_4 C5
4 GP_SE_3V3_3 C6
5 GP_SE_3V3_6 C1
6 GP_SE_3V3_1 C4
7 GP_SE_3V3_7 D4
8 GP_SE_3V3_0 B1
Table 12 : Header J15
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ADM-VPX3-9Z5-RTM User Manual
V1.1 - 1 th August 2022
Revision History
Date Revision Nature of Change
08 June 2021 1.0 Initial Release
18 August 2022 1.1 Added extra detail to tables
Address: Suite L4A, 160 Dundee Street,
Edinburgh, EH11 1DQ, UK
elephone: [phone]
Fax: [phone]
email: [email protected]
website: http://www.alpha-data.com
Address: 10822 West oller Drive, Suite 250
Littleton, CO 80127
elephone: [phone]
Fax: [phone] - toll free
email: [email protected]
website: http://www.alpha-data.com
5.0