Altera timequest User manual

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TimeQuest Timing Analyzer
Quick Start Tutorial
Software Version: 9.1
Document Version: 1.1
Document Date: © December 2009
UG-TMQSTANZR-1.1

Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
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UG-TMQSTANZR-1.1

© December 2009 Altera Corporation TimeQuest Timing Analyzer Quick Start Tutorial
Contents
Chapter 1. About this Tutorial
Chapter 2. Quick Start Tutorial
System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Step 1: Open and Setup Your Design in the Quartus II Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Step 2: Setup the TimeQuest Timing Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Step 3: Perform Initial Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Step 4: Launch the TimeQuest Timing Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Step 5: Create a Post-Map Timing Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Step 6: Specify Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Step 7: Update the Timing Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Step 8: Save the Synopsys Design Constraints (SDC) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Step 9: Generate Timing Reports for the Initial Timing Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Step 10: Save Constraints to an SDC File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Step 11. Perform Timing-Driven Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
Step 12. Verify Timing in the TimeQuest Timing Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
Chapter 3. Script Examples
Commands and Tcl Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Additional Information
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About–1

iv
TimeQuest Timing Analyzer Quick Start Tutorial © December 2009 Altera Corporation

© December 2009 Altera Corporation TimeQuest Timing Analyzer Quick Start Tutorial
1. About this Tutorial
This tutorial describes the steps to constrain and perform static timing analysis with
the TimeQuest Timing Analyzer. For this tutorial, use the fir_filter design that ships
with the Quartus®II software. Figure 1–1 shows the fir_filter design schematic.
Figure 1–1. fir_filter Design Schematic

1–2 Chapter 1: About this Tutorial
TimeQuest Timing Analyzer Quick Start Tutorial © December 2009 Altera Corporation

© December 2009 Altera Corporation TimeQuest Timing Analyzer Quick Start Tutorial
2. Quick Start Tutorial
System Requirements
For this tutorial, use Stratix, Cyclone, MAX II, or newer device families (you can also
use MAX 3000 and MAX 7000 device families) with the Quartus®II software
beginning with version 6.0. APEX, FLEX, and Mercury device families are not
supported.
Procedures
Use the following steps to constrain and analyze a design with the TimeQuest Timing
Analyzer. Each step includes the GUI procedure and the command-line equivalent.
Step 1: Open and Setup Your Design in the Quartus II Software
In the Quartus II software, browse to and open the fir_filter located in the
<qdesign folder>/fir_filter/ folder. Use the GUI or the command-line equivalent
procedures in Table 2–1.
Step 2: Setup the TimeQuest Timing Analyzer
By default, the Quartus II software uses the Classic Timing Analyzer as the timing
analysis tool for designs targeting the Cyclone device family. Specify the TimeQuest
Timing Analyzer as the timing analysis tool in the Quartus II software to use in the
compilation flow for the fir_filter project.
1This step is not required for all projects. The newer FPGA families default to the
TimeQuest Timing Analyzer.
Specify the TimeQuest Timing Analyzer as the timing analysis tool in the Quartus II
software with the procedures in Ta b l e 2–2 .
Table 2–1 . Opening and Setting Up Your Design
Quartus II Software GUI Command Line
On the File menu, click Open Project and browse to the
project file <Quartus II Installation
Folder>\qdesigns\fir_filter\fir_filter.qpf.
Type:
quartus_sh –s r
project_open fir_filter -revision \
filtref r

2–2 Chapter 2: Quick Start Tutorial
Procedures
TimeQuest Timing Analyzer Quick Start Tutorial © December 2009 Altera Corporation
Step 3: Perform Initial Compilation
Before applying timing constraints to the design, create an initial database with the
procedures in Table 2–3. The initial database is generated from the post-map results of
the design.
The Analysis & Synthesis step generates a post-map database.
1You can also create a post-fit netlist for the initial database. However, creating a
post-map is less time consuming and is sufficient for this tutorial example.
Step 4: Launch the TimeQuest Timing Analyzer
Launch the TimeQuest Timing Analyzer to create and verify all timing constraints and
exceptions with the procedures in Table 2–4. This command opens the TimeQuest
shell.
1When you launch the TimeQuest Timing Analyzer directly from the Quartus II
software, the current project is automatically opened.
If you use the GUI, select No when the following message appears:
"No SDC files were found in the Quartus Settings File and filtref.sdc doesn't exist.
Would you like to generate an SDC file from the Quartus Settings File?"
Table 2–2 . Specifying the TimeQuest Timing Analyzer as Default
Quartus II Software GUI Command Line
1. On the Assignments menu, click Settings. The Settings
dialog box appears.
2. In the Category list, select Timing Analysis Settings
3. Turn on Use TimeQuest Timing Analyzer during
compilation.
4. Click OK.
Type:
set_global_assignment -name \
USE_TIMEQUEST_TIMING_ANALYZER ON r
To close the project, type: project_close exit r
Table 2–3 . Performing Initial Compilation (Note 1)
Quartus II Software GUI Command Line
On the Processing menu, point to Start and click Start
Analysis & Synthesis.
Type: quartus_map filtref r
Note to Tab le 2 –3:
(1) The quartus_map is used to create a post-map database.
Table 2–4 . Launching the TimeQuest Timing Analyzer
Quartus II Software GUI Command Line
On the Tools menu, click TimeQuest Timing Analyzer. Type:
quartus_sta –s r
project_open fir_filter -revision filtref r

Chapter 2: Quick Start Tutorial 2–3
Procedures
© December 2009 Altera Corporation TimeQuest Timing Analyzer Quick Start Tutorial
Step 5: Create a Post-Map Timing Netlist
Before specifying the timing requirements, create a timing netlist. You can create a
timing netlist from a post-map or post-fit database. In this step, create a timing netlist
from the post-map database you created in “Step 3: Perform Initial Compilation” with
the procedures in Table 2–5.
1You cannot use the Create Timing Netlist command in the Task s pane to create a
post-map timing netlist. By default, the Create Timing Netlist requires a post-fit
database.
Step 6: Specify Timing Requirements
You must define two clocks in the fir_filter design. Refer to Table 2–6 for a list of
properties for each clock.
Create the clocks in the fir_filter design and assign the proper clock ports with the
procedures in Table 2–7.
fFor more information about constraints supported by the TimeQuest Timing
Analyzer, refer to the TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II
Handbook.
1By default, the create_clock command assumes a 50/50 duty cycle if the
-waveform option is not used.
Table 2–5 . Creating a Post-Map Timing Netlist
TimeQuest Timing Analyzer GUI TimeQuest Timing Analyzer Console
1. On the Netlist menu, click Create Timing Netlist. The
Create Timing Netlist dialog box appears.
2. Under Input netlist, select Post-Map.
3. Click OK.
Type: create_timing_netlist –post_mapr
Table 2–6 . Clocks in fir_filter Design
Clock Port Name Requirement
clk 50 MHz with a 50/50 duty cycle
clkx2 100 MHz with a 60/40 duty cycle
Table 2–7 . Creating Clocks and Assigning Clock Ports
TimeQuest Timing Analyzer
GUI TimeQuest Timing Analyzer Console
1. On the Constraints menu,
click Create Clock. The
Create Clock dialog box
appears.
2. Specify the parameters in
Table 2–2 for the 50 MHz
clock. Repeat these step for
the 100 MHz clock.
Type:
#create the 50 MHz (20 ns) clock
create_clock –period 20 [get_ports clk] r
#create the 100 MHz (10 ns) clock
create_clock –period 10 –waveform {0 6} [get_ports clkx2] r

2–4 Chapter 2: Quick Start Tutorial
Procedures
TimeQuest Timing Analyzer Quick Start Tutorial © December 2009 Altera Corporation
fFor more information about creating clocks of different duty cycles, refer to the
TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook.
After you complete the procedure shown in Table 2–7, the clock definition is
complete.
Step 7: Update the Timing Netlist
After you create timing constraints or exceptions, update the timing netlist to apply
all timing requirements to the timing netlist (the new clk and clkx2 clock
constraints) with the procedures in Table 2–8.
1You must update the timing netlist whenever new timing constraints are applied.
Step 8: Save the Synopsys Design Constraints (SDC) File
You have the option of creating an SDC file after specifying the clock constraints for
the design and updating the timing netlist with the procedures in Table 2–9.
Constraints that have been specified with the TimeQuest Timing Analyzer GUI or in
the console are not automatically saved.
1If you inadvertently overwrite any of your constraints later in the design flow, use this
initial SDC file to restore all of your constraints.
The initial SDC file can act as the “golden” SDC file that contains the original
constraints and exceptions for the design.
The new filtref.sdc file contains the constraints and false path exceptions for the two
clocks that you defined in “Step 6: Specify Timing Requirements”.
The Write SDC File command can overwrite any existing SDC file. When this occurs,
the new SDC file does not maintain order or comments. Therefore, Altera
recommends saving a golden SDC file separately that you can manually edit with a
text editor. This allows you to enter comments and organize the file to your own
specifications.
Table 2–8 . Updating the Timing Netlist
TimeQuest Timing Analyzer GUI TimeQuest Timing Analyzer Console
In the Task s pane, double-click the Update Timing Netlist
command.
Type: update_timing_netlist r
Table 2–9 . Saving the SDC File
TimeQuest Timing Analyzer GUI TimeQuest Timing Analyzer Console
1. In the Tasks pane, double-click the Write SDC File
command. The Write SDC File dialog box appears.
2. Enter filtref.sdc in the File Name field.
Type: write_sdc filtref.sdc r