Altera Classic Product guide

Data Book

September 1991

2610 Orchard Parkway
San Jose, CA 95134-2020
[phone]
Applications Hotline:
1 (800) 800-EPLD
Marketing Information:
[phone]
Altera, MAX, MAX+PLUS, LogicMap, and LogiCaps are registered trademarks of Altera Corporation. Th
following are trademarks of Altera Corporation: MAX+PLUS II, AHDL, MPLD, MCMap, MCKit, SALSA
ADLIB, ASMILE, ASM, SAMSIM, PLAESW, SDP, A+PLUS, Turbo Bit, MAX 5000, MAX 7000, Classic, STC
SAM, PLDS-HPS, PLDS-ENCORE, PLD5-MAX, PLCAD-SUPREME, PLD5-SAM, PLDS-MCMAP, PL5-rm:
PLS-OS, PLS-ES, PLS-MAX, PLS-SUPREME, PLS-SAM, PLS-MCKIT, PL5-WS/SN, PL5-WS/HP, PL5-EDII
EP310, EP320, EP330, EP600,
EP61O, EP61OA, EP61OT, EP630, EP900, EP910, EP91OA, EP91OT, EP1800, EP181C
EP181OT, EP1830, EPM5016, EPM5032, EPM5064, EPM5128,EPM5130, EPM5192, EPM7032, EPM7064, EPM709l
EPM7128, EPM7160, EPM7192, EPM7256, EPM7320,EPM7384, EPM7512,EPM7768, EPM71024,EPS448, EPS46.J
EPB2001, EPB2002A, MP1810, MPM5032, MPM5064, MPM5128,MPM5130,MPM5192, MPS464. Product desigJ
elements and mnemonics are Altera Corporation copyright. Altera Corporation acknowledges the trademark
of other organizations for theirrespective products or services mentioned in this document, specifically: Tangl
and TangoPLD are trademarks of Accel Technologies, Incorporated. Amadeus is a trademark of Cadenc
Design Systems, Incorporated. MacABEL is a trademark of Capilano Computing Systems Ltd. FutureNet is
registered trademark and DASH, ABEL, LogicPak, and UniSite are trademarks of Data I/O Corporatior
ISDATA LOG/ iC is a registered trademark of ISDATA GmbH CUPL,MacCUPL, and ALLPRO are trademark
ofLogical Devices,Incorporated. NETED, PLDSynthesis, QuickSimII, and AutoLogic are trademarks of Mento
Graphics Corporation. PLDesigner and PGADesigner are trademarks of Minc Incorporated. ValidGE[
SystemPLD, SystemPGA, Viewsim, and RapidSim are trademarks of Valid Logic Systems, Incorporatec
Viewlogic,
Viewdraw, and Viewwave are registered trademarks and Viewsim/SD is a trademark of Viewlogi
Systems, Incorporated. ATGEN, AADELA
Y, and AAMAX are trademarks of Acugen Software, Incorporatec
Dazix is a
trademark of Dazix. System Expert, CADAT, and Visula are trademarks of Racal-Redac. OrCAD is
trademark of OrCAD Systems Corporation. PC-UPROG is a trademark of American Advantech Corporatior
PILOT is a trademark of Advin Systems Incorporated. MDLTIPROGRAMMER is a trademark of Byte
Corporation. SmartModel is a registered trademark of Logic Automation Incorporated. IBM and AT ar
registered trademarks and IBM PC, XT, PS/2 and Micro Channel are trademarks of International Busines
MachinesCorporation.M5-DOSisa registered
trademark and Windows isa trademark of MicrosoftCorporatior
Sun, SunOS,
and SPARCstation are trademarks of Sun Microsystems, Incorporated. UNIX is a trademark c
AT&TBell Laboratories. Apollo
and Domain are registered trademarks, and Series3000,Series3500,Series400(
and Series 4500 are trademarks of Apollo Computer, Incorporated, a subsidiary of Hewlett-Packard Compan)
HP is a registered trademark of Hewlett-Packard Company. PAL and PALASM are registered trademarks e
Advanced MicroDevices, Incorporated.386 is a trademark of Intel Corporation. Synopsys and Design Compile
are trademarks of Synopsys, Inc.
Altera reserves the right to make changes, without notice, in the devices or the device specificationsidentified i
this document. Altera advises its customers to obtain the latest version of device specifications to verify, befor
placing orders, that the information being relied upon by the customer is current. Altera warrants performanc
of its semiconductor products to current specifications in accordance with Altera's standard warranty. Testin
and other quality control techniques are used to the extent Altera deems such testing necessary to support thi
warranty. Unless mandated by government requirements, specific testing of all parameters of each device is ne
necessarily
performed. In the absence of written agreement to the contrary, Altera assumes no liabilityfor Alter
applications assistance, customer's product design, or infringement of patents or copyrights of third parties b
or arising from use of semiconductor devices described herein. Nor does Altera warrant or represent any pater
right, copyright, or other intellectual property right of Altera covering or relating to any combination, machinl
or process in which such semiconductor devices might be or are used.
Altera's products are not authorized for use as critical components in life support devices or systems without th
express written approval of the president of Altera Corporation. As used herein:
1. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the bod
or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instruction
for
use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can b
reasonably expected to cause the failure of the life support device or system, or toaffectits safety or effectivenesl
Products mentioned in this document are covered by one or more of the following U.S. patents: 4,609,98/
4,617,479;4,677,318; 4,713,792; 4,774,421; 4,831,571; 4,864,161; 4,871,930; 4,899,067; 4,899,070; 4,903,223; 4,912,34;
4,930,107; 4,969,121; 5,045,772;
and certain foreign patents. Additional patents pending.
Copyright © 1991 Altera Corporation

September 1991
~/tera Corporation
About this
Data Book
This data book contains complete information about Altera's Classic,
MAX 5000, MAX 7000, STG,
and SAM EPLDs, development systems, and
developmentsoftware. Forcompleteinformation about theMicroChannel
EPLDs
and the associated development system and software, refer to
Altera's Micro Channel
Adapter Handbook.
For immediate assistance on technical questions, call:
Altera Applications Hotline
1 (800) 800-EPLD
For information on product availability, pricing, and order status, please
contact
your Altera Representative or Distributor. Phone numbers and
addresses of Altera Sales Offices, Representatives, and Distributors are
listed in this data book.
If you have questions that cannot be answered by your SalesRepresentative
or Distributor, call:
Altera Marketing S L·/j, .
[phone]
or contactAltera by:
FAX
[phone]
Page iii I

September 1991
)ection 1
)ection 2
)ection 3
)ection 4
)ection 5
)ection 6
Altera Corporation
1992 Data Book Contents
About this Data Book ......................................................................................iii
Product In.dex ..................................................................................................vii
Introduction to Altera EPLDs ................................................................. 1
Provides an introduction to Erasable Programmable Logic
Devices(EPLDs). Thissectiondescribestheprinciplesunderlying
EPLD architecture, summarizes EPLD families and software
tools offered
by Altera, and explains the advantages of CMOS
EPROMtechnology. Thissectionalsocontainsa ProductSelection
Guide for a quick overview of Altera products.
Classic EPLDs ............................................................................................. 35
Describesall Classic EPLDs, includingtheEP330, EP610, EP610A,
EP610T, EP630, EP910, EP910A,EP910T, EP1810, EP1810T,
and
EP1830 EPLDs.
MAX 5000 EPLDs ...................................................................................... 121
Describes all MAX 5000 EPLDs,
including the EPM5016,
EPM5032, EPM5064, EPM5128, EPM5130,
and EPM5192 EPLDs.
MAX 7000 EPLDs ...................................................................................... 177
Provides preliminary information about the MAX 7000 EPLDs.
STG & SAM EPLDs .................................................................................. 187
DescribestheEPS464 SynchronousTimingGenerator(STG) and
EPS448 Stand-Alone Microsequencer (SAM) EPLDs.
Micro Channel EPLDs ............................................................................ 223
Gives
an overview of the Micro Channel EPLDs, Altera's user-
configurable
adapter interface chips for the IBM PS/2 Micro
Channel. The EPB2001
and EPB2002A EPLDs are described in
detail in Altera'sMicro Channel Adapter Handbook (April1990).
Page v I

I1992Data Book Contents
Section 7
Section 8
Section 9
Section 10
Section 11
Section 12
IPage vi
MPLDs ........................................................................................................... 227
Describes all Mask-Programmed Logic Devices (MPLDs),
including the MP1810, MPM5032, MPM5064, MPM5128,
MPM5130, MPM5192,
and MPS464 MPLDs.
Operating Requirements for EPLDs ................................................ 263
Describes requirements for operatingEPLDs and how to obtain
maximum performance.
Development Products .......................................................................... 267
DescribesAltera'sdevelopmentproducts,includingdevelopment
systems
and software, software utility programs, EDIF netlist
interface,software
support for HP / Apollo and Sun workstations,
device
programming unit, adapters, and software warranty.
This section also includes a description of third-party
support.
Military Products ...................................................................................... 371
Describes the military products offered by Altera, including the
Source Control Drawings (SCDs) for military-qualified EPLDs.
Thissectionalso containsinformation about total-doseradiation
hardness of Altera EPLDs.
General Information ................................................................................ 383
Describes how to use Altera's electronic bulletin board service
and how to order Altera products. This section also shows all
EPLD package outlines, describes thermal characteristics of
EPLDs, explains how to select sockets for J-Iead packages, and
lists Altera sales offices, representatives, and distributors.
Index .............................................................................................................. 421
Altera Corporation

Product Index
I September 1991
EPLDs Classic EPLDs
EP330 EPLD ......................................................................................................39
EP610 EPLD ......................................................................................................59
EP610A EPLD...................................................................................................65
EP610T EPLD ...................................................................................................69
EP630 EPLD ......................................................................................................
73
EP910 EPLD ......................................................................................................87
EP910A EPLD ...................................................................................................
91
EP910T EPLD ...................................................................................................95
EP1810 EPLD ..................................................................................................107
EP1810T EPLD ...............................................................................................113
EP1830 EPLD ..................................................................................................117
Classic MilitaryEPLDs ...................................................................................
21
MAX 5000 EPLDs
EPM5016 EPLD ..............................................................................................137
EPM5032 EPLD ..............................................................................................143
EPM5064 EPLD .............................................................................................. 149
EPM5128 EPLD ..............................................................................................155
EPM5130 EPLD ..............................................................................................161
EPM5192 EPLD ..............................................................................................169
MAX 5000 MilitaryEPLDs .............................................................................22
MAX 7000 EPLDs
MAX 7000 EPLDs ..........................................................................................179
STG & SAM EPLDs
EPS464 EPLD ..................................................................................................191
EPS448 EPLD ..................................................................................................205
Micro Channel EPLDs
EPB2001 EPLD ...............................................................................................225
EPB2002A EPLD ............................................................................................225
I Altera Corporation Page vii I

I1992 Data Book Contents
MPLDs
Development
Tools
IPage viii
MPLDs
MP1810MPLD ...............................................................................................235
MPM5032 MPLD ...........................................................................................239
MPM5064 MPLD ...........................................................................................243
MPM5128 MPLD ...........................................................................................247
MPM5130MPLD ........................................................................................... 251
MPM5192 MPLD ...........................................................................................255
MPS464 MPLD ...............................................................................................259
PClWindows 3.0
PLDS-HPS .................................................................................................26, 269
PLS-ES .......................................................................................................26, 269
PLS-HPS ....................................................................................................26, 269
PLS-OS ... '" ............................................... '" ...............................................26, 269
PC/DOS
PLCAD-SUPREME ..................................................................................28, 299
PLDS-ENCORE ........................................................................................24, 315
PLDS-MAX ...............................................................................................27, 283
PLDS-MCMAP .........................................................................................28, 225
PLDS-SAM ................................................................................................28, 307
PLS-EDIF ...................................................................................................24, 319
PLS-MAX ..................................................................................................27, 283
PLS-MCKIT.......................................................................................................29
PLS-SAM ...................................................................................................28, 307
PLS-SUPREME .........................................................................................28, 299
Workstation
PLS-WS/HP ..............................................................................................26, 331
PLS-WS/SN..............................................................................................27, 341
Hardware
PL-ASAP ...................................................................................................32, 357
PL-MPU.............................................................................................33, 359, 389
PLP6 .................................................................................................................389
Programming Adapters ..................................................................33, 361, 390
Altera Corporation I

Contents
I September 1991
Section 1 Introduction to Altera EPLDs
Programmable Logic Overview ......................................................................3
Product Selection Guide .................................................................................17
i Altera Corporation Page
11

I September 1991, ver. 2
Introduction
Programmable Logic
Overview
Data Sheet I
ProgrammableLogic Devices(also describedasPALs,PLAs,FPLAs,PLDs,
EPLDs, EEPLDs, LCAs,
and FPGAs) combine the logistical advantages of
standard,fixed integratedcircuits with thearchitecturalflexibilityofcustom
devices. These devices allow engineers to electrically
program standard,
off-the-shelflogic elementsto meet thespecific needs oftheir applications.
Proprietary logic functions
can be designed and fabricated in-house,
eliminating the long engineering lead times,
high tooling costs, complex
procurement logistics, and dedicated inventoryproblems associated with
custom Application-Specific Integrated Circuit (ASIC) devices, such as
gate arrays and standard cells.
The key to this "off-the-shelf ASIC" capability is reprogrammable CMOS
technology, which is used tocreate Erasable Programmable Logic Devices
(EPLDs). Altera has
taken advantage of speed and density advances in
CMOS memory products to create sophisticated EPLDs that solve many
logic design problems.
Altera provides
the broadest line of CMOS EPLDs in the industry, with
products ranging in densityfrom 300 to 40,000 maximum gates, offered in
a variety of packages with 20 to 288 pins. These EPLDs, together with
Alteradevelopmentsoftware,enablesystemmanufacturers to createcustom
logic functions for a
wide variety ofapplications. See Figure 1.
Figure 1. Altera EPLD Families
General-Purpose EPLDs:
Function-Specific EPLDs:
Optimized for distinct applications
Classic: MAX 5000: MAX 7000: STG: SAM: Micro Channel:
EP330 EPM5016 EPM7032 EPS464 EPS448 EPB2001
EP610 EPM5032 EPM7064 EPB2002A
EP610A EPM5064 EPM7096 (Synchronous (Stand-Alone
EP610T EPM5128 EPM7128 Timing Generator) Microsequencer)
EP630 EPM5130 EPM7160
EP910 EPM5192 EPM7192
EP910A EPM7256 MPLDs:
EP910T EPM7320 Optimized for high-volume applications
EP1810 EPM7384
EP1810T EPM7512
EP1830 EPM7768
EPM71 024
Optimized for Optimized for high-performance,
high-performance, pin-intensive, register-intensive
"zero-power" applications
EJ
Classic: MAX 5000:
MP1810 MPM5032
MPM5064
MPM5128
MPM5130
MPM5192
applications
Altera Corporation Page 3 I

IProgrammable Logic Overview Data Sheet I
EPLD
Families
IPage 4
EPLDs can be used to integrate complete printed circuit boards of TTL,
PAL, and FPGA devices intoa single package. EPLDs are also valuable for
prototyping high-density custom devices, whichenables designers to test
markets and evaluatesystemsbeforecommittingto expensiveengineering
developmentcycles and tooling charges. For most of today's applications,
EPLDs not only ensure faster time-to-market, but also provide a lower
total cost than custom ASIC solutions.
AItera concentrates on creating high-performance device architectures
and easy-to-use, highly productive CAE software. AItera products meet
the demands of designers who require complete solutions to logic
integration that include both PAL speed and FPGA density. See Figure 2.
Figure 2. PLD Speed vs. Density
100
N
I
:2
~
z
~
"'0
Q)
50
Q)
0..
en
Q)
::c
as
en
:::>
100 10,000
Usable Density
20,000
AItera offers several families of EPLDs that satisfy many common board-
and system-integration needs. EPLD families are divided into two
architecturalcategories: thefirstprovides maximum flexibilityfor general-
purpose logicreplacement;thesecondis specializedfor performingspecific
system design tasks.
o General-purpose EPLDs are available in a variety of integration
densities, ranging from PAL replacements to high-density devices
that integratethousands of TTL and random logic gates. TheseEPLDs
are the Classic, MAX 5000, and MAX 7000 EPLD families.
TheClassic architectureincludes20- to 68-pinEPLDs that feature
zero-standby power, propagation delays (t
pD
) as low as 12 ns,
and counter frequencies up to 100 MHz.
Altera Corporation I

Data Sheet
Software
Tools
~igure 3. EPLD DeSign
lIethodology: from
';oncept to Silicon in
'-lours
Altera Corporation
Programmable Logic Overview I
The Multiple Array Matrix (MAX) 5000 architecture includes 20-
to 100-pin EPLDs that combine the high speed and ease-of-use of
PAL devices with the density of FPGA devices. High-density
MAX 5000 EPLDs
can consolidate 20 to 25 PAL packages and
over 100 TTL functions while offering system clock rates up to 50
MHz.
The MAX 7000 family represents the second generation of
the
MAX architecture. TheseEPLDsrangefrom 44 to 288 pins,provide
integration densities of1,200 to 40,000 maximum gates,
and offer
system clock rates
up to 70 MHz.
o Function-specific EPLDs provide optimized integration for specific
system design tasks. They are classified
by their system design focus.
The
EPB2001 and EPB2002A Micro Channel EPLDs are bus-
oriented devices designed to integrate all required add-on card
logic for a Micro Channel bus interface.
The EPS464 Synchronous Timing Generator (SIG)
and EPS448
Stand-Alone Microsequencer (SAM) EPLDs offer the logic
and
speed required for complex control logic, state machines, and
imaging and display applications.
o Mask-ProgrammedLogic Devices(MPLDs) providea low-costmasked
alternative to EPLDs for customers
with high-volume production.
A varietyofpackageoptionsis offered, including
dual in-line (DIP), J-lead
chip carrier aLCC), small-outline integratedcircuit (SOIC),
quad flat pack
(QFP), and pin-grid array (PGA) packages. EPLDs are available in
windowed (erasable) ceramic packages or one-time-programmable (OTP)
plastic versions. In addition, Mask-Programmed Logic Devices (MPLDs)
are available for high-volume applications.
Altera software products are developed together with the EPLD
architectures, so features are placed where they are most appropriate-in
eithersoftware or hardware. The resultis efficientsoftware tools that offer
familiar design
entry methods and rapid designcompletion. See Figure 3.
With Altera's CAE development tools, users can take a logic circuit from
less than
1 hour
5 seconds
to
30 minutes
2 hours less than
2 minutes
PageS/

IProgrammable Logic Overview Data Sheet I
designentrytodeviceprogramming in a matterofhours.Designprocessing
is typically completed in minutes, allowingseveral design iterations to be
completed in a single day.
Altera software is available for IBM PC-AT, PS/2, and compatible
computers, and workstations (HP/ Apollo and Sun). Several design entry
options are available: hierarchical schematic capture (with basic gate and
complete TTL macrofunction libraries), the Altera Hardware Description
Language(AHDL), Booleanequation,statemachine, truth table,waveforms,
netlist, and microcoded assembly language. See Figure 4. Design entry
methods can be freely combined to create a single EPLD design. Design
compilers perform minimization and logic synthesis, design fitting
(analogous to automatic place-and-route), and generate programming
data. Designverificationviafunctional simulation, timingsimulation, and
delay prediction for speed-critical paths is also available. Hardware for
programming EPLDs is offered by Altera and a variety of third-party
vendors.
Figure 4. Altera Design Environment
IPage 6
EDIF EDIF
Softwareinterfaces to otherdesign tools are provided by Altera and third-
party translators, and via industry-standard EDIF netlists. Many third-
party compilers also support Altera EPLDs directly.
Affera Corporation I

Data Sheet
EPLD
~rch itecture
3asic
:oncepts
':;gure 5. AND-Array Notation
:ircuit A: Typical Circuit
Programmable Logic Overview 1
The Altera approach to logic design eliminates the necessity of mastering
the inner complexities of EPLD architectures. The
user can work with
familiar design entry tools (e.g., TTL macrofunctions or a high-level state
machine language),
and the Altera software automatically translates the
design into the format required to fit the EPLD architecture. For detailed
architecture
and pin-out descriptions of each device, refer to individual
EPLD data sheets in this data book.
Altera general-purpose EPLDs provide dedicated input pins, user-
configurable I/O pins, and programmableflip-flop and clock options that
ensure maximum flexibility for integrating random logic functions.
Each EPLD also contains
an AND array that provides product terms. A
product term is simply an n-input AND gate, where n is the number of
connections. EPLD schematics use a
shorthand AND-array notation to
represent several large
AND gates with common inputs. Figure 5 shows
three different representations of the same logic function. Circuit A is
presented
in classiclogicnotation; CircuitB has been modifiedto a sum-of-
products notation; and Circuit C is written in AND-array notation. A dot
represents a connection between an input (vertical wire) and one of the
8-input AND gates. No dot implies no connection: the AND-gate input is
unused and floats to a logic 1.
Circuit B: Circuit A drawn with complementary
output buffers
11~:~~~
::~ 11'12'/13+11 *14
:! C)-
11 * 12 * 113 + 11 * 14
11 12 13 14
;ircuit C: Circuit B with 8-input AND gates in AND-array notation
11 * 12 * 113 + 11 * 14
11 12 13 14
A/tera Corporation Page
71

IProgrammable Logic Overview Data
Sheet I
Macrocell
Architecture
Figure 6. The Macrocell
I
e>--:
I
C>-:
I
I
c>-:
I
c:::>----:
I
I
LogicArray
The 2 x 8 AND-array ofCircuit C can produce any Boolean function offour
variables (providedonly
two product terms are required) when expressed
in sum-of-products form. Any Boolean expression-no matter how
complex--can be written in sum-of-productsform. Outputs ofthe two AND
gates in Figure 5 are called product terms (or p-terms).
The fundamental
building block of an Altera EPLD is the macrocell. Each
macrocell consists of three
parts (see Figure 6):
o The logic array implements all combinatorial logic functions.
o The programmable register provides D, T, JK, or SR options. The
register
can also be bypassed.
o Programmable II 0 allowseach II 0 pin to be configuredasa dedicated
output, input, or bidirectional pin.
I
Register Options
r··DF::·~·······
D Q
CLRN
----- .. ---------------
.:
:; K
I: CLRN
,:
,:
TFF
PRN
T Q
CLRN
PRN
S Q
R
CLRN
1/0 Control
: : OUTPUT
f~·····----·········l
L .................. J
:-------------------------------------~
I !..--------------------- ----------------- .. --
1 ______ -------------------
Logic Array
I Page8
The logic array consists of a programmable-AND/fixed-oR array. Inputs to
the AND array come from the true and complement of the dedicated input
and clock pins, and from the macrocell and 110 feedback paths.
Foreachmacrocell,
the logic array typicallycontains 10 product terms that
are distributed among the combinatorial and sequential resources. See
Figure
7. Connections are opened during the programming process.
Therefore,
any product term may be connectedtothe true and complement
of
any array input signal. When both the true and complement of any
signal are left intact, a logical false results on the output of the product
term. If both the true and complement connection are open, a logical
"don't care" results for that input. If all inputs for the product term are
programmed opened, a logical true results on the output of the product
term.
Altera Corporation I

Data Sheet Programmable Logic Overview I
:igure 7. Detailed EPLD Macrocell Architecture
from
Inputs from 1/0
from
Macrocells
Inputs
EPROM
Bit
)rogrammable
=lip-Flops
Altera Corporation
I
LogicArray
1/0 Output Enable
Preset
Array Clock
Clear
p
Global Clock
Programmable
Flip-Flop
(D, T, JK, SR)
Several product termsfeed a fixed OR whose output connects to an exclusive-
OR (XOR) gate. The second input to the XOR function is controlled by a
programmable resource (usually a
product term) that allows the logic
array output to be inverted. Altera software uses this gate to implement
active-high or active-lowlogic,complex mutually exclusive and arithmetic
functions,
or to reduce the number of product terms to implement a
function (by
applying De Morgan's inversion). Figure 8 shows an OR
function that requires six product terms in its current form. By using the
"programmable" XOR gate and De Morgan'sinversion, the OR function can
be transformed into a NAND function:
A+B+C+D+E+F = /(/A*/B*/C*/D*/E*/F)
This inversion from OR to AND translates the equation and reduces the
number of fixed OR terms required in the logic array. Altera software
automatically applies De
Morgan's inversion and other logic synthesis
techniques to optimize the
use of the logic array.
Programmableflip-flops are
used to createa varietyoflogic functions that
use a minimum of EPLD resources. Each flip-flop can be programmed to
provide a conventionalD, T, JK, or SR function. MAX 5000 EPLD flip-flops
can also be configured as flow-through latches. If the flip-flop is not
required for macrocelliogic, it may be simply bypassed. Macrocell flip-
flops also
have an asynchronous Clear and Preset capability that allows
complete emulation of
any TTL macrofunction.
Page 9 I

IProgrammable Logic Overview Data
Sheet I
Figure 8. Logic Minimization with De Morgan's Inversion
Programmable
Clock
1/0 Control
Block
IPage 10
De Morgan's
Inversion
A
B
C
D
E
F
A
B
C
~ D
E
F
lEPLD
Implementation Logic 1
In general-purpose EPLDs (except the EP330), each internal flip-flop can
be clocked from a dedicated global clock (also known as a synchronous
clock),
any input or 1/0 pin, or any internal logic function. For each flip-
flop, a multiplexerselectseithera
pin or product-term sourcefor the clock,
so
that flip-flops can be clocked independently or in user-defined groups.
EPLD registersarepositive-edge-triggered with data transitions that occur
on the rising edge of the dedicated global clock.
When the clockis driven by a product term,flip-flops can be configuredfor
eitherpositive-
or negative-edge-triggeredoperation. In addition,product-
term clocks allow gated-clock and clock-enable logic to be implemented.
However,globalclocksignals
have faster clock-to-output delay times than
internally generated product-term clock signals.
The EPLD
110 block contains a tri-state buffer controlled by a macrocell
product term, and drives the I/O pin (see Figure 9). 110 pins can be
configured
as dedicated outputs, bidirectional outputs, or as additional
dedicatedinputs.Most
EPLDs have" dual feedback," whereby the macrocell
feedback is decoupled from
the 1/0 pin feedback. Dual feedback makes it
possibleto implement a buried function in the macrocellwhile the I/O pin
is used simultaneously as a dedicated input. Applications that require
bus-oriented functions
or many buried flip-flops such as counters, shift
registers, and state machines are easily accommodated by this
programmable 110 block.
Altera Corporation