AMD AMD5K86 Use and care manual

. AMD5
K86™ Processor
Technical Reference Manual
AMD ~

Technical Reference Manual
AMD~

Trademarks:
@ 1996 Advanced Micro Devices, Inc. All rights reserved.
Advanced Micro Devices reserves the right to make changes in its products
without notice in order to improve design or performance characteristics.
This publication neither states nor implies any representations or warranties
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AMD disclaims
responsibility for any consequences resulting from the use of
the information included herein.
AMD, the Arrow Logo and combinations thereof are trademarks of Advanced Micro Devices,Inc. and are protected
in many countries throughout the world. Am386 and Am486 are registered trademarks, and AMD5K86 and K86 are
trademarks of Advanced Micro Devices, Inc.
Microsoft
and Windows are registered trademarks and Windows NT is a trademark of Microsoft.
Other product names used in this publication are for identification purposes only and may be trademarks of their
respective companies.

AMD~
185248/0- Mar1996
AMD5J<fJ6 Processor Technical Reference Manual
Contents
1 Overview 1-1
1.1 Features ............................................ 1-2
2 Internal Architedure 2-1
2.1 Prefetch and Predecode ............................... 2-3
2.2 Execution Pipeline .................................... 2-4
2.2.1 Fetch .............................................. 2-6
2.2.2 Decode ............................................ 2-7
2.2.3
Execute............................................ 2-8
Integer/Shift Units .................................. 2-9
Floating-Point Unit ................................. 2-10
Load/Store Units ................................... 2-10
Branch Unit ....................................... 2-10
2.2.4 Result ............................................ 2-11
2.2.5
Retire ............................................ 2-12
2.3 Cache Organization and Management ................... 2-13
2.3.1 Instruction Cache .................................. 2-14
2.3.2
Data Cache ........................................ 2-15
2.3.3
Cache Tags ........................................ 2-16
2.3.4 Cache-Line Fills
.................................... 2-17
2.3.5
Cache Coherency ................................... 2-18
2.3.6
Snooping .......................................... 2-21
Inquire Cycles ..................................... 2-21
Internal Snooping .................................. 2-22
2.3.7
Buffers ........................................... 2-23
Line-Fill Buffers
................................... 2-23
Prefetch Cache .................................... 2-24
Store Buffer ....................................... 2-24
Replacement and Invalidation Writeback Buffer ........ 2-25
Snoop Write back Buffer . . . . . . . .. . . . . . . . . . . . . . . . . . . . . 2-26
2.4 Memory Management Unit (MMU) ..................... 2-26
2.4.1 Storage Model ..................................... 2-26
2.4.2
ReadlWrite Reordering ............................. 2-27
2.4.3
Segmentation ...................................... 2-27
2.4.4
Paging and the TLBs ................................ 2-28
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3 Software Environment and Extensions 3-1
3.1 Control Register 4 (CR4) Extensions ..................... 3-2
3.1.1 Machine-Check Exceptions ................ ; .......... 3-4
3.1.2 4-Mbyte
Pages ...................................... 3-5
3.1.3 Global
Pages .......•................................ 3-9
3.1.4 Virwal-8086
Mode Extensions (VME) ................. 3-12
Interrupt Redirection in Virtual-8086 Mode Without
VME Extensions ................................... 3-12
Hardware Interrupts and the VIF and VIP Extensions .... 3-13
Software Interrupts and the Interrupt Redirection
Bitmap (IRB) Extension ............................. 3-21
3.1.5
Protected Virtual Interrupt (PVI) Extensions ........... 3-24
3.2 Model-Specific Registers (MSRs) ....................... 3-25
3.2.1 Machine-Check Address Register (MCAR) ............. 3-25
3.2.2
Machine-Check Type Register (MCTR) ................ 3-26
3.2.3
Time Stamp Counter (TSC) .......................... 3-27
3.2.4
Array Access Register (AAR) ........................ 3-27
3.2.5
Hardware Configuration Register (HWCR) . . . . . . . . . . . . . 3-28
3.3 New Instructions .................................... 3-28
3.3.1 CPUID ............................................ 3-29
3.3.2 CMPXCHG8B
...................................... 3-32
3.3.3 MOV
to and from CR4 .............................. 3-33
3.3.4 RDTSC
............................................ 3-34
3.3.5 RDMSR
and WRMSR ............................... 3-35
3.3.6 RSM
............................................. 3-37
3.3.7
lllegal Instruction (Reserved Opcode) ................. 3-38
4 Performance 4-1
4.1 Code Optimization .................................... 4-1
4.1.1 General Superscalar Techniques ....................... 4-1
4.1.2 Techniques Specific to the AMD5K86 Processor .......... 4-3
4.2 Dispatch and Execution Timing ......................... 4-5
4.2.1 Notation ........................................... 4-5
4.2.2 Integer Instructions .................................. 4-8
4.2.3 Integer Dot Product Example .. ; ..................... 4-17
4.2.4
Floating-Point Instructions ........................... 4-19
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185248jO-Mar1996 AMD5K,iJ6 Processor Technical Reference Manual
5 Bus Interlac:e 5-1
5.1 Signal Overview ...................................... 5-2
5.1.1 Signal Characteristics ................................ 5-4
5.1.2 Conditions for Driving
and Sampling Signals ............ 5-8
5.1.3 External Interrupts ................................. 5-14
5.1.4 Bus
Signal Compatibility with Pentium Processor ....... 5-18
5.2 Signal Descriptions .................................. 5-18
5.2.1 :A'ZOll (Address Bit 20 Mask) ......................... 5-19
5.2.2 A31-A3
(Address Bus) .............................. 5-21
5.2.3 ADS
(Address Strobe) ............................... 5-25
5.2.4
AD'SC (Address Strobe Copy) ........................ 5-28
5.2.5 AHOLD
(Address Hold) ............................. 5-29
5.2.6
AP (Address Parity) ................................ 5-32
5.2.7
APCRK (Address Parity Check) ...................... 5-33
5.2.8 BE7-BEiJ (Byte
Enables) ............................. 5-34
5.2.9 BF (Bus
Frequency) ................................. 5-37
5.2.10 BUFF (Backoff) .................................... 5-38
5.2.11 BRDY (Burst
Ready) ................................ 5-42
5.2.12 RDYC (Burst
Ready) ................................ 5-45
5.2.13 BREQ (Bus
Request) ................................ 5-46
5.2.14 BUSCHK (Bus Check)
............................... 5-47
5.2.15 CACHE
(Cacheable Access) .......................... 5-50
5.2.16 CLK (Bus Clock) ................................... 5-53
5.2.17 D/C
(Data or Code) ................................. 5-54
5.2.18 D63-DO
(Data Bus) ................................. 5-56
5.2.19 DP7-DPO
(Data Parity) ............................... 5-58
5.2.20 EADS (External Address Strobe) ..................... 5-59
5.2.21
EWBE (External Write Buffer Empty) ................. 5-63
5.2.22
FERR (Floating-Point Error) ......................... 5-65
5.2.23
FLOSH (Cache Flush) ............................... 5-67
5.2.24 FRCMC
(Functional-Redundancy Check Master/Checker) 5-70
5.2.25 HIT (Inquire-Cycle Hit) ............................. 5-72
5.2.26
HITM (Inquire Cycle Hit To Modified Line) ............ 5-74
5.2.27 HLDA (Bus-Hold Acknowledge)
...................... 5-76
5.2.28 HOLD (Bus-Hold
Request) ........................... 5-78
5.2.29 !ERR
(Internal Error) ............................... 5-80
5.2.30 IGNNE
(Ignore Numeric Error) ....................... 5-81
5.2.31 INIT (Initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-82
5.2.32
INTR (Maskable Interrupt) .......................... 5-85
5.2.33 INV
(Invalidate Cache Line) ......................... 5-89
5.2.34
KEN (External Cache Enable) ........................ 5-90
5.2.35 LUCK (Bus Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-92
5.2.36 MIID (Memory
or 110) ............................... 5-96
5.2.37 NA
(Next Address) ................................. 5-97
5.2.38 NMI (Non-Maskable
Interrupt) ....................... 5-98
5.2.39 PCD
(Page Cache Disable) .......................... 5-100
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5.2.40 PCHK (Parity Status) .............................. 5-102
5.2.41 PEN (Parity Enable) ............................... 5-103
5.2.42 PRDY (Probe Ready) .............................. 5-104
5.2.43 PWT (Page Writethrough) .......................... 5-106
5.2.44 R/S (Run or Stop) ................................. 5-108
5.2.45 RESET (Reset) .................................... 5-110
5.2.46 SCYC (Split Cycle) ..... ' ........................... 5-115
5.2.47 sm(System
Management Interrupt) ................. 5-117
5.2.48 SMIACT (System Management Interrupt Active) ....... 5-122
5.2.49 STPCLK (Stop Clock) .............................. 5-123
5.2.50 TCK (Test Clock) .................................. 5-128
5.2.51 TDI (Test Data Input) .............................. 5-129
5.2.52 TDO (Test
Data Output) ............................ 5-130
5.2.53 TMS (Test Mode Select) ............................ 5-131
5.2.54 TRST (Test Reset) ................................. 5-132
5.2.55 WfR (Write or Read) ............................... 5-133
5.2.56 WBIWT
(Writeback or Writethrough) ................. 5-134
5.3 Bus Cycle Overview ................................. 5·137
5.3.1 Cycle Definitions .................................. 5-137
5.3.2 Addressing ............. ; ......................... 5-138
5.3.3 Alignment ........................................ 5-139
5.3.4 Bus Speed and Typical DRAM Timing ................ 5-140
5.3.5 Bus-Cy<;le Priorities ................................ 5-140
5.4 Bus Cycle Timing ................................... 5·141
5.4.1 Timing Diagrams .................................. 5-141
5.4.2 Single-Transfer Reads and Writes .................... 5-142
Single-Transfer Memory Read and Write .............. 5-142
Single-Transfer
Memory Write Delayed by EWBE Signal 5-145
I/O Read and Write ................................ 5-147
Single-Transfer Misaligned Memory and I/O Transfers .. 5-148
5.4.3
Burst Cycles ...................................... 5-150
Burst Read ............................. " ........ 5-150
Burst Writeback ................................... 5-154
5.4.4 Bus Arbitration and Inquire Cycles ................... 5-157
AHOLD-Initiated
Inquire Miss ...................... 5-158
AHOLD-Initiated
Inquire Hit to Shared or Exclusive Line 5-160
AHOLD-Initiated Inquire Hit to Modified Line ......... 5-161
Bus Backoff (BUFF) ................................ 5-163
BUFF-Initiated Inquire Hit to Modified Line ........... 5-165
HOLD-Initiated Inquire Hit to Shared or Exclusive Line . 5-167
HOLD-Initiated Inquire Hit to Modified Line .......... 5-169
5.4.5 Locked Cycles .................................... 5-170
Basic Locked Operation ............................ 5-170
TLB Miss (4-Kbyte Page) ........................... 5-172
Locked Operation with BUFF Intervention ............ 5-174
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18524BjO- Mar1996 AMD5 J<!36 Processor Technical Reference Manual
Interrupt Acknowledge Operation ................... 5-176
5.4.6
Special Bus Cycles ................................. 5-181
Basic
Special Bus Cycle ............................ 5-182
Shutdown Cycle ................................... 5-183
FLOSH-Acknowledge Cycle
......................... 5-184
Cache-Invalidation Cycle (INVD Instruction) .......... 5-185
Cache-Writeback and Invalidation Cycle
(WBINVD
Instruction) ............................. 5-186
Branch-Trace
Message Cycles ....................... 5-188
5.4.7
Mode Transitions, Reset, and Testing ................. 5-190
Transition from Normal Execution to SMM ............ 5-190
Stop-Grant and Stop-Clock States .................... 5-193
INIT-Initiated Transition from Protected Mode to
Real Mode ....................................... 5-196
6 System Design 6·1
6.1 Memory ............................................. 6-1
6.1.1 Memory Map ....................................... 6-2
6.1.2
Memory-Decoder Aliasing of Boot ROM Space ........... 6-4
6.1.3
Cacheable and Noncacheable Address Spaces ........... 6-4
6.1.4 SMM
Memory Space and Cache ability .................. 6-5
6.2 Cache ............................................... 6-8
6.2.1 L2 Cache ........................................... 6-9
6.2.2
Cache ability and Cache-State Control .................. 6-9
6.2.3
Write through vs. Writeback Coherency States .......... 6-10
6.2.4 Inquire Cycles ..................................... 6-12
6.2.5 Bus
Arbitration for Inquire Cycles .................... 6-14
BUFF Arbitration .................................. 6-15
AHOLD Arbitration ................................ 6-17
HOLD Arbitration .................................. 6-19
6.2.6 Write-Once
Protocol ................................ 6-19
6.2.7
Cache Invalidations ................................. 6-22
6.2.8
AZOJ.IJ Masking of Cache Accesses . . . . . . . . . . . . . . . . . . . . . 6-22
6.3 System Management Mode (SMM) ..................... 6-23
6.3.1 Operating Mode and Default Register Values ........... 6-24
6.3.2 SMM
State-Save Area ............................... 6-25
6.3.3 SMM
Revision Identifier ............................ 6-28
6.3.4 SMM Base
Address ................................. 6-28
6.3.5
Halt Restart Slot ................................... 6-30
6.3.6 JJO Trap Dword .................................... 6-31
6.3.7
JJO Trap Restart Slot ................................ 6-31
6.3.8
Exceptions and Interrupts in SMM . . . . . . . . . . . . . . . . . . . . 6-32
6.3.9 SMM
Compatibility with Pentium Processor . . . . . . . . . . . . 6-33
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6.4 Clock Control ....................................... 6-33
6.4.1 State Transitions ................................... 6-34
6.4.2
Halt State ........... _. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34
6.4.3
Stop Grant State ................................... 6-37
6.4.4
Stop Grant Inquire State ............................ 6-37
6.4.5
Stop Clock State ................................... 6-38
6.4.6 Clock
Control Compatibility with Pentium Processor .... 6-38
6.5 Power and Ground Design ............................. 6-38
6.6 Clock
Design ........................................ 6·40
6.6.1 Noise Reduction ................................... 6-43
6.7 Thermal Design ..................................... 6-44
6.8
Design Support and Peripheral Products ................ 6·45
7 Test and Debug
7-1
7.1 Hardware Configuration Register (HWCR) ............... 7·3
7.2 Built·In Self Test (BIST) ............................... 7-5
7.2.1 Normal BIST ........................................ 7-5
7.2.2 Test Access Port (TAP) BIST .......................... 7-6
7.3 Output.Float Test ..................................... 7·7
7.4 Cache and TLB Testing ................................ 7·7
7.4.1 Array Access Register (AAR) ......................... 7-8
7.4.2 Array Pointer ....................................... 7-9
7.4.3 Array Test Data .................................... 7-10
7.5 Debug Registers ..................................... 7-16
7.5.1 Standard Debug Functions ........................... 7-16
7.5.2 IJO Breakpoint Extension ............................ 7-16
7.5.3
Debug Compatibility with Pentium Processor ........... 7-17
7.6 Branch Tracing ...................................... 7·17
7.7 Functional·Redundancy Checking ...................... 7·18
7.8 Boundary·Scan Test Access Port (TAP) .................. 7-19
7.8.1 Device Identification Register ........................ 7-21
7.8.2
Public Instructions ................................. 7-22
7.9 Hardware Debug Tool (HDT) .......................... 7·23
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AMD51(fJ6 Processor Technical Reference Manual
Appendix A Compatibility With the Pentium and 486 Processors
A-I
A.1 Bus Signals ......................................... A-2
A.lol Signal Comparison .................................. A-2
A.2 Bus Interface ....................................... A-5
A.2.l Updates to Descriptor Accessed and TSS Busy Bits ....... A-S
A.2.2 Locked and Unlocked CMPXCHG8B Operation .......... A-S
A.2.3 Bus Cycle Order of Misaligned Memory and 110 Cycles .... A-6
A.2A Halt Cycle after FLUSH .............................. A-6
A.2.S
Selectable Drive Strengths on Output Driver ............ A-6
Comments .......................................... A-7
A.3 Bus Mastering Operations (including Snooping) .......... A-8
A.3.l AHOLD Snoop to Linefill Buffer Prior to or Coincident
with the Establishment of the Cacheability of the Line .... A-8
Comments .......................................... A-8
A.3.2 :mJFF
Asserted before Snoop to Linefill Buffer and
after the Cacheability of the Line is Established .......... A-8
Comments .......................................... A-9
A.3.3 Snoop
Before Write Hit to ICACHE Appears on Bus ...... A-9
A.3A Invalidations during a FLUSHIWBINVD ................ A-9
A.3.5
Cache Line Ownership ............................... A-9
A.3.6
Write Hit to a Shared Line in the DCACHE ............. A-l0
A.4 Memory Management ............................... A-ll
AA.l Speculative TLB Refills ............................. A-ll
AA.2 Page Fault Encountered by a Load/Store Type
of Instruction ...................................... A-ll
A.5 Power Saving Features .............................. A-12
A.S.l STPCLK in Halt State ............................... A-12
A.S.2 STPCLK
Pulse does not Guarantee That One
Instruction Executes ................................ A-12
A.S.3
Simultaneous 110 SM! Trap and Debug Breakpoint Trap .. A-12
A.SA
Sl\1lV[ Save Area .................................... A-12
A.S.S NM!
Recognition during Sl\1lV[ ........................ A-13
Comment ................................... : ..... A-13
A.6 Exceptions ......................................... A-14
A.6.l Limit Faults on an Invalid Instruction ................. A-14
A.6.2
Task Switch ....................................... A-14
A.7 Debug ............................................ A-15
A.7.l Proprietary Branch Trace Messages ................... A-1S
A.7.2
Multiple Debug Breakpoint Matches .................. A-1S
A.7.3
Simultaneous Debug Trap and Debug Fault ............ A-1S
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