AMD AMD5K86 Use and care manual

. AMD5
K86™ Processor
Technical Reference Manual
AMD ~

Technical Reference Manual
AMD~

Trademarks:
@ 1996 Advanced Micro Devices, Inc. All rights reserved.
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without notice in order to improve design or performance characteristics.
This publication neither states nor implies any representations or warranties
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AMD disclaims
responsibility for any consequences resulting from the use of
the information included herein.
AMD, the Arrow Logo and combinations thereof are trademarks of Advanced Micro Devices,Inc. and are protected
in many countries throughout the world. Am386 and Am486 are registered trademarks, and AMD5K86 and K86 are
trademarks of Advanced Micro Devices, Inc.
Microsoft
and Windows are registered trademarks and Windows NT is a trademark of Microsoft.
Other product names used in this publication are for identification purposes only and may be trademarks of their
respective companies.

AMD~
185248/0- Mar1996
AMD5J<fJ6 Processor Technical Reference Manual
Contents
1 Overview 1-1
1.1 Features ............................................ 1-2
2 Internal Architedure 2-1
2.1 Prefetch and Predecode ............................... 2-3
2.2 Execution Pipeline .................................... 2-4
2.2.1 Fetch .............................................. 2-6
2.2.2 Decode ............................................ 2-7
2.2.3
Execute............................................ 2-8
Integer/Shift Units .................................. 2-9
Floating-Point Unit ................................. 2-10
Load/Store Units ................................... 2-10
Branch Unit ....................................... 2-10
2.2.4 Result ............................................ 2-11
2.2.5
Retire ............................................ 2-12
2.3 Cache Organization and Management ................... 2-13
2.3.1 Instruction Cache .................................. 2-14
2.3.2
Data Cache ........................................ 2-15
2.3.3
Cache Tags ........................................ 2-16
2.3.4 Cache-Line Fills
.................................... 2-17
2.3.5
Cache Coherency ................................... 2-18
2.3.6
Snooping .......................................... 2-21
Inquire Cycles ..................................... 2-21
Internal Snooping .................................. 2-22
2.3.7
Buffers ........................................... 2-23
Line-Fill Buffers
................................... 2-23
Prefetch Cache .................................... 2-24
Store Buffer ....................................... 2-24
Replacement and Invalidation Writeback Buffer ........ 2-25
Snoop Write back Buffer . . . . . . . .. . . . . . . . . . . . . . . . . . . . . 2-26
2.4 Memory Management Unit (MMU) ..................... 2-26
2.4.1 Storage Model ..................................... 2-26
2.4.2
ReadlWrite Reordering ............................. 2-27
2.4.3
Segmentation ...................................... 2-27
2.4.4
Paging and the TLBs ................................ 2-28
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3 Software Environment and Extensions 3-1
3.1 Control Register 4 (CR4) Extensions ..................... 3-2
3.1.1 Machine-Check Exceptions ................ ; .......... 3-4
3.1.2 4-Mbyte
Pages ...................................... 3-5
3.1.3 Global
Pages .......•................................ 3-9
3.1.4 Virwal-8086
Mode Extensions (VME) ................. 3-12
Interrupt Redirection in Virtual-8086 Mode Without
VME Extensions ................................... 3-12
Hardware Interrupts and the VIF and VIP Extensions .... 3-13
Software Interrupts and the Interrupt Redirection
Bitmap (IRB) Extension ............................. 3-21
3.1.5
Protected Virtual Interrupt (PVI) Extensions ........... 3-24
3.2 Model-Specific Registers (MSRs) ....................... 3-25
3.2.1 Machine-Check Address Register (MCAR) ............. 3-25
3.2.2
Machine-Check Type Register (MCTR) ................ 3-26
3.2.3
Time Stamp Counter (TSC) .......................... 3-27
3.2.4
Array Access Register (AAR) ........................ 3-27
3.2.5
Hardware Configuration Register (HWCR) . . . . . . . . . . . . . 3-28
3.3 New Instructions .................................... 3-28
3.3.1 CPUID ............................................ 3-29
3.3.2 CMPXCHG8B
...................................... 3-32
3.3.3 MOV
to and from CR4 .............................. 3-33
3.3.4 RDTSC
............................................ 3-34
3.3.5 RDMSR
and WRMSR ............................... 3-35
3.3.6 RSM
............................................. 3-37
3.3.7
lllegal Instruction (Reserved Opcode) ................. 3-38
4 Performance 4-1
4.1 Code Optimization .................................... 4-1
4.1.1 General Superscalar Techniques ....................... 4-1
4.1.2 Techniques Specific to the AMD5K86 Processor .......... 4-3
4.2 Dispatch and Execution Timing ......................... 4-5
4.2.1 Notation ........................................... 4-5
4.2.2 Integer Instructions .................................. 4-8
4.2.3 Integer Dot Product Example .. ; ..................... 4-17
4.2.4
Floating-Point Instructions ........................... 4-19
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185248jO-Mar1996 AMD5K,iJ6 Processor Technical Reference Manual
5 Bus Interlac:e 5-1
5.1 Signal Overview ...................................... 5-2
5.1.1 Signal Characteristics ................................ 5-4
5.1.2 Conditions for Driving
and Sampling Signals ............ 5-8
5.1.3 External Interrupts ................................. 5-14
5.1.4 Bus
Signal Compatibility with Pentium Processor ....... 5-18
5.2 Signal Descriptions .................................. 5-18
5.2.1 :A'ZOll (Address Bit 20 Mask) ......................... 5-19
5.2.2 A31-A3
(Address Bus) .............................. 5-21
5.2.3 ADS
(Address Strobe) ............................... 5-25
5.2.4
AD'SC (Address Strobe Copy) ........................ 5-28
5.2.5 AHOLD
(Address Hold) ............................. 5-29
5.2.6
AP (Address Parity) ................................ 5-32
5.2.7
APCRK (Address Parity Check) ...................... 5-33
5.2.8 BE7-BEiJ (Byte
Enables) ............................. 5-34
5.2.9 BF (Bus
Frequency) ................................. 5-37
5.2.10 BUFF (Backoff) .................................... 5-38
5.2.11 BRDY (Burst
Ready) ................................ 5-42
5.2.12 RDYC (Burst
Ready) ................................ 5-45
5.2.13 BREQ (Bus
Request) ................................ 5-46
5.2.14 BUSCHK (Bus Check)
............................... 5-47
5.2.15 CACHE
(Cacheable Access) .......................... 5-50
5.2.16 CLK (Bus Clock) ................................... 5-53
5.2.17 D/C
(Data or Code) ................................. 5-54
5.2.18 D63-DO
(Data Bus) ................................. 5-56
5.2.19 DP7-DPO
(Data Parity) ............................... 5-58
5.2.20 EADS (External Address Strobe) ..................... 5-59
5.2.21
EWBE (External Write Buffer Empty) ................. 5-63
5.2.22
FERR (Floating-Point Error) ......................... 5-65
5.2.23
FLOSH (Cache Flush) ............................... 5-67
5.2.24 FRCMC
(Functional-Redundancy Check Master/Checker) 5-70
5.2.25 HIT (Inquire-Cycle Hit) ............................. 5-72
5.2.26
HITM (Inquire Cycle Hit To Modified Line) ............ 5-74
5.2.27 HLDA (Bus-Hold Acknowledge)
...................... 5-76
5.2.28 HOLD (Bus-Hold
Request) ........................... 5-78
5.2.29 !ERR
(Internal Error) ............................... 5-80
5.2.30 IGNNE
(Ignore Numeric Error) ....................... 5-81
5.2.31 INIT (Initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-82
5.2.32
INTR (Maskable Interrupt) .......................... 5-85
5.2.33 INV
(Invalidate Cache Line) ......................... 5-89
5.2.34
KEN (External Cache Enable) ........................ 5-90
5.2.35 LUCK (Bus Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-92
5.2.36 MIID (Memory
or 110) ............................... 5-96
5.2.37 NA
(Next Address) ................................. 5-97
5.2.38 NMI (Non-Maskable
Interrupt) ....................... 5-98
5.2.39 PCD
(Page Cache Disable) .......................... 5-100
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5.2.40 PCHK (Parity Status) .............................. 5-102
5.2.41 PEN (Parity Enable) ............................... 5-103
5.2.42 PRDY (Probe Ready) .............................. 5-104
5.2.43 PWT (Page Writethrough) .......................... 5-106
5.2.44 R/S (Run or Stop) ................................. 5-108
5.2.45 RESET (Reset) .................................... 5-110
5.2.46 SCYC (Split Cycle) ..... ' ........................... 5-115
5.2.47 sm(System
Management Interrupt) ................. 5-117
5.2.48 SMIACT (System Management Interrupt Active) ....... 5-122
5.2.49 STPCLK (Stop Clock) .............................. 5-123
5.2.50 TCK (Test Clock) .................................. 5-128
5.2.51 TDI (Test Data Input) .............................. 5-129
5.2.52 TDO (Test
Data Output) ............................ 5-130
5.2.53 TMS (Test Mode Select) ............................ 5-131
5.2.54 TRST (Test Reset) ................................. 5-132
5.2.55 WfR (Write or Read) ............................... 5-133
5.2.56 WBIWT
(Writeback or Writethrough) ................. 5-134
5.3 Bus Cycle Overview ................................. 5·137
5.3.1 Cycle Definitions .................................. 5-137
5.3.2 Addressing ............. ; ......................... 5-138
5.3.3 Alignment ........................................ 5-139
5.3.4 Bus Speed and Typical DRAM Timing ................ 5-140
5.3.5 Bus-Cy<;le Priorities ................................ 5-140
5.4 Bus Cycle Timing ................................... 5·141
5.4.1 Timing Diagrams .................................. 5-141
5.4.2 Single-Transfer Reads and Writes .................... 5-142
Single-Transfer Memory Read and Write .............. 5-142
Single-Transfer
Memory Write Delayed by EWBE Signal 5-145
I/O Read and Write ................................ 5-147
Single-Transfer Misaligned Memory and I/O Transfers .. 5-148
5.4.3
Burst Cycles ...................................... 5-150
Burst Read ............................. " ........ 5-150
Burst Writeback ................................... 5-154
5.4.4 Bus Arbitration and Inquire Cycles ................... 5-157
AHOLD-Initiated
Inquire Miss ...................... 5-158
AHOLD-Initiated
Inquire Hit to Shared or Exclusive Line 5-160
AHOLD-Initiated Inquire Hit to Modified Line ......... 5-161
Bus Backoff (BUFF) ................................ 5-163
BUFF-Initiated Inquire Hit to Modified Line ........... 5-165
HOLD-Initiated Inquire Hit to Shared or Exclusive Line . 5-167
HOLD-Initiated Inquire Hit to Modified Line .......... 5-169
5.4.5 Locked Cycles .................................... 5-170
Basic Locked Operation ............................ 5-170
TLB Miss (4-Kbyte Page) ........................... 5-172
Locked Operation with BUFF Intervention ............ 5-174
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18524BjO- Mar1996 AMD5 J<!36 Processor Technical Reference Manual
Interrupt Acknowledge Operation ................... 5-176
5.4.6
Special Bus Cycles ................................. 5-181
Basic
Special Bus Cycle ............................ 5-182
Shutdown Cycle ................................... 5-183
FLOSH-Acknowledge Cycle
......................... 5-184
Cache-Invalidation Cycle (INVD Instruction) .......... 5-185
Cache-Writeback and Invalidation Cycle
(WBINVD
Instruction) ............................. 5-186
Branch-Trace
Message Cycles ....................... 5-188
5.4.7
Mode Transitions, Reset, and Testing ................. 5-190
Transition from Normal Execution to SMM ............ 5-190
Stop-Grant and Stop-Clock States .................... 5-193
INIT-Initiated Transition from Protected Mode to
Real Mode ....................................... 5-196
6 System Design 6·1
6.1 Memory ............................................. 6-1
6.1.1 Memory Map ....................................... 6-2
6.1.2
Memory-Decoder Aliasing of Boot ROM Space ........... 6-4
6.1.3
Cacheable and Noncacheable Address Spaces ........... 6-4
6.1.4 SMM
Memory Space and Cache ability .................. 6-5
6.2 Cache ............................................... 6-8
6.2.1 L2 Cache ........................................... 6-9
6.2.2
Cache ability and Cache-State Control .................. 6-9
6.2.3
Write through vs. Writeback Coherency States .......... 6-10
6.2.4 Inquire Cycles ..................................... 6-12
6.2.5 Bus
Arbitration for Inquire Cycles .................... 6-14
BUFF Arbitration .................................. 6-15
AHOLD Arbitration ................................ 6-17
HOLD Arbitration .................................. 6-19
6.2.6 Write-Once
Protocol ................................ 6-19
6.2.7
Cache Invalidations ................................. 6-22
6.2.8
AZOJ.IJ Masking of Cache Accesses . . . . . . . . . . . . . . . . . . . . . 6-22
6.3 System Management Mode (SMM) ..................... 6-23
6.3.1 Operating Mode and Default Register Values ........... 6-24
6.3.2 SMM
State-Save Area ............................... 6-25
6.3.3 SMM
Revision Identifier ............................ 6-28
6.3.4 SMM Base
Address ................................. 6-28
6.3.5
Halt Restart Slot ................................... 6-30
6.3.6 JJO Trap Dword .................................... 6-31
6.3.7
JJO Trap Restart Slot ................................ 6-31
6.3.8
Exceptions and Interrupts in SMM . . . . . . . . . . . . . . . . . . . . 6-32
6.3.9 SMM
Compatibility with Pentium Processor . . . . . . . . . . . . 6-33
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6.4 Clock Control ....................................... 6-33
6.4.1 State Transitions ................................... 6-34
6.4.2
Halt State ........... _. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34
6.4.3
Stop Grant State ................................... 6-37
6.4.4
Stop Grant Inquire State ............................ 6-37
6.4.5
Stop Clock State ................................... 6-38
6.4.6 Clock
Control Compatibility with Pentium Processor .... 6-38
6.5 Power and Ground Design ............................. 6-38
6.6 Clock
Design ........................................ 6·40
6.6.1 Noise Reduction ................................... 6-43
6.7 Thermal Design ..................................... 6-44
6.8
Design Support and Peripheral Products ................ 6·45
7 Test and Debug
7-1
7.1 Hardware Configuration Register (HWCR) ............... 7·3
7.2 Built·In Self Test (BIST) ............................... 7-5
7.2.1 Normal BIST ........................................ 7-5
7.2.2 Test Access Port (TAP) BIST .......................... 7-6
7.3 Output.Float Test ..................................... 7·7
7.4 Cache and TLB Testing ................................ 7·7
7.4.1 Array Access Register (AAR) ......................... 7-8
7.4.2 Array Pointer ....................................... 7-9
7.4.3 Array Test Data .................................... 7-10
7.5 Debug Registers ..................................... 7-16
7.5.1 Standard Debug Functions ........................... 7-16
7.5.2 IJO Breakpoint Extension ............................ 7-16
7.5.3
Debug Compatibility with Pentium Processor ........... 7-17
7.6 Branch Tracing ...................................... 7·17
7.7 Functional·Redundancy Checking ...................... 7·18
7.8 Boundary·Scan Test Access Port (TAP) .................. 7-19
7.8.1 Device Identification Register ........................ 7-21
7.8.2
Public Instructions ................................. 7-22
7.9 Hardware Debug Tool (HDT) .......................... 7·23
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AMD51(fJ6 Processor Technical Reference Manual
Appendix A Compatibility With the Pentium and 486 Processors
A-I
A.1 Bus Signals ......................................... A-2
A.lol Signal Comparison .................................. A-2
A.2 Bus Interface ....................................... A-5
A.2.l Updates to Descriptor Accessed and TSS Busy Bits ....... A-S
A.2.2 Locked and Unlocked CMPXCHG8B Operation .......... A-S
A.2.3 Bus Cycle Order of Misaligned Memory and 110 Cycles .... A-6
A.2A Halt Cycle after FLUSH .............................. A-6
A.2.S
Selectable Drive Strengths on Output Driver ............ A-6
Comments .......................................... A-7
A.3 Bus Mastering Operations (including Snooping) .......... A-8
A.3.l AHOLD Snoop to Linefill Buffer Prior to or Coincident
with the Establishment of the Cacheability of the Line .... A-8
Comments .......................................... A-8
A.3.2 :mJFF
Asserted before Snoop to Linefill Buffer and
after the Cacheability of the Line is Established .......... A-8
Comments .......................................... A-9
A.3.3 Snoop
Before Write Hit to ICACHE Appears on Bus ...... A-9
A.3A Invalidations during a FLUSHIWBINVD ................ A-9
A.3.5
Cache Line Ownership ............................... A-9
A.3.6
Write Hit to a Shared Line in the DCACHE ............. A-l0
A.4 Memory Management ............................... A-ll
AA.l Speculative TLB Refills ............................. A-ll
AA.2 Page Fault Encountered by a Load/Store Type
of Instruction ...................................... A-ll
A.5 Power Saving Features .............................. A-12
A.S.l STPCLK in Halt State ............................... A-12
A.S.2 STPCLK
Pulse does not Guarantee That One
Instruction Executes ................................ A-12
A.S.3
Simultaneous 110 SM! Trap and Debug Breakpoint Trap .. A-12
A.SA
Sl\1lV[ Save Area .................................... A-12
A.S.S NM!
Recognition during Sl\1lV[ ........................ A-13
Comment ................................... : ..... A-13
A.6 Exceptions ......................................... A-14
A.6.l Limit Faults on an Invalid Instruction ................. A-14
A.6.2
Task Switch ....................................... A-14
A.7 Debug ............................................ A-15
A.7.l Proprietary Branch Trace Messages ................... A-1S
A.7.2
Multiple Debug Breakpoint Matches .................. A-1S
A.7.3
Simultaneous Debug Trap and Debug Fault ............ A-1S
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AMD~
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AMD5[(fJ6 Processor Technical Reference Manual
List of Figures
FIGURE 2-1.
FIGURE 2-2.
FIGURE 3-l.
FIGURE 3-2.
FIGURE 3-3.
FIGURE 3-4.
FIGURE 3-5.
FIGURE 3-6.
FIGURE 3-7.
FIGURE 3-8.
FIGURE 3-9.
FIGURE 5-l.
FIGURE 5-2.
FIGURE 5-3.
FIGURE 5-4.
Internal Architecture, with Pipeline Stage . . . . . . . . . . . 2-2
Pipeline Stage Functions . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Control Register 4 (CR4) .......................... 3-2
4-Kbyte
Paging Mechanism ........................ 3-5
4-Mbyte
Paging Mechanism ........................ 3-6
Page-Directory
Entry (PDE) ........................ 3-7
Page-Table
Entry (PTE) .......................... 3-10
EFLAGS
Register ............................... 3-15
Task State Segment (TSS) ........................ 3-22
Machine-Check Address Register (MCAR) . . . . . . . . . . 3-25
Machine-Check
Type Register (MCTR) ............. 3-26
Signal Groups ................................. _ .. 5-3
Single-Transfer Memory Read and Write ........... 5-144
Single-Transfer
Memory Write Delayed by
EWBE Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-146
I/O Read and Write ............................. 5-147
FIGURE 5-5. Single-Transfer Misaligned Memory and
FIGURE 5-6.
FIGURE 5-7.
FIGURE 5-8.
FIGURE 5-9.
FIGURE 5-10.
FIGURE 5-1l.
FIGURE 5-12.
FIGURE 5-13.
FIGURE 5-14.
I/O Transfers .................................. 5-149
Burst Reads ................................... 5-152
Burst Read (NA Sampled) ....................... 5-153
Burst Writeback Due To Cache-Line Replacement ... 5-156
AHOLD-Initiated
Inquire Miss ................... 5-159
AHOLD-Initiated
Inquire Hit to Shared or
Exclusive Line ................................. 5-160
AHOLD-Initiated Inquire Hit to Modified Line ...... 5-162
Basic
BUFF Operation .......................... 5-164
BUFF-Initiated Inquire Hit to Modified Line ........ 5-166
HOLD-Initiated
Inquire Hit to Shared or
Exclusive Line ................................. 5-168
FIGURE 5-15. HOLD-Initiated Inquire Hit to Modified Line ....... 5-169
FIGURE 5-16. Basic Locked Operation ......................... 5-171
FIGURE 5-17. TLB Miss (4-Kbyte Page) ........................ 5-173
FIGURE 5-18. Locked Operation with BUFF Intervention ......... 5-175
FIGURE 5-19A. Interrupt Acknowledge Operation Part 1. . . . . . . . . .. 5-178
FIGURE 5-19B. Interrupt Acknowledge Operation Part 2 ........... 5-179
FIGURE 5-19C. Interrupt Acknowledge Operation Part 3 ........... 5-180
FIGURE 5-20. Basic Special Bus Cycle (Halt Cycle) .............. 5-182
FIGURE 5-21. Shutdown Cycle ................................ 5-183
FIGURE 5-22. FLUSH-Acknowledge Cycle ...................... 5-184
FIGURE 5-23. Cache-Invalidation Cycle (INVD Instruction) ....... 5-185
FIGURE 5-24A. Cache-Writeback and Invalidation Cycle
(WBINVD
Instruction) Part 1. .................... 5-186
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xii
FIGURE 5-24B. Cache-Writeback and Invalidation Cycle
(WBINVD
Instruction) Part 2 ............ : ........ 5-187
FIGURE 5-25. Branch-Trace Message Cycle ..................... 5-189
FIGURE 5-26A. Transition from Normal Execution to SMM Part 1 ... 5-191
FIGURE 5-26B. Transition from Normal Execution to SMM Part 2 ... 5-192
FIGURE 5-27 A. Stop-Grant and Stop-Clock Modes Part 1 ........... 5-194
FIGURE 5-27B. Stop-Grant and Stop-Clock Modes Part 2 ........... 5-195
FIGURE 5-28. INIT-Initiated Transition from Protected
FIGURE 6-1.
FIGURE 6-2.
FIGURE 6-3.
FIGURE 6-4.
FIGURE 6-5.
FIGURE 6-6.
FIGURE 6-7.
FIGURE 6-8.
FIGURE 6-9.
FIGURE 6-10.
FIGURE 7-1.
FIGURE 7-2.
FIGURE 7-3.
FIGURE 7-4.
FIGURE 7-5.
FIGURE 7-6.
FIGURE 7~7.
FIGURE 7-8.
Mode to Real Mode ............................. 5-197
Typical Desktop-System BIOS
Memory Map . . . . . . . . . . 6-3
Default SMM Memory Map ........................ 6-7
BUFF Example .................................. 6-16
AHOLD and BUFF Example ...................... 6-18
Write-Once Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
Clock Control
State Transitions. . . . . . . . . . . . . . . . . . . . 6-36
Vee and CLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40
CLK Delay Function ............................. 6-41
CLK Synthesizer with Output Enable. . . . . . . . . . . . . . . 6-42
CPUCLK Clamping Circuit .. . . . . . . . . . . . . . . . . . . . . . 6-42
Hardware Configuration Register (HWCR) ........... 7-3
Array Access Register (AAR) ...................... 7-8
Test Formats: Data-Cache Tags .................... 7-10
Test Formats: Data-Cache Data .................... 7-11
Test Formats: Instruction-Cache Tags ............... 7-12
Test Formats: Instruction-Cache Instructions ........ 7-13
Test Formats: 4-Kbyte TLB ........................ 7-14
Test Formats: 4-Mbyte TLB ....................... 7-15

AMD~
18524B/O-Mar1996
AMD5~6 Processor Technical Reference Manual
List of Tables
TABLE 2-1. ALU Instruction Classes ............................. 2-9
TABLE 2-2.
Cache States for Read and Write Accesses ............ 2-19
TABLE 2-3.
Cache States for Snoops, Invalidation, and Replacements 2-20
TABLE 2-4. Snoop Action ..................................... 2-22
TABLE 3-1.
Control Register 4 (CR4) Fields ...................... 3-3
TABLE 3-2. Page-Directory Entry (PDE) Fields .................... 3-8
TABLE 3-3.
Page-Table Entry (PTE) Fields ...................... 3-11
TABLE 3-4.
Virtual-Interrupt Additions to EFLAGS Register ....... 3-15
TABLE 3-5.
Instructions that Modify the IF or VIF Flags ........... 3-16
TABLE 3-6.
Interrupt Behavior and Interrupt-Table Access ......... 3-23
TABLE 3-7.
Machine-Check Type Register (MCTR) Fields ......... 3-27
TABLE 4-1.
Integer Instructions ................................. 4-8
TABLE 4-2. Integer Dot Product Internal Operations Timing ....... 4-18
TABLE 4-3.
Floating-Point Instructions .......................... 4-19
TABLE 5-1.
Summary of Signal Characteristics .................... 5-4
TABLE 5-2.
Conditions for Driving and Sampling Signals ........... 5-9
TABLE 5-3. Summary of Interrupts and Exceptions ............... 5-17
TABLE 5-4.
Address-Generation Sequence During Bursts .......... 5-22
TABLE 5-5.
Relation Of Jffi7-BEO To Other Signals ............... 5-35
TABLE 5-6.
Encodings For Special Bus Cycles .................... 5-36
TABLE 5-7. Processor-to-Bus Clock
Ratios ....................... 5-37
TABLE 5-8.
Outputs Floated When :BUFF is Asserted .............. 5-39
TABLE 5-9. MESI-State Transitions for Reads .................... 5-52
TABLE 5-10.
Relation Between D63-DO, BE7-BEO, and DP7-DPO .... 5-57
TABLE 5-11. MESI-State
Transitions for Inquire Cycles ............. 5-73
TABLE 5-12.
Outputs Floated When HLDA is Asserted ............. 5-76
TABLE 5-13.
Interrupt Acknowledge Operation Definition .......... 5-86
TABLE 5-14. PWT,
WritebacklWritethrough, and MESI ............ 5-106
TABLE 5-15.
Register State After RESET or INIT ................. 5-111
TABLE 5-16.
Outputs at RESET ................................ 5-113
TABLE 5-17.
MESI-State Transitions for Reads ................... 5-135
TABLE 5-18. MESI-State
Transitions for Writes .................. 5-136
TABLE 5-19. Bus Cycle Definitions ............................. 5-137
TABLE 5-20. Bus-Cycle
Order During Misaligned Transfers ......... 5-148
TABLE 5-21.
Address-Generation Sequence During Bursts ......... 5-151
TABLE 5-22.
Interrupt Acknowledge Operation Definition ......... 5-176
TABLE 5-23.
Encodings For Special Bus Cycles ................... 5-181
TABLE 5-24.
Branch-Trace Message Special Bus Cycle Fields ....... 5-188
TABLE 6-1.
Initial State of Registers in SMM .................... 6-25
TABLE 6-2. SMM
State-Save Area Map .......................... 6-26
TABLE 7-1.
Hardware Configuration Register (HWCR) Fields ....... 7-4
TABLE 7-2. BIST Error Bit Definition in EAX Register ............. 7-6
TABLE 7-3. Array IDs in Array Pointers .......................... 7-9
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TABLE 7-4. Branch-Trace Message Special Bus Cycle Fields ........ 7-18
TABLE 7-5.
Test Access Port (TAP) ID Code ..................... 7-21
TABLE 7-6.
Public TAP Instructions ............................ 7-22
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AMD5~6 Processor Technicol Reference Manual
Preface
This manual describes the technical features of the AMD5K86™ processor, and its
differences from the Pentium processor, at a level of detail suitable for a hardware
designer or system-software developer to implement system boards, core system
logic, and system software. Specifically, the manual describes the following aspects
of the processor
• Internal architecture
• Software differences from the 486 and Pentium processors
• Performance parameters
• Bus signals functions
• Bus cycle timing
• Design issues for system-board designs
• Test and debugging features
A full description of the x86 programming environment is beyond the scope of this
manual. Instead, the software sections describe differences from the 486 processor's
programming environment. A list of commercial books that describe the x86 pro-
gramming environment and other subjects of potential interest appears at the end of
this preface.
In addition to descriptions of the AMD5K86 processor's unique internal architecture,
the manual incorporates details about the behavior of bus signals and bus cycles that
are standard to the x86 processors but that are not fully documented in other x86
manuals.
Notation
The following notation is used in this manual:
b-Binary
d-Decimal
h-Hexadecimal
Set- Written with a value of 1
Clear- Written with a value of 0
GP (D)-General-protection exception (13 decimal) with an error value of 0
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EFLAGS.IF- The IF bit in the EFLAGS register
CS:EIP-A logical address, expressed as a segment selector (CS) and offset (EIP)
OOOF_FFFOh-A physical-memory address using hexadecimal notation
Terminology
The following definitions apply throughout this document:
• Pin and Signal-A pin is a piece of metal on the processor's package. A signal is
the information about logical states that a pin carries. Pins have pin numbers; sig-
nals have signal names. On processors that multiplex signals, pins can carry more
than one signal; the AMDSK86 processor, however, does not multiplex signals in
this manner.
• Assert and Negate-A signal that is driven or sampled active is asserted. A signal
that is inactive is negated. In general, asserted means sampled asserted either by
the processor or target logic. Signals that are active in a Low-voltage state, such as
BRDY, are shown with an overbar. Signals that are active in a High-voltage state,
such as INTR, are shown without an overbar. Dual-state signals, such as R/S and
WBfWT, have two states of assertion and, therefore, the term asserted has no
meaning; such dual-state signals are driven High or Low.
• Drive and Sample-A single-state signal is driven when it is asserted or negated by
a logic device; it is sampled when its driven state is detected by another device.
• Cycle and Clock- This term commonly refers to at least four different things:
xvi
• Bus-clock period: The cycle time of the CLK signal.
• Processor-clock period: The cycle time of the processor's internal clock, which
has a frequency relative to CLK that is determined by the state of the BF sig-
nal during RESET. Whenever this cycle is meant, such as in the Chapter 4 de-
scription of pipeline timing and the instruction latency, the full name,
processor-clock cycle, is used.
• Bus cycle: A signal protocol on the processor's bus, such as a single-transfer
read cycle or a special bus cycle.
• Sequence oj buscycles: One or more contiguous bus cycles. For example, the two
bus cycles that constitute an interrupt acknowledgment are called a bus opera-
tion, so that the constituent bus cycles can be distinguished from the entire op-
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AMD5,!J6 Processor Technical Reference Manual
• Writeback- This term refers to two related concepts:
• Bus Cycle-A 32-byte burst write cycle to a memory block that has been cached
in the modified state. Writebacks can be caused by inquire cycles, internal
snoops, writeback and invalidate operations (such as FLUSH or the WBINVD
instruction), cache-line replacements, or locked operations on cached loca-
tions.
It is sometimes called a copyback.
• Cache-Line State-A cache line in the modified or exclusive MESI state (modi-
fied,
exclusive, shared, invalid).
• Writethrough- This term refers to two related concepts:
• Bus Cycle-A I-to-8-byte, single-transfer write cycle caused by write misses or
write hits to lines in the shared or exclusive MESI state.
• Cache-Line State-A cache line in the shared MESI state.
• Flush-This term commonly refers to at least four things and is usually avoided in
favor of the following specific terms:
• Pipeline Invalidation: A pipeline-flush operation invalidates instructions in the
pipeline that have not been retired (and, depending on the type of pipeline in-
validation, entries in the reorder buffer, entries in the TLB, and/or branch-pre-
diction bits) without writing their state to any storage resource.
• Cache Invalidation: The INVD instruction invalidates the contents of the in-
struction and data caches, without writing modified data back to memory.
Cache Writeback and Invalidation: The WBINVD instruction writes modified
lines in the data cache back to memory while invalidating each line in the in-
struction and data caches.
FLUSH Operation: The FLUSH input signal executes the same microcode rou-
tine as the WBINVD instruction to write modified lines in the data cache back
to memory while invalidating each line in the instruction and data caches.
• Flush Acknowledge Cycle- This term commonly refers to different types of special
bus cycles driven by the processor, and is therefore avoided in favor of the follow-
ing specific terms:
• FLUSHAcknowledge: A special bus cycle driven after the FLUSH operation
completes.
• INVD Acknowledge: A special bus cycle driven after the INVD cache invalida-
tion completes.
• WBINVD Acknowledge: A sequence of two special bus cycles driven after the
WBINVD cache write back and invalidation completes.
• Snoop-This term commonly refers to at least three different actions and is there-
fore avoided in favor ofthe following specific terms:
• Inquire Cycles: These are bus cycles driven by system logic. They cause the pro-
cessor to compare the inquire-cycle address with the processor's physical
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cache tags. The AMD5K86 and Pentium processors both support inquire cycles.
Internal Snooping: These snoops are initiated by the processor (rather than sys-
tem logic) during certain types of cache accesses. Both the AMD5K 86 and Pen-
tium microprocessors support this type of internal snooping for the purpose of
detecting self-modifying code. See page 2-22 for details.
• Bus Watch: Some caching devices watch their address and data bus continu-
ously while they are held off the bus. They compare every address driven by
another bus master with their internal cache tags, and they may also be able to
update their cached lines during writebacks to memory by another bus master.
Neither the AMD5K86 nor Pentium microprocessors support bus watching.
• Cold and Warm Reset-The terms cold or hard reset and warm or soft reset are
commonly used to mean three related but different things, and the terms are
therefore avoided. A cold or hard reset typically refers to the assertion of RESET
at power-up, but warm or soft reset can refer either to the assertion of RESET
after power-up or to the assertion of INIT.
• System Logic-Any logic outside the processor, including a core-logic chipset,
another bus master, or separate controllers for L2 cache, memory, interrupts,
DMA, communications, video, bus bridging, bus arbitration, or any other system
function.
References
Abel, Peter. IBM PC AssemblyLanguage and Programming. Englewood Cliffs: Prentice
Hall,1995.
Abramovici, Miron; Melvin A. Breuer; and Arthur D. Friedman. Digital Systems Test-
ing and Testable Design. New York: IEEE Press, 1990.
Agarwal, Rakesh. 80x86Architecture& Programming. Vols. I and II. Englewood Cliffs:
Prentice-Hall, 1991.
Alexandridis, Nikitas. Design of Microprocessor-Based Systems. Englewood Cliffs: Pren-
tice-Hall, 1993.
Anderson, Don, and Tom Shanley. Pentium Processor System Architecture. Reading:
Addison-Wesley, 1995.
Barkakati, Nabajyoti, and Randall Hyde. Microsoft Macro AssemblerBible. Carmel:
Sams, 1992.
Brey, Barry B. The Intel 32-Bit Microprocessors. Englewood Cliffs: Prentice Hall, 1995.
Brown, Ralf, and Jim Kyle. PC Interrupts, A Programmer's Reference to BIOS, DOS, and
Third-Party Calls. Reading: Addison-Wesley, 1994. For an updated version on the
Internet, ftp to oak. oakl and. edu and get file /pub/msdos/i nfo/i nter41. zi p.
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AMD5,IJ6 Processor Technical Reference Manual
Brumm, Penn, and Don Brumm. 80386/80486Assembly Language Programming. Wind-
crest: McGraw-Hill, 1993.
Chappell, Geoff. DOS Internals. Reading: Addison-Wesley, 1994.
Crawford, John H., and Patrick P. Gelsinger. Programming the 80386. San Francisco:
Sybex, 1987.
Giles, William B. Assembly Language Programmingfor theIntel 80xxx Family. New
York: Macmillan, 1991.
Handy, Jim. The Cache Memory Book. San Diego: Academic Press, 1993.
Hennessy, John L., and David A. Patterson. ComputerArchitecture, A Quantitative
Approach.
2d Ed. San Francisco: Morgan Kaufmann Publishers, 1996.
Hogan, Thorn. The Programmer's PC Sourcebook. Redmond: Microsoft Press, 1991.
Hwang, Kai. Advanced Computer Architecture. New York: McGraw-Hill, 1993.
Institute of Electrical and Electronics Engineers. IEEE Standard for Binary Floating-
PointArithmetic. ANSIlIEEE Std 754-1985.
Institute of Electrical and Electronics Engineers. IEEE Standard for Radix-Indepen-
dentFloating-PointArithmetic.
ANSIlIEEE Std 854-1987.
Institute of Electrical and Electronics Engineers. IEEE Standard Glossary of Mathe-
matics of Computing Terminology. ANSIIIEEE Std 1084-1986. Out of print.
Johnson, Mike. Superscalar Microprocessor Design. Englewood Cliffs: Prentice-Hall,
1991.
Katz, Randy H. Contemporary Logic Design. Redwood City: Benjamin Cummings,
1994.
Morse, Stephen P.; Eric J. Isaacson; and Douglas J. Albert. The 803861387Architec-
ture. New York: John Wiley & Sons, 1987.
Norton, Peter; Peter Aitken; and Richard Wilton. PC Programmer's Bible. Redmond:
Microsoft Press, 1993.
Parker, Kenneth P. The Boundary-Scan Handbook. Boston: Kluiver, 1992.
Patterson, David A., and John L. Hennessy. Computer Organization and Design: The
Hardware/Software Interface.
San Francisco: Morgan Kaufmann Publishers, 1994.
Phoenix Technical Reference Series. System BIOS for IBM PCs, Compatibles, and EISA
Computers. Reading: Addison-Wesley, 1991.
xix