Intel iAPX 86/88 User manual

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iAPX 86/88, 186/188 User's Manual
Hardware Reference
1985

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Chapter 1
8086/8088 CPU
Table of Contents
1.1 Introduction................................................................. 1-1
1.2 Component Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-1
1.2.1 Architectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-2
1.2.2 Software Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 1-12
1.3 Device
Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-42
1.3.1 Functional Description of All Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-43
1.3.2 Electrical Description of Pins
.................................................. 1-43
1.3.3 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 1-43
1.3.4 Minimum Mode System Overview/Description
.............. , ..................... 1-44
1.3.5 Maximum Mode System Overview/Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 1-52
1.3.6 General Design Considerations
................................................ 1-64
1.4 Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 1-64
1.4.1 Multiplexed Address and Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-64
1.4.2 Bus Cycle Definition
........................................................ 1-65
1.4.3 Address and Data Bus Concepts
............................................... 1-66
1.4.4 Memory and
110 Peripherals Interface ........................................... 1-71
1.4.5 System DeSign Alternatives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-92
1.4.6 Multiprocessor/Coprocessor Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 1-97
1.4.7 Interpreting The 8086/8088 Bus Timing Diagrams
................................. 1-98
1.4.8 Wait State Insertion
......................................................... 1-107
1.4.9 8086/8088 Instruction Sequence
............................................ , .. 1-109
1.5 Bus Exchange Mechanisms
.................................................... 1-110
1.5.1 Minimum Mode (HOLD/HLDA) ................................................ 1-110
1.5.2 Maximum Mode (RQ*/GT*)
................................................... 1-113
1.6 RESET
.................................................................... 1-118
1.6.1 Reset Bus Conditioning ...................................................... 1-118
1.6.2 Multiple Processor Considerations
............................................. 1-119
1.7 Interrupts
................................................................... 1-120
1
.7.1 Classes of Interrupts ........................................................ 1-120
1.7.2 Divide
Error-Type 0 ........................................................ 1-121
1.7.3 Single Step-Type 1 ........................................................ 1-121
1.7.4 Non-Maskable Interrupt-Type 2 ............................................... 1-121
1.7.5 One Byte Interrupt-Type 3 ................................................... 1-121
1.7.6 Interrupt on Overflow-Type 4 ........................................ ' ......... 1-121
1.7.7 User-Defined Software Interrupts .............................................. 1-122
1.7.8 User-Defined Hardware Interrupts
.............................................. 1-122
1.7.9 Interrupt Acknowledge
....................................................... 1-122
1.8 Support Components
......................................................... 1-125
1.8.1 8284A Clock Generator and Driver
............................................. 1-125
1.8.2 8288 Bus Controller
......................................................... 1-130
1.8.3 8289 Bus Arbiter
........................................................... 1-133
1.8.4 8259A Programmable Interrupt Controller
....................................... 1-134
1.8.5 8237A Programmable DMA Controller .......................................... 1-142
Chapter 2
80186/80188 CPU
2.1 Introduction-The High Integration Concept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
2.2 Component Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
2.2.1 Architectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
2.2.2 Software Overview .... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-4
2.3 Device Pin Definitions
......................................................... 2-12
2.3.1 Functional Description of All Signals ............................................ 2-12
2.3.2 Electrical Description of Pins
.................................................. 2-12
iii

TABLE OF CONTENTS
2.4 Operating Modes ............................................................ 2·12
2.4.1 8086/88·80186/188 Operating Mode Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·12
2.4.2 Queue Status Mode of Operation ............................................. , 2·12
2.4.3 Interrupt Controller Operating Modes ........................................... 2·19
2.5 Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·19
2.5.1 HALT Bus Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·23
2.5.2 8086/80186 Bus Operation Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·24
2.5.3 Multiplexed Address/Data Bus (186,188) ........................................ 2·29
2.5.4 Data Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·34
2.5.5 Memory and I/O Peripherals Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·34
2.5.6 Interpreting the 80186/80188 Bus Timing Diagrams ................................ 2·41
2.5.7 Wait State Generator ........................................................ 2·44
2.5.8 80186 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·46
2.6 Bus Exchange Mechanisms .................................................... 2·47
2.6.1 HOLD Response ........................................................... 2·47
2.6.2 HOLD/HLDA Timing and Bus Latency .......................................... 2·48
2.6.3 End of HOLD Timing ........................................................ 2·48
2.7 Interrupts ................................................................... 2·50
2.8 Support Circuits ............................................................. 2·51
2.8.1 Direct Memory Access (DMA) Unit ............................................. 2·51
2.8.2 Timer Unit ................................................................ 2·56
2.8.3 Interrupt Controller ......................................................... 2·59
2.8.4 Chip Select/Wait State Generation Unit ......................................... 2·74
2.8.5 Clock Generator/Reset/Ready ................................................. 2·79
Chapter 3
8087 Numeric Processor Extension
3.1 Introduction................................................................. 3·1
3.1.1 iAPX86,88,186,188Base ................................................... 3·1
3.1.2 8087 Mobility In Any iAPX 86, 88, 186 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3·2
3.2 Component Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3·3
3.2.1 Architecture Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. 3·3
3.2.2 Software Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3·7
3.3 Device Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3·8
3.4 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3·8
3.4.1 8087/8086(88) Interface ...................................................... 3·11
3.4.2 8087/80186(88) Interface ..................................................... 3·11
3.5 8086 (80186)/8087 Operation ................................................... 3·12
3.5.1 Decoding Escape Instructions ................................................. 3·12
3.5.2 Concurrent Execution of Host and Coprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3·13
3.5.3 Instruction Synchronization ................................................... 3·13
3.6 Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3·15
3.6.1 iAPX86/20 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3·15
3.6.2 iAPX186/20 Bus Operation ................................................... 3·15
3.7 Bus Exchange Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3·16
3.7.1 8087 RQ/GT Function ....................................................... 3·16
3.7.2 Delay Effects of the 8087 ..................................................... 3·17
3.7.3 Reducing 8087 Delay Effects ................................................. 3·19
3.8 Interrupts................................................................... 3·22
3.8.1 Recommended Interrupt Configurations ......................................... 3·22
Chapter 4
8089 Input/Output Processor
4.1 Introduction................................................................. 4·1
4.2 Component Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4·1
iv

TABLE OF CONTENTS
4.2.1 Architectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1
4.2.2 Software Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-3
4.3 Device Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 4-20
4.4 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-20
4.4.1 Interfacing the SOS9 to the SOS6 and S01S6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-24
4.4.2 lOP Initialization ............................................................ 4-26
4.4.3 Channel Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 4-27
4.4.4 Direct Memory Access Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 4-30
4.4.5 DMA Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-32
4.4.6 Peripheral Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-33
4.4.7 Status Lines
............................................................... 4-34
4.5 Bus Operation ............................................................... 4-34
4.6 Bus Exchange Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-36
4.6.1 Bus Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-37
4.6.2 Bus Load Limit. . . . . . . . . . . . . . . . . . . . . . . . .. .................................. 4-39
4.6.3 Bus Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 4-39
4.7 Interrupts
................................................................... 4-40
Chapter 5
80130 Operating System Firmware
5.1 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
5.2 S0130 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
5.3 Device Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
5.4 Operating System Primitives Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
5.5 Interfacing With the SOS6/SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
5.5.1 Programming The S0130 OSP's Onchip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
5.6 OSP Memory Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-11
5.7 Interrupt Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.7.1 Level-Triggered Mode ....................................................... 5-12
5.7.2 Edge-Triggered Mode
....................................................... 5-12
5.7.3 Local Interrupt Requests
..................................................... 5-13
5.7.4 Interrupt Sequence ......................................................... 5-13
5.S Timing ..................................................................... 5-13
Tables
1-1 Implicit Use of General Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-7
1-2 Logical Addresses Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 1-10
1-3 Data Transfer Instructions ......................................................... 1-13
1-4 Arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 1-14
1-5 Arithmetic Interpretation of S-Bit Numbers
............................................ 1-14
1-6 Bit Manipulation Instructions ....................................................... 1-15
1-7 String Instructions
............................................................... 1-15
1-S String Instruction Register and Flag Use .............................................. 1-15
1-9 Program Transfer Instructions ...................................................... 1-16
1-10 Interpretation of Conditional Transfers ................................................ 1-17
1-11 Processor Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-17
1-12
Key to Instruction Coding Formats .................................................. 1-22
1-13 Key to Flag Effects ............................................................... 1-23
1-14 Key to Operand Types ............................................................ 1-23
1-15 Effective Address Calculation Time .................................................. 1-24
1-16 Instruction Set Reference Data ..................................................... 1-24
1-17 Single-Bit Field Encoding ......................................................... 1-42
1-1S Mode (MOD) Field Encoding ....................................................... 1-42
1-19 REG (Register) Field Encoding ..................................................... 1-42
v

TABLE OF CONTENTS
1·20 Register/Memory Field Encoding ................................................... 1·43
1·21 Key to Machine Instruction Encoding and Decoding ..................................... 1-45
1·22 8086/88 Instruction Encoding ................................. : .................... 1·46
1·23 Machine Instruction Decoding Guide
................................................ 1·52
1·24 8086/8088 Device
Pin Descriptions .................................................. 1·61
1·25 D.C. Characteristics ............................................................. , 1·66
1·26
A.C. Timing Requirements for Minimum .............................................. 1·67
1·27
A.C. Timing Requirements for Maximum Complexity System .............................. 1·69
1·28 Minimum/Maximum Mode Pin Assignments
........................................... 1·71
1·29 Status Bit Decoding .............................................................. 1·71
1·30 Status Line Decoders ............................................................ 1·71
1·31
Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1·82
1·32 EPROM/ROM Parameters
......................................................... 1·82
1·33
Typical Static RAM Write Timing Parameters .......................................... 1·84
1·34 Cycle Dependent Write Parameters for
RAM Memories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1·84
1·35 Peripheral Compatibility Parameters
................................................. 1·89
1·36 Peripherals Cycle Dependent Parameter Requirements
.................................. 1·89
1·37 Compatible Peripherals for a 5 MHz 8086/88
.......................................... 1·90
1·38 Peripheral Requirements for Full Speed Operation with a 5MHz 8086/88
.................... 1·91
1·39 Queue Status Bit Decoding ........................................................ 1·99
1·40 Condition of 8086/88 Bus
and Output Signal Pins During Reset ........................... 1·119
1-41 8288 Outputs During Passive Modes ...................... , ......................... 1·119
1·42 Interrupt Processing Timing
....................................................... 1·121
1·43 Status Line Decode Chart .......... , .............................................. 1·131
1-44 8237A Internal Registers .......................................................... 1·146
1·45 Definition of Register Codes
....................................................... 1·147
2·1 Data Transfer Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·8
2·2 Arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 2·8
2·3 Arithmetic Interpretation of 8·Bit Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 2·9
2·4 Bit Manipulation Instructions
................................ , ........... , . . . . . . . . .. 2·9
2·5 String Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. . . . . . . . . . . .. 2·10
2.6 Program Transfer Instructions ............................................ , ......... 2·10
2·7 I
nterpretation of Conditional Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·11
2·8 Processor Control Instructions .................................................... , 2·11
2·9 Instruction Set Summary .......................................................... 2·13
2·10 80186/80188 Device
Pin Descriptions ................................................ 2·20
2·11 D.C. Characteristics ............................................................. , 2·23
2·12
A.C. Characteristics Timing Requirements ........................................ 0 ••• 2·24
2·13
A.C. Characteristics Master Interface Timing Responses. 0 ••••••••• 0 ••• 0 •••••• 0 ••••• 0 •• 0 0 2·25
2·14
A.C. Characteristics Chip·Select Timing Requirements. 0 0 0 • 0 0 0 0 0 0 0 0 0 0 0 00.0000000000. 0 00' 2·25
2·15
A.Co Characteristics CLKIN Requirements 0 0 •••• 0 0 ••• 0 0 •• 0 • 0 • 0 0 0 0 •••••• 0 •••• 0 • 0 ••• 0 ••• 2·26
2·16
A.C. Characteristics CLKOUT Requirements ........... 0 0 0 •••••••• 0 •••••••••••••• 0 •••• 2·26
2·17 80186 Queue
Status. 0 ••••• 0 •• 0 •••• 0 •• 0 0 ••••• 0 ••••• 0 • 0 •• 0 •••• 0 •••••• 0 •••••••••••• 2·28
2·18 80186 Status Line Interpretation 0
••••••••••••• 0 •••••• 0 • 0 •••• 0 • 0 ••• 0 ••• 0 ; ••••• 0 •••••• 2·32
2·19 Bank Selection Decoding
and Word Expansion .................... 0 •••••••••••••• 0 ••• 0 2·41
2·20 80186 Bus Signals ................. 0 ••• 0 •••• 0 •••• 0 •• 0 • 0 0 ••• 0 ••• 0 ••• 0 •• 0 • 0 •••••• o' 2·42
2·21 80186/188 Interrupt Vectors ............ 0 •••••••••••••• 0 •••• 0 •••••••••••••• 0 ••• 0 •• 0 0 2·50
2·22 DMA Request Inactive Timing. 0 • 0
•••• 0 0 ••••••• 0 0 • 0 • 0 •••••• 0 •• 0 ••••• 0 ••• 0 ••••••••• o' 2·57
2·23 Timer Control Block Format
.... 0 0 0 •• 0 0 •••••••• 0 ••••••••• 0 • 0 •• 0 ••••• 0 ••• 0 •••••••••• , 2·57
2·24 Internal Source Priority Level
........... 0 •••••• 0 •• 0 •••• 0 • 0 •••• 0 0 •••••• 0 • 0 ••••••• 0 •• 2·65
2·25 80186 Interrupt Vector
Types ......................... 0 •••••••••• 0 ••• 0 • 0 •••••• 0 • 0 0 •• 2·73
2·26
UMCS Programming Values .... 0 •••••••• 0 ••••• 0 ••• 0 • 0 •••• 0 ••••••••••••••••••••••• , 2·76
2·27
LMCS Programming Values . 0 •••••••••••••••••••••••• 0 ••••• 0 •••••••• 0 •••• 0 0 •• 0 • 0 • 0 2·77
2·28
MPCS Programming Values. 0 0 • 0 •• 0 •• 0 ••• 0 •••• 0 • 0 ••• 0 •••••••••••••••••• 0 •••••••••• 2·77
2·29 80186WAIT State Programming
.......... 0 •••••••••••••• 0 •••••••••••••••••••••••••• 2·78
2·30 80186 Initial Register State After RESET
............................................. 2·81
vi

TABLE OF CONTENTS
3-1 8087 Device Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-9
3-2 Worst Case Local Bus Request Wait Times In Clocks ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
4-1 Physical/Logical Bus Combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-2
4-2 Channel Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. 4-4
4-3
Instruction Set Reference Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-7
4-4
Operand Identifiers Definitions ..................................................... 4-14
4-5 Operand Type Definitions ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-14
4-6 Instruction Fetch Timings (Clock Periods) ............................................. 4-15
4-7 8089 Instruction Encoding ......................................................... 4-15
4-8 8089 Machine Instruction Decoding Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-21
4-9 R/B/P Field Encoding .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-21
4-10 WB Field Encoding .............................................................. 4-21
4-11 AA Field Encoding ............................................................... 4-22
4-12 MM Field Encoding .............................................................. 4-22
4-13 8089 DIP Pin Assignments ........................................................ 4-23
4-14 DMA Assembly Register Operation .................................................. 4-31
4-15 DMA Transfer Cycles ............................................................. 4-32
4-16 Status Signals SO-S2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-34
4-17 Status Signals S3-S6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-34
4-18 Data Bus Usage ................................................................. 4-37
4-19 Bus Cycle Decoding ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-37
4-20 Type of Cycle Decoding ......................................................... ;. 4-37
4-21 Bus Arbitration Requirements and Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-39
5-1 80130 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-4
5-2
OSP Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-6
5-3 Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .. 5-8
5-4
Mnemonic Codes for Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-9
5-5
Baud Rate Counter Values (16X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-11
Figures
1-1 Small 8088-Based System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-2
1-2 8086/8088/8089 Multiprocessing System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-3
1-3
8086 Simplified Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-4
1-4 8088 Simplified Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-5
1-5
Overlapped Instruction Fetch and Execution .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-6
1-6 General Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-7
1-7
Segment Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-7
1-8
Status Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-7
1-9
Segment Locations in Physical Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-8
1-10 Currently Addressable Segments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-8
1-11 Logical and Physical Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-9
1-12 Physical Address Generation ...................................................... 1-10
1-13 Dynamic Code Relocation ........................................................ , 1-11
1-14 Stack Operation ............................................... ; ................. 1-12
1-15 Reserved Memory and I/O Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-12
1-16 Flag Storage Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. 1-13
1-17 Memory Address Computation ..................................................... 1-19
1-18
Direct Addressing .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-19
1-19
Register Indirect Addressing ....................................................... 1-19
1-20 Based Addressing ............................................................... 1-19
1-21 Accessing A Structure With Based Addressing ......................................... 1-20
1-22 Indexed Addressing .............................................................. 1-20
1-23
Accessing an Array with Indexed Addressing .......................................... 1-20
1-24 Based Index Addressing ............................................... ; . . . . . . . . .. 1-20
1-25
Accessing a Stacked Array with Based Index Addressing ................................ 1-21
vii

TABLE OF CONTENTS
1-26 String Operand Addressing .......................... ; ......... , ..... : ; ........... , 1-21
1-27 110 Port Addressing ................................................. " ........... 1-21
1-28 Typical 8086/88 Machine Instruction Format. ...................... , ................... 1-41
1-29 Machine Instruction Encoding Matrix ................................................ 1-44
1-30 8086/8088 DIP Pin Assignments .................................................... 1-65
1-31 Minimum Mode Waveforms ........................................................ 1-72
1-32 Maximum Mode Waveforms ....................................................... 1-74
1-33 Elementary Maximum Mode System ................................................. 1-76
1-34 8086/88 Minimum Mode System ................................................ : ... 1-77
1-35 8086/88 Maximum Mode System ................................................... 1-77
1-36 8086/88 Queue Tracking Circuit .................................................... 1-78
1-37 8086/88 Lock Activity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-78
1-38 Decoding Memory and 110 RD" and WR" Commands ................................... 1-79
1-39 Linear Select for
110 . ............................................................. 1-79
1-40 Basic 8086/88 Bus Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-80
1-41 8086 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-80
1-42 Memory
Even and Odd Data Byte Transfers .......................................... , 1-81
1-43 Memory Even and Odd Data Word Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-82
1-44 8086/8088 Memory Organization ............................. , ..................... 1-82
1-45 Reserved Memory Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-82
1-46 8086/8088 Memory Array ......................................................... 1-83
1-47 EPROMIROM Bus Interface ....................................................... 1-83
1-48 Chip Select Generation for Devices Without Output Enables. . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 1-83
1-49 Chip Selection for Devices With Output Enables
....................................... 1-84
1-50 Sample Compatibility Analysis Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-84
1-51 5 MHz 8086 System USing an 8202 Dynamic RAM Controller ............................. 1-85
1-52 8202 Timing Information ............................................. , ............ 1-86
1-53 2118 Family Timing
.............................................................. 1-87
1-54 110 Device Chip Select Techniques .................................................. 1-88
1-55 16-bit to 8-bit Bus Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 1-88
1-56 Bipolar PROM Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-88
1-57 16-bit I/O Decode ................................................................ 1-88
1-58 8086 System Configurations
...................................................... , 1-90
1-59 Device Assignment ..................................... ; . . . . . . . . . . . . . . . . . . . . . . .. 1-91
1-60 110 Input Request Code Example ................................ , ................. , 1-92
1-61 Block Transfer to 16-bit 110 Using 8086/88 String Primitives ............................... 1-92
1-62 Block Transfer to 8-bit
110 USing 8086/88 String Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. 1-92
1-63 Code For Block Transfers
.......................................................... 1-93
1-64 Multiplexed Data Bus ............................................................. 1-93
1-65 Buffered Data
Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-93
1-66 Devices With Output Enable
on the Multiplexed Bus .................................... 1-93
1-67 Relationship of ALE to READ
...................................................... 1-94
1-68 Devices Without Output Enable
on the Multiplexed Bus .................................. 1-94
1-69 Access Time:
CS Gated with AO"twR" .............................................. 1-94
1-70
CE TO WR" Setup and Hold ...................................................... , 1-94
1-71 Bus Transceiver Control. .......................................................... 1-95
1-72 Devices With Output Enable on the System Bus ....................................... 1-95
1-73 CS"/Bus Driving Device Timing .................................................... 1-95
1-74 De-multiplexing Address and Data From the Processor Bus
.............................. 1-96
1-75 Multiplexed Bus With Local Address Oemultiplexing ................................... , 1-96
1-76 Fully Buffered System ...................................................•......... 1-97
1-77 ContrOlling System Transceivers with DEN and OT/R" ................................... 1-97
1-78 Buffering Devices with OE"/RO" ......................................... " ..... " .. 1-97
1-79 Buffering Devices Without OE"/RO" and With Common or Separate Input/Output. ............ 1-97
1-80 Buffering Devices Without OE"/RO" and With Common or Separate Input/Output ............. 1-97
1-81 Buffering Devices Without OE"/RO" and With Separate Input/Output. ...................... 1-98
viii