Intel iAPX 86/88 User manual

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iAPX 86/88, 186/188 User's Manual
Hardware Reference
1985

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Chapter 1
8086/8088 CPU
Table of Contents
1.1 Introduction................................................................. 1-1
1.2 Component Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-1
1.2.1 Architectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-2
1.2.2 Software Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 1-12
1.3 Device
Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-42
1.3.1 Functional Description of All Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-43
1.3.2 Electrical Description of Pins
.................................................. 1-43
1.3.3 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 1-43
1.3.4 Minimum Mode System Overview/Description
.............. , ..................... 1-44
1.3.5 Maximum Mode System Overview/Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 1-52
1.3.6 General Design Considerations
................................................ 1-64
1.4 Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 1-64
1.4.1 Multiplexed Address and Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-64
1.4.2 Bus Cycle Definition
........................................................ 1-65
1.4.3 Address and Data Bus Concepts
............................................... 1-66
1.4.4 Memory and
110 Peripherals Interface ........................................... 1-71
1.4.5 System DeSign Alternatives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-92
1.4.6 Multiprocessor/Coprocessor Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 1-97
1.4.7 Interpreting The 8086/8088 Bus Timing Diagrams
................................. 1-98
1.4.8 Wait State Insertion
......................................................... 1-107
1.4.9 8086/8088 Instruction Sequence
............................................ , .. 1-109
1.5 Bus Exchange Mechanisms
.................................................... 1-110
1.5.1 Minimum Mode (HOLD/HLDA) ................................................ 1-110
1.5.2 Maximum Mode (RQ*/GT*)
................................................... 1-113
1.6 RESET
.................................................................... 1-118
1.6.1 Reset Bus Conditioning ...................................................... 1-118
1.6.2 Multiple Processor Considerations
............................................. 1-119
1.7 Interrupts
................................................................... 1-120
1
.7.1 Classes of Interrupts ........................................................ 1-120
1.7.2 Divide
Error-Type 0 ........................................................ 1-121
1.7.3 Single Step-Type 1 ........................................................ 1-121
1.7.4 Non-Maskable Interrupt-Type 2 ............................................... 1-121
1.7.5 One Byte Interrupt-Type 3 ................................................... 1-121
1.7.6 Interrupt on Overflow-Type 4 ........................................ ' ......... 1-121
1.7.7 User-Defined Software Interrupts .............................................. 1-122
1.7.8 User-Defined Hardware Interrupts
.............................................. 1-122
1.7.9 Interrupt Acknowledge
....................................................... 1-122
1.8 Support Components
......................................................... 1-125
1.8.1 8284A Clock Generator and Driver
............................................. 1-125
1.8.2 8288 Bus Controller
......................................................... 1-130
1.8.3 8289 Bus Arbiter
........................................................... 1-133
1.8.4 8259A Programmable Interrupt Controller
....................................... 1-134
1.8.5 8237A Programmable DMA Controller .......................................... 1-142
Chapter 2
80186/80188 CPU
2.1 Introduction-The High Integration Concept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
2.2 Component Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
2.2.1 Architectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
2.2.2 Software Overview .... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-4
2.3 Device Pin Definitions
......................................................... 2-12
2.3.1 Functional Description of All Signals ............................................ 2-12
2.3.2 Electrical Description of Pins
.................................................. 2-12
iii

TABLE OF CONTENTS
2.4 Operating Modes ............................................................ 2·12
2.4.1 8086/88·80186/188 Operating Mode Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·12
2.4.2 Queue Status Mode of Operation ............................................. , 2·12
2.4.3 Interrupt Controller Operating Modes ........................................... 2·19
2.5 Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·19
2.5.1 HALT Bus Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·23
2.5.2 8086/80186 Bus Operation Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·24
2.5.3 Multiplexed Address/Data Bus (186,188) ........................................ 2·29
2.5.4 Data Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·34
2.5.5 Memory and I/O Peripherals Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·34
2.5.6 Interpreting the 80186/80188 Bus Timing Diagrams ................................ 2·41
2.5.7 Wait State Generator ........................................................ 2·44
2.5.8 80186 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·46
2.6 Bus Exchange Mechanisms .................................................... 2·47
2.6.1 HOLD Response ........................................................... 2·47
2.6.2 HOLD/HLDA Timing and Bus Latency .......................................... 2·48
2.6.3 End of HOLD Timing ........................................................ 2·48
2.7 Interrupts ................................................................... 2·50
2.8 Support Circuits ............................................................. 2·51
2.8.1 Direct Memory Access (DMA) Unit ............................................. 2·51
2.8.2 Timer Unit ................................................................ 2·56
2.8.3 Interrupt Controller ......................................................... 2·59
2.8.4 Chip Select/Wait State Generation Unit ......................................... 2·74
2.8.5 Clock Generator/Reset/Ready ................................................. 2·79
Chapter 3
8087 Numeric Processor Extension
3.1 Introduction................................................................. 3·1
3.1.1 iAPX86,88,186,188Base ................................................... 3·1
3.1.2 8087 Mobility In Any iAPX 86, 88, 186 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3·2
3.2 Component Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3·3
3.2.1 Architecture Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. 3·3
3.2.2 Software Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3·7
3.3 Device Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3·8
3.4 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3·8
3.4.1 8087/8086(88) Interface ...................................................... 3·11
3.4.2 8087/80186(88) Interface ..................................................... 3·11
3.5 8086 (80186)/8087 Operation ................................................... 3·12
3.5.1 Decoding Escape Instructions ................................................. 3·12
3.5.2 Concurrent Execution of Host and Coprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3·13
3.5.3 Instruction Synchronization ................................................... 3·13
3.6 Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3·15
3.6.1 iAPX86/20 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3·15
3.6.2 iAPX186/20 Bus Operation ................................................... 3·15
3.7 Bus Exchange Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3·16
3.7.1 8087 RQ/GT Function ....................................................... 3·16
3.7.2 Delay Effects of the 8087 ..................................................... 3·17
3.7.3 Reducing 8087 Delay Effects ................................................. 3·19
3.8 Interrupts................................................................... 3·22
3.8.1 Recommended Interrupt Configurations ......................................... 3·22
Chapter 4
8089 Input/Output Processor
4.1 Introduction................................................................. 4·1
4.2 Component Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4·1
iv

TABLE OF CONTENTS
4.2.1 Architectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1
4.2.2 Software Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-3
4.3 Device Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 4-20
4.4 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-20
4.4.1 Interfacing the SOS9 to the SOS6 and S01S6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-24
4.4.2 lOP Initialization ............................................................ 4-26
4.4.3 Channel Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 4-27
4.4.4 Direct Memory Access Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 4-30
4.4.5 DMA Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-32
4.4.6 Peripheral Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-33
4.4.7 Status Lines
............................................................... 4-34
4.5 Bus Operation ............................................................... 4-34
4.6 Bus Exchange Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-36
4.6.1 Bus Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-37
4.6.2 Bus Load Limit. . . . . . . . . . . . . . . . . . . . . . . . .. .................................. 4-39
4.6.3 Bus Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 4-39
4.7 Interrupts
................................................................... 4-40
Chapter 5
80130 Operating System Firmware
5.1 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
5.2 S0130 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
5.3 Device Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
5.4 Operating System Primitives Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
5.5 Interfacing With the SOS6/SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
5.5.1 Programming The S0130 OSP's Onchip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
5.6 OSP Memory Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-11
5.7 Interrupt Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.7.1 Level-Triggered Mode ....................................................... 5-12
5.7.2 Edge-Triggered Mode
....................................................... 5-12
5.7.3 Local Interrupt Requests
..................................................... 5-13
5.7.4 Interrupt Sequence ......................................................... 5-13
5.S Timing ..................................................................... 5-13
Tables
1-1 Implicit Use of General Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-7
1-2 Logical Addresses Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 1-10
1-3 Data Transfer Instructions ......................................................... 1-13
1-4 Arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 1-14
1-5 Arithmetic Interpretation of S-Bit Numbers
............................................ 1-14
1-6 Bit Manipulation Instructions ....................................................... 1-15
1-7 String Instructions
............................................................... 1-15
1-S String Instruction Register and Flag Use .............................................. 1-15
1-9 Program Transfer Instructions ...................................................... 1-16
1-10 Interpretation of Conditional Transfers ................................................ 1-17
1-11 Processor Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-17
1-12
Key to Instruction Coding Formats .................................................. 1-22
1-13 Key to Flag Effects ............................................................... 1-23
1-14 Key to Operand Types ............................................................ 1-23
1-15 Effective Address Calculation Time .................................................. 1-24
1-16 Instruction Set Reference Data ..................................................... 1-24
1-17 Single-Bit Field Encoding ......................................................... 1-42
1-1S Mode (MOD) Field Encoding ....................................................... 1-42
1-19 REG (Register) Field Encoding ..................................................... 1-42
v

TABLE OF CONTENTS
1·20 Register/Memory Field Encoding ................................................... 1·43
1·21 Key to Machine Instruction Encoding and Decoding ..................................... 1-45
1·22 8086/88 Instruction Encoding ................................. : .................... 1·46
1·23 Machine Instruction Decoding Guide
................................................ 1·52
1·24 8086/8088 Device
Pin Descriptions .................................................. 1·61
1·25 D.C. Characteristics ............................................................. , 1·66
1·26
A.C. Timing Requirements for Minimum .............................................. 1·67
1·27
A.C. Timing Requirements for Maximum Complexity System .............................. 1·69
1·28 Minimum/Maximum Mode Pin Assignments
........................................... 1·71
1·29 Status Bit Decoding .............................................................. 1·71
1·30 Status Line Decoders ............................................................ 1·71
1·31
Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1·82
1·32 EPROM/ROM Parameters
......................................................... 1·82
1·33
Typical Static RAM Write Timing Parameters .......................................... 1·84
1·34 Cycle Dependent Write Parameters for
RAM Memories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1·84
1·35 Peripheral Compatibility Parameters
................................................. 1·89
1·36 Peripherals Cycle Dependent Parameter Requirements
.................................. 1·89
1·37 Compatible Peripherals for a 5 MHz 8086/88
.......................................... 1·90
1·38 Peripheral Requirements for Full Speed Operation with a 5MHz 8086/88
.................... 1·91
1·39 Queue Status Bit Decoding ........................................................ 1·99
1·40 Condition of 8086/88 Bus
and Output Signal Pins During Reset ........................... 1·119
1-41 8288 Outputs During Passive Modes ...................... , ......................... 1·119
1·42 Interrupt Processing Timing
....................................................... 1·121
1·43 Status Line Decode Chart .......... , .............................................. 1·131
1-44 8237A Internal Registers .......................................................... 1·146
1·45 Definition of Register Codes
....................................................... 1·147
2·1 Data Transfer Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·8
2·2 Arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 2·8
2·3 Arithmetic Interpretation of 8·Bit Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 2·9
2·4 Bit Manipulation Instructions
................................ , ........... , . . . . . . . . .. 2·9
2·5 String Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. . . . . . . . . . . .. 2·10
2.6 Program Transfer Instructions ............................................ , ......... 2·10
2·7 I
nterpretation of Conditional Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·11
2·8 Processor Control Instructions .................................................... , 2·11
2·9 Instruction Set Summary .......................................................... 2·13
2·10 80186/80188 Device
Pin Descriptions ................................................ 2·20
2·11 D.C. Characteristics ............................................................. , 2·23
2·12
A.C. Characteristics Timing Requirements ........................................ 0 ••• 2·24
2·13
A.C. Characteristics Master Interface Timing Responses. 0 ••••••••• 0 ••• 0 •••••• 0 ••••• 0 •• 0 0 2·25
2·14
A.C. Characteristics Chip·Select Timing Requirements. 0 0 0 • 0 0 0 0 0 0 0 0 0 0 0 00.0000000000. 0 00' 2·25
2·15
A.Co Characteristics CLKIN Requirements 0 0 •••• 0 0 ••• 0 0 •• 0 • 0 • 0 0 0 0 •••••• 0 •••• 0 • 0 ••• 0 ••• 2·26
2·16
A.C. Characteristics CLKOUT Requirements ........... 0 0 0 •••••••• 0 •••••••••••••• 0 •••• 2·26
2·17 80186 Queue
Status. 0 ••••• 0 •• 0 •••• 0 •• 0 0 ••••• 0 ••••• 0 • 0 •• 0 •••• 0 •••••• 0 •••••••••••• 2·28
2·18 80186 Status Line Interpretation 0
••••••••••••• 0 •••••• 0 • 0 •••• 0 • 0 ••• 0 ••• 0 ; ••••• 0 •••••• 2·32
2·19 Bank Selection Decoding
and Word Expansion .................... 0 •••••••••••••• 0 ••• 0 2·41
2·20 80186 Bus Signals ................. 0 ••• 0 •••• 0 •••• 0 •• 0 • 0 0 ••• 0 ••• 0 ••• 0 •• 0 • 0 •••••• o' 2·42
2·21 80186/188 Interrupt Vectors ............ 0 •••••••••••••• 0 •••• 0 •••••••••••••• 0 ••• 0 •• 0 0 2·50
2·22 DMA Request Inactive Timing. 0 • 0
•••• 0 0 ••••••• 0 0 • 0 • 0 •••••• 0 •• 0 ••••• 0 ••• 0 ••••••••• o' 2·57
2·23 Timer Control Block Format
.... 0 0 0 •• 0 0 •••••••• 0 ••••••••• 0 • 0 •• 0 ••••• 0 ••• 0 •••••••••• , 2·57
2·24 Internal Source Priority Level
........... 0 •••••• 0 •• 0 •••• 0 • 0 •••• 0 0 •••••• 0 • 0 ••••••• 0 •• 2·65
2·25 80186 Interrupt Vector
Types ......................... 0 •••••••••• 0 ••• 0 • 0 •••••• 0 • 0 0 •• 2·73
2·26
UMCS Programming Values .... 0 •••••••• 0 ••••• 0 ••• 0 • 0 •••• 0 ••••••••••••••••••••••• , 2·76
2·27
LMCS Programming Values . 0 •••••••••••••••••••••••• 0 ••••• 0 •••••••• 0 •••• 0 0 •• 0 • 0 • 0 2·77
2·28
MPCS Programming Values. 0 0 • 0 •• 0 •• 0 ••• 0 •••• 0 • 0 ••• 0 •••••••••••••••••• 0 •••••••••• 2·77
2·29 80186WAIT State Programming
.......... 0 •••••••••••••• 0 •••••••••••••••••••••••••• 2·78
2·30 80186 Initial Register State After RESET
............................................. 2·81
vi

TABLE OF CONTENTS
3-1 8087 Device Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-9
3-2 Worst Case Local Bus Request Wait Times In Clocks ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
4-1 Physical/Logical Bus Combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-2
4-2 Channel Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. 4-4
4-3
Instruction Set Reference Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-7
4-4
Operand Identifiers Definitions ..................................................... 4-14
4-5 Operand Type Definitions ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-14
4-6 Instruction Fetch Timings (Clock Periods) ............................................. 4-15
4-7 8089 Instruction Encoding ......................................................... 4-15
4-8 8089 Machine Instruction Decoding Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-21
4-9 R/B/P Field Encoding .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-21
4-10 WB Field Encoding .............................................................. 4-21
4-11 AA Field Encoding ............................................................... 4-22
4-12 MM Field Encoding .............................................................. 4-22
4-13 8089 DIP Pin Assignments ........................................................ 4-23
4-14 DMA Assembly Register Operation .................................................. 4-31
4-15 DMA Transfer Cycles ............................................................. 4-32
4-16 Status Signals SO-S2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-34
4-17 Status Signals S3-S6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-34
4-18 Data Bus Usage ................................................................. 4-37
4-19 Bus Cycle Decoding ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-37
4-20 Type of Cycle Decoding ......................................................... ;. 4-37
4-21 Bus Arbitration Requirements and Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-39
5-1 80130 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-4
5-2
OSP Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-6
5-3 Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .. 5-8
5-4
Mnemonic Codes for Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-9
5-5
Baud Rate Counter Values (16X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-11
Figures
1-1 Small 8088-Based System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-2
1-2 8086/8088/8089 Multiprocessing System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-3
1-3
8086 Simplified Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-4
1-4 8088 Simplified Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-5
1-5
Overlapped Instruction Fetch and Execution .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-6
1-6 General Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-7
1-7
Segment Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-7
1-8
Status Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-7
1-9
Segment Locations in Physical Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-8
1-10 Currently Addressable Segments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-8
1-11 Logical and Physical Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-9
1-12 Physical Address Generation ...................................................... 1-10
1-13 Dynamic Code Relocation ........................................................ , 1-11
1-14 Stack Operation ............................................... ; ................. 1-12
1-15 Reserved Memory and I/O Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-12
1-16 Flag Storage Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. 1-13
1-17 Memory Address Computation ..................................................... 1-19
1-18
Direct Addressing .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-19
1-19
Register Indirect Addressing ....................................................... 1-19
1-20 Based Addressing ............................................................... 1-19
1-21 Accessing A Structure With Based Addressing ......................................... 1-20
1-22 Indexed Addressing .............................................................. 1-20
1-23
Accessing an Array with Indexed Addressing .......................................... 1-20
1-24 Based Index Addressing ............................................... ; . . . . . . . . .. 1-20
1-25
Accessing a Stacked Array with Based Index Addressing ................................ 1-21
vii

TABLE OF CONTENTS
1-26 String Operand Addressing .......................... ; ......... , ..... : ; ........... , 1-21
1-27 110 Port Addressing ................................................. " ........... 1-21
1-28 Typical 8086/88 Machine Instruction Format. ...................... , ................... 1-41
1-29 Machine Instruction Encoding Matrix ................................................ 1-44
1-30 8086/8088 DIP Pin Assignments .................................................... 1-65
1-31 Minimum Mode Waveforms ........................................................ 1-72
1-32 Maximum Mode Waveforms ....................................................... 1-74
1-33 Elementary Maximum Mode System ................................................. 1-76
1-34 8086/88 Minimum Mode System ................................................ : ... 1-77
1-35 8086/88 Maximum Mode System ................................................... 1-77
1-36 8086/88 Queue Tracking Circuit .................................................... 1-78
1-37 8086/88 Lock Activity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-78
1-38 Decoding Memory and 110 RD" and WR" Commands ................................... 1-79
1-39 Linear Select for
110 . ............................................................. 1-79
1-40 Basic 8086/88 Bus Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-80
1-41 8086 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-80
1-42 Memory
Even and Odd Data Byte Transfers .......................................... , 1-81
1-43 Memory Even and Odd Data Word Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-82
1-44 8086/8088 Memory Organization ............................. , ..................... 1-82
1-45 Reserved Memory Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-82
1-46 8086/8088 Memory Array ......................................................... 1-83
1-47 EPROMIROM Bus Interface ....................................................... 1-83
1-48 Chip Select Generation for Devices Without Output Enables. . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 1-83
1-49 Chip Selection for Devices With Output Enables
....................................... 1-84
1-50 Sample Compatibility Analysis Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-84
1-51 5 MHz 8086 System USing an 8202 Dynamic RAM Controller ............................. 1-85
1-52 8202 Timing Information ............................................. , ............ 1-86
1-53 2118 Family Timing
.............................................................. 1-87
1-54 110 Device Chip Select Techniques .................................................. 1-88
1-55 16-bit to 8-bit Bus Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 1-88
1-56 Bipolar PROM Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-88
1-57 16-bit I/O Decode ................................................................ 1-88
1-58 8086 System Configurations
...................................................... , 1-90
1-59 Device Assignment ..................................... ; . . . . . . . . . . . . . . . . . . . . . . .. 1-91
1-60 110 Input Request Code Example ................................ , ................. , 1-92
1-61 Block Transfer to 16-bit 110 Using 8086/88 String Primitives ............................... 1-92
1-62 Block Transfer to 8-bit
110 USing 8086/88 String Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. 1-92
1-63 Code For Block Transfers
.......................................................... 1-93
1-64 Multiplexed Data Bus ............................................................. 1-93
1-65 Buffered Data
Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-93
1-66 Devices With Output Enable
on the Multiplexed Bus .................................... 1-93
1-67 Relationship of ALE to READ
...................................................... 1-94
1-68 Devices Without Output Enable
on the Multiplexed Bus .................................. 1-94
1-69 Access Time:
CS Gated with AO"twR" .............................................. 1-94
1-70
CE TO WR" Setup and Hold ...................................................... , 1-94
1-71 Bus Transceiver Control. .......................................................... 1-95
1-72 Devices With Output Enable on the System Bus ....................................... 1-95
1-73 CS"/Bus Driving Device Timing .................................................... 1-95
1-74 De-multiplexing Address and Data From the Processor Bus
.............................. 1-96
1-75 Multiplexed Bus With Local Address Oemultiplexing ................................... , 1-96
1-76 Fully Buffered System ...................................................•......... 1-97
1-77 ContrOlling System Transceivers with DEN and OT/R" ................................... 1-97
1-78 Buffering Devices with OE"/RO" ......................................... " ..... " .. 1-97
1-79 Buffering Devices Without OE"/RO" and With Common or Separate Input/Output. ............ 1-97
1-80 Buffering Devices Without OE"/RO" and With Common or Separate Input/Output ............. 1-97
1-81 Buffering Devices Without OE"/RO" and With Separate Input/Output. ...................... 1-98
viii

TABLE OF CONTENTS
1-82 8086 Family Multiprocessor System ................................................. 1-98
1-83 8086 Bus
Timing-Minimum Mode System ........................................... 1-100
1-84 8086 Bus Timing-Maximum Mode System Using 8288) ................................. 1-102
1-85 Max Mode 8086 with Master 8259A on the local Bus and Slave 8259A's on the System Bus ..... 1-107
1-86 Normally Ready System Inserting a Wait State ......................................... 1-108
1-87 Normally Not Ready System Avoiding aWait State ...................................... 1-108
1-88 Ready Inputs to the 8284 and Output to the 8086/88 .................................... 1-108
1-89 8284 With 8086/88 Ready Timing ................................................... 1-110
1-90 Using RDY1/RDY2 to Generate Ready
............................................... 1-110
1-91 Using AEN1'/AEN2' to Generate Ready ............................................. 1-110
1-92 Representative Instruction Execution Sequence ....................................... 1-111
1-93 Instruction loop Sequence ........................................................ 1-111
1-94 HOlD/HlDA Sequence Timing Diagram ............................................. 1-112
1-95 DMA Using the 8237-2
............................................................ 1-114
1-96 8086/88 Minimum System, 8257
on System Bus 16-Bit Transfers .......................... 1-115
1-97 HOlD/HlDA-to/from-RQ
'/GT' Conversion Circuit. ..................................... 1-116
1-98
HOlD/HlDA-to/from-RQ'/GT' Conversion Timing ..................................... 1-116
1-99 Request/Grant Sequence Timing
................................................... 1-117
1-100 Channel Transfer Delay Timing ..................................................... 1-117
1-101 Circuit to Translate HOLD into AEN Disable for Maximum Mode 8086/88 .................... 1-118
1-102 8086/88 Bus Conditioning on Reset Timing Diagram .................................... 1-119
1-103 Reset Disable for Max Mode 8086/8088 Bus Interface ................................... 1-119
1-104 Reset Disable for Max Mode 8086/88 Bus Interface in Multi-CPU System .................... 1-120
1-105 Interrupt Vector
Table ............................................................. 1-120
1-106 Interrupt Acknowledge Timing
...................................................... 1-123
1-107 NMI During Single Stepping and Normal Single Step Operation ........................... 1-125
1-108 NMI, INTR, Single Step and Divide Error Simultaneous Interrupts .......................... 1-126
1-109 8284A Clock Generator/Driver Block Diagram ......................................... 1-127
1-110 8086/88 Clock Waveform .......................................................... 1-127
1-111 Recommended Crystal Clock Configuration ........................................... 1-127
1-112 8284A Interfaced to an 8086/88
..................................................... 1-127
1-113 External Frequency for Multiple 8284's
............................................... 1-128
1-114 Oscillator to
ClK and ClK to PClK Timing Relationships ................................ 1-128
1-115 Synchronizing CSYNC With
EFI .................................................... 1-128
1-116 CSYNC Setup and Hold to
EFI ..................................................... 1-128
1-117
EFI From 8284A Oscillator ......................................................... 1-129
1-118 Synchronizing Multiple 8284As
..................................................... 1-129
1-119 Buffering the 8284
ClK Output ..................................................... 1-129
1-120 8086 and Coprocessor on the local Bus Share a Common 8284 ........................... 1-129
1-121 8284A Reset Circuit. ............................................................. 1-130
1-122 Constant Current Power Up Reset Circuit. ............................................ 1-130
1-123 8086/88 Reset and System Reset. .................................................. 1-130
1-124 8288 Bus Controller Block Diagram ................................................. 1-131
1-125 Status Line Activation and Termination ............................................... 1-132
1-126 Maximum and Minimum Mode Command Timing
.................•..................... 1-132
1-127 8289 Bus Arbiter Block Diagram
......................................... , .......... 1-133
1-128 Parallel Priority Resolving Technique
................................................ 1-135
1-129 Higher Priority Arbiter Obtaining the Bus From a
lower Priority Arbiter ...................... 1-135
1-130 Serial Priority Resolvi ng .......................................................... 1-136
1-131 Typical Medium Complexity CPU Circuit .............................................. 1-136
1-132 Min Mode 8086 with Master 8259A
on the local Bus and Slave 8259A's on the System Bus ..... 1-137
1-133 Max Mode 8086 with Master 8259A on the
local Bus and Slave 8259A's on the System Bus ..... 1-138
1-134 MCE Timing to Gate 8259A CAS Address onto the 8086
local Bus ......................... 1-138
1-135 Interrupt Vector Byte
............................................................. 1-139
1-136 Priority Structure Variations-Fully Nested Mode
....................................... 1-139
1-137 IR Triggering Timing Requirements
.................................................. 1-141
ix

TABLE OF CONTENTS
1-138 Cascaded 8259A's22 Interrupt Levels ....................................... , ....... 1-141
1-139 Cascade-Buffered Mode Example ................................................... 1-143
1-140 8237A DMA Controller Block Diagram
............................................... 1-143
1-141 Cascaded 8237As ............................................................... 1-145
1-142 Memory-To-Memory Transfer Timing
................................................. 1-146
1-143 Command Register
.............................................................. 1-147
1-144 Software Command Codes
........................................................ 1-147
1-145 Mode Register
.................................................................. 1-147
1-146 Request Register
................................................................ 1-147
1-147 Mask Bits
...................................................................... 1-148
1-148 Mask Register
.................................................................. 1-148
1-149 Status Register
................................................................. 1-148
2-1 80186/80188 Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-2
2-2 ENTER Instruction Stack
Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-7
2-3 Flag Store Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 2-8
2-4 80186/80188 DIP Pin Assignments
.................................................. 2-19
2-5 Major Cycle Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2-6 Generating Queue Status Information
................................................ 2-28
2-7 80186 and 8086 Queue Status Generation
............................................ 2-29
2-8 Example 80186 Buffered/Unbuffered Data Bus
........................................ 2"30
2-9 Read Cycle Timing .............................................................. 2-30
2-10 Generating
1/0 and Memory Read Signals ............................................ 2-31
2-11
Write Cycle Timing ............................................................... 2-31
2-12 Synthesizing Delayed Write from the 80186 ........................................... 2-32
2-13 Active-Inactive Status Transitions
................................................... 2-32
2-14 80186/8288 Bus Controller Interconnection
........................................... 2-32
2-15 Circuit Holding
LOCK' Active Until Ready Is Returned .................................. 2-33
2-16 80186/8288/8289 Interconnection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
2-17 Physical Memory BytelWord Addressing
.............................................. 2-35
2-18 80186/External Chip SelectlDevice Chip Select Generation
.............................. 2-35
2-19 Example 2764/80186 Interface
..................................................... 2-35
2-20 Example 2186/80186 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 2-37
2-21 Example 8203/DRAM/80186 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 2-38
2-22 8203/2164A-15 Access Time Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 2-39
2-23 8208 Dynamic RAM Controller Interfaces
............................................. 2-40
2-24 8208 Processor Address Interfaces
.................................................. 2-41
2-25 8208 Differentiated Reset Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-42
2-26 Single T-State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 2-42
2-27 Example 80186 Bus Cycle
......................................................... 2-43
2-28 80186 Address Generation Timing
.................................................. 2-43
2-29 Demultiplexing the 80186 Address Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 2-44
2-30 Valid/lnvalid ARDY Transitions
...................................................... 2-45
2-31 Asynchronous Ready Circuits for the 80186 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46
2-32 Valid SRDY Transitions on the 80186
............. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-46
2-33 Valid & Invalid Latch Input Transitions & Responses
..................................... 2-47
2-34 Signal FloatlHLDA Timing
......................................................... 2-47
2-35 80186 Idle Bus HOLD/HLDA Timing
............................................... " 2-48
2c36 HOLD/HLDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-49
2-37 End of HOLD Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 2-49
2-38 80186 CPUlDMA Channel Internal Model
............................................. 2-51
2-39 80186 DMA Register Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-52
2-40 DMA Control Register
.............. ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-52
2-41 Example DMA Transfer Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. 2-53
2-42 DMA Request Timing
............................................................. 2-55
2-43 DMA Request Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 2-55
2-44 DMA Acknowledge
Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-55
x

TABLE OF CONTENTS
2-45 Source &Destination Synchronized DMA Request Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-56
2-46 Timer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57
2-47
80186 Timer Out Signal ........................................................... 2-59
2-48 Example Timer Interface Code ..................................................... 2-60
2-49 80186 Real Time Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-64
2-50
80186 Baud Rate Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-64
2-51 80186 Event Counter ............................................................. 2-65
2-52
Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-65
2-53 iRMXTM 86 Interrupt Controller Interconnection ........................................ 2-66
2-54 80186 Interrupt Controller Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66
2-55
INTO/INT1 Control Register Formats ................................................. 2-66
2-56
INT2/INT3 Control Register Format .................................................. 2-67
2-57
80186 Interrupt Sequencing ....................................................... 2-67
2-58
Interrupt Controller Control Register ................................................. 2-68
2-59 80186 Non-Cascaded Interrupt Connection ........................................... 2-69
2-60 Cascade and Special Fully Nested Mode Interface ...................................... 2-69
2-61 80186/8258A Interrupt Cascading ................................................... 2-70
2-62 Example Interrupt Controller Interface Code ........................................... 2-71
2-63 80186 iRMXTM 86 Mode Interface ................................................... 2-72
2-64
80186/80130 iRMXTM 86 Mode Interface ............................................. 2-72
2-65
80186 iRMXTM 86 Mode Interrupt Acknowledge Timing .................................. 2-74
2-66
80186 Cascaded Interrupt Acknowledge Timing ........................................ 2-75
2-67 80186 Memory Areas and Chip Selects .............................................. 2-75
2-68
80186 Chip Select Control Registers ................................................. 2-76
2-69 UMCS Register ................................................................. 2-77
2-70 LMCS Register. ................................................................. 2-77
2-71 MPCS Register ................................................................. 2-77
2-72
MMCS Register ................................................................. 2-78
2-73 Clock In/Clock Out Timing ......................................................... 2-79
2-74 80186 Clock Generator Block Diagram ............................................... 2-79
2-75
Recommended iAPX 186 Crystal Configuration ........................................ 2-80
2-76
80186 Crystal Connection ......................................................... 2-80
2-77 80186 Clock Generator Reset ...................................................... 2-81
2-78 Coming out of Reset ............................................................. 2-81
3-1 Submit file Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-2
3-2
8087 Numeric Data Processor Pin Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-3
3-3
Typical iAPX 86/2X Family System Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-4
3-4 Typical iAPX 186/2X Family System Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-5
3-5 Test for the Existence of an 8087. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-6
3-6
iSBC 337 MULTIMODULE Mounting Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-6
3-7
8087 Numeric Processor Extension Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-6
3-8
Non-Memory Reference Escape Instruction Form ...................................... 3-7
3-9
Memory Reference Escape Instruction Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-8
3-10 ESCAPE Instructions Not Used By the 8087 NPX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-8
3-11 8087 NPX-8086/88 CPU System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-11
3-12 8087 NPX-80186/188 CPU System Configuration ..................................... 3-12
3-13
Synchronizing Execution With WAIT ................................................. 3-15
3-14
Three Processor System Bus Signal Connections ...................................... 3-17
3-15 iAPX 88/21 System Configuration ................................................... 3-18
3-16 iAPX 86/22 System . . . . . . . . . . . . . . . .
.. . . . . . . .. . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . 3-20
3-17 SMALLBLOCK-NP)LSAVE ..................................................... 3-21
3-18 SMALLBLOCK-NP)LRESTORE ................................................. 3-21
3-19 NP)LCLEAN Code Example ...................................................... 3-22
3-20
Inhibit/Enable 8087 Interrupts ...................................................... 3-23
4-1 8089 Simplified Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-2
4-2
Channel Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-3
xi

TABLE OF CONTENTS
4-3 Register Operands in MOV Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-5
4-4 Register Operands in Arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
4-5 Register Operands in Logical Instructions ............................... , . . . . . . . . . . . .. .4-6
4-6 Typical 8089 Machine Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
4-7 80891/0 Processor Pinout Diagram ................................................. 4-22
4-8 Command Communication Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 4-24
4-9 CPU/lOP Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. 4-24
4-10 iAPX 86/11,88/11 Configuration with 8089 in Local Mode
.......... " .................... 4-25
4-11 Typical 8089 Remote Configuration ................................................ " 4-26
4-12 RESET-CA Initialization Timing ..............................•...................... 4-27
4-13 Channel Attention Decoding Circuit
................................................. 4-28
4-14 Channel Command Word Encoding ................................................. 4-28
4-15 Channel Commands ............................................................. 4-29
4-16 Channel State Save Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . .. 4-30
4-17 Source Synchronized Transfer Cycle ..................... : ........................... 4-31
4-18 Destination Synchronized Transfer Cycle ............................................. 4-32
4-19 Read Bus Cycle (8-bit Bus) ........................................................ 4-35
4-20 Write Bus Cycle (16-bit Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-36
4-21 Wait State Timing ................................................................ 4-38
4-22 Program Status
Word ....................... . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. 4-40
5-1 80130 Simplified Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . .. 5-2
5-2 80130 OSP Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-3
5-3 OSP Typical Configuration With An 8086 .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . . . . . . . . .. 5-10
5-4 80130 OSP Timing Diagram ....................................................... 5-14
5-5 High-Speed Address Decoding Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. 5-15
xii

808618088 CPU 1

CHAPTER 1
8086/8088 CPU
1.1 INTRODUCTION
This chapter contains specific hardware design informa-
tion on the operation and functions
of INTEL's 8086/8088
Central Processing Units (CPUs). This information con-
sists of a component overview of the 8086/88 micropro-
cessors presenting architectural and software
considerations, individual device pin functional and elec-
trical signal definitions, a detailed description of the mini-
mum and maximum operating modes, detailed
descriptions of the operation of the address and data
buses, an explanation
of the protocols supported for local
bus transfers to other devices, and a detailed description
of interrupt operation. In addition, descriptions of the var-
ious 8086/88 family support circuits and their circuit
functions appear at the end
of the chapter. For more spe-
cific information of any of the 8086 family support cir-
cuits, refer to the Microsystem Components Handbook
(Order Number: 230843-002).
1.2 COMPONENT OVERVIEW
The 8086 and 8088 are closely related third-generation
microprocessors. Both CPU's contain a 20-bit address
bus (1 mega-byte of address space) and utilize an identical
instruction/function format. Differences between the two
devices consist essentially of their respective data bus
widths. The 8088 is designed with an 8-bit external data
path to memory and lIO, while the 8086 can transfer
16
bits at a time. In almost every other respect the processors
are identical; software written for one CPU will execute
on the other without alteration. Both chips are contained
in standard 40-pin dual in-line packages and operate from
a single +
5V power source. Except where expressly
noted, the descriptions contained in this chapter are appli-
cable to both microprocessors.
The 8086 and 8088 Microprocessors can be used for a
wide spectrum of microcomputer applications. This flexi-
bility
is one of their most outstanding characteristics. Sys-
tems can range from small uniprocessor minimal-memory
designs implemented with a
few chips (see Figure 1-1), to
multiprocessor systems with up to a megabyte of memory
(see Figure 1-2).
Both the 8086 and 8088 microprocessors use a combined,
or "time-multiplexed", address and data bus that permits
several of the device pins to serve dual functions. Some
microprocessor control pins also serve dual functions.
These pins are defined according to the strapping of a
single input pin (the MN/MX* pin). This feature provides
configuration of the CPU's in either "minimum mode" or
"maximum mode" circuits.
1-1
In the "minimum mode," the CPU is configured for
small, single-processor systems. In this configuration all
control signals are provided
by the CPU and the dual
function pins transfer signals directly to memory and
input/output devices.
In the "maximum mode" these same pins take on differ-
ent functions that are helpful in medium to large systems,
especially systems with multiple processors. An Intel
8288 Bus Controller is used to provide the control signal
outputs. This allows several of the device pins previously
delegated to these control functions to be redefined in or-
der to support multiprocessing applications. A detailed
description of this feature is presented later in the chapter.
The 8086 and 8088 Microprocessors are designed to op-
erate with the 8089 Input/Output Processor (lOP) and
other processors in multiprocessing and distributed proc-
essing systems. When used
in conjunction with one or
more 8089s, the 8086 and 8088 expand the applicability
of microprocessors into lIO-intensive data processing sys-
tems. Built-in coordinating signals and instructions, and
electrical compatibility with Intel's
MULTIBUS® shared
bus architecture, simplify and reduce the cost
of develop-
ing multiple-processor designs.
Both the 8086 and 8088 are substantually more powerful
than any microprocessor previously offered by Intel. Ac-
tual performance, of course, varies from application to
application, but comparisons to the industry standard
2-MHz 8080A are instructive. The 8088 is from four to
six times more powerful than the 8080A; the 8086 pro-
vides seven to ten times the 8080Xs performance.
The 8086's advantage over the 8088 is the result
of the
8086's 16-bit external data bus. In applications that ma-
nipulate 8-bit quantities extensively, or that are
execution-bound, the 8088 can approach to within 10%
of the 8086's processing throughput.
The improved performance of the 8086 and 8088
is ac-
complished by combining a l6-bit internal data path with
a pipelined architecture that allows instructions to be pre-
fetched during spare bus cycles. In addition, a compact
instruction format that enables more instructions to be
fetched in a given amount of time contributes to this high
performance.
Software for 8086 and 8088 systems does not need to be
written in assembly language. The CPUs are designed to
provide direct hardware support for programs written in
high-level languages such as Intel's PLlM-86. Most
high-level languages store variables in memory; the
8086/8088 symmetrical instruction set supports direct op-
eration on memory operands, including operands on the
210912·001

8086/8088 CPU
..
...
...
l..t
PORT A
..
.1..
I~
r
~
PORT B •
4 •
8155
RAM
I/O
~
PORTe
•
TIMER
•
-}ClOCK
______ TIMER
ADDRESS
•
I>
,.
~
PORT A •
8088
4ADDRESS/DATA
. ~
CPU
•
8755A
EPROM
I/O
~
~
PORTS
•
CONTROl. •
,...
r-- '--
I>
r
4 • 8185
8284
1K XB
CLOCK
RAM
GEN. •
'---
,..
... ""
... ""
Figure 1·1 Small8088·8ased System
stack. The hardware addressing modes provide efficient,
straightforward implementations
of based variables, ar-
rays, arrays
of structures and other high-level language
data constructs. A powerful set
of memory-to-memory
string operations is available for efficient character data
manipulation. Finally, routines with critical performance
requirements that cannot be met with PLlM-86
may be
written in ASM-86 (the 8086/8088 assembly language)
and linked with PLlM-86 code.
Although the 8086 and 8088 Microprocessors are totally
new designs, they make the most
of user's existing invest-
ments in systems designed around the 8080/8085 micro-
processors. Many
of the standard Intel memory,
peripheral control and communication chips are compati-
ble with the 8086 and the 8088. Software is developed in
the familiar Intellec Microcomputer Development System
environment, and most existing programs, whether writ-
ten in ASM-80 or PLlM-80, can be directly converted to
run
on the 8086 and 8088.
1.2.1 Architectural Overview
Both the 8086 and 8088 microprocessors incorporate two
separate processing units (see Figures
1-3 and 1-4). These
are the Execution Unit (EU) and the Bus Interface Unit
(BID). Both microprocessors contain identical EU's. In
1-2
the 8086 the BID incorporates a 16-bit data bus and a
6-byte instruction queue. In the 8088 the BID incorpo-
rates an 8-bit data bus and a 4-byte instruction queue.
The EUexecutes instructions and the BIU fetches instruc-
tions, reads operands and writes results. The two units can
operate independently
of one another and are able, under
most circumstances,
to extensively overlap instruction
fetch with execution. The result is that, in most cases, the
time normally required to fetch instructions "disappears"
because the EU executes instructions that have already
been fetched by the BID. Figure
1-5 illustrates this over-
lap and compares it with traditional microprocessor oper-
ation. In the example, overlapping reduces the elapsed
time required
to execute three instructions, and allows two
additional instructions to be prefetched as well.
In the 8086 CPU, when two or more bytes
of the 6-byte
instruction queue are empty and the EU does not require
the BIU to perform a bus cycle, the BIU executes instruc-
tion fetch cycles
to refill the queue. In the 8088 CPU,
when one byte of the 4-byte instruction queue is err-pty.
the BID executes an instruction fetCh cycle. Note that
since the 8086 CPU has a 16-bit data bus, it can access
two instruction object code bytes in a single bus cycle.
Since the 8088 CPU has an 8-bit data bus, it accesses one
instruction object code byte per bus cycle. If the EU
210912'()01

8086/8088 CPU
Figure 1·2 8086/8088/8089 Multiprocessing System
issues a request for bus access while the BIU is in the
process
of an instruction fetch bus cycle, the BIU comple-
tes the cycle before honoring the EU's request.
EXECUTION UNIT
The execution units (EU's) of the 8086 and 8088 are iden-
tical (see Figures 1-3 and 1-4). The EU is responsible for
the execution of all instructions, for providing data and
addresses to the BIU, and for manipulating the general
registers and the flag register. A 16-bit arithmetic/logic
unit (ALU)
in the EU maintains the CPU status and con-
trol flags, and manipulates the general registers and in-
struction operands. All registers and data paths
in the EU
are 16 bits wide for fast internal transfers.
The EU has
no connection to the system bus, the "outside
world." It obtains instructions from a queue maintained
by the BIU. Likewise, when an instruction requires ac-
cess to memory or to a peripheral device, the EU requests
the BIU to obtain and store the data. All addresses manip-
ulated by the EU are 16 bits wide. The BIU, however,
performs an address relocation that gives the EU access to
the full megabyte of memory space.
When the EU is ready to execute an instruction, it fetches
the instruction object code byte from the BIU's instruction
queue and then executes the instruction.
If the queue is
1-3
empty when the EU is ready to fetch an instruction byte,
the EU waits for the instruction byte to be fetched. If a
memory location or I/O port must be accessed during the
execution of an instruction, the EU requests the BIU to
perform the required bus cycle.
BUS INTERFACE UNIT
The 8086 and 8088 BIU's are functionally identical, but
are implemented differently
to match the structure and
performance characteristics
of their respective buses.
Data
is transferred between the CPU and memory or I/O
devices upon demand from the EU. The BIU executes all
external bus cycles. This unit consists
of the segment and
communications registers, the instruction pointer and the
instruction object code queue. The BIU combines seg-
ment and offset values
in a dedicated adder to derive
20-bit addresses, transfers data to and from the EU on the
ALU data bus and loads or "prefetches" instructions into
the queue. These "prefetched" instructions can then be
fetched by the EU with a minimum of wait.
During periods when the EU is busy executing instruc-
tions, the BIU "looks ahead" and fetches more instruc-
tions from memory. These instructions are stored in an
internal RAM array called the instruction stream queu-:.
The 8088 instruction queue holds up to four bytes of the
instruction stream, while the 8086 queue can store
up to
210912·001

8086/8088 CPU
GENERAL
REGISTERS
AH Al
Bl
CH Cl
SP
BP
SI
ALU DATA BUS
(1& BITSI
EXECUTION UNIT
(EUI
DATA BUS
CS
OS
INTERNAL
COMMUNICATIONS
REGISTERS
(16 BITS)
BUS INTERFACE UNIT
(Btu)
BUS
CONTROL
LOGIC
808&
BUS
Figure 1-3 8086 Simplified Functional Block Diagram
six instruction bytes. These queue sizes allow the BIU to
keep the EU supplied with prefetched instructions under
most conditions without monopolizing the system bus.
The 8088 BIU fetches another instruction byte whenever
one byte in its queue
is empty and there is no active re-
quest for bus access from the EU. The 8086 BIU operates
similarly except that it does not initiate a fetch until there
are two empty bytes in its queue. The 8086 BIU normally
obtains two instruction bytes per fetch.
If a program
transfer forces fetching from an odd address, the 8086
automatically reads one byte from the odd address and
then resumes fetching two-byte words from the subse-
quent even addresses.
In most circumstances the queues contain at least one byte
of the instruction stream and the EU does not have to wait
for instructions to be fetched. The instructions in the
queue are those stored in memory locations immediately
adjacent
to and higher than the instruction currently being
executed. That is, they are the next logical instructions so
long as execution proceeds serially.
If the EU executes an
instruction that transfers control
to another location, the
BIU resets the queue, fetches the instruction from the new
address, passes it immediately
to the EU, and then begins
refilling the queue from the new location. In addition, the
BIU suspends instruction fetching whenever the EU
1-4
requests a memory or 110 read or write (except that a
fetch already in progress is completed before executing
the EU's bus request).
GENERAL REGISTERS
Both CPU's have the same complement of eight 16-bit
general registers (see Figure 1-6). The general registers
are subdivided into two sets
of four registers each. These
are the data registers (sometimes called the H & L group
for "high" and "low"), and the pointer and index regis-
ters (sometimes called the P & I group).
The data registers are unique in that their upper (high) and
lower halves are separately addressable. This means that
each data register can be used interchangeably as a 16-bit
register, or as a two 8-bit registers. The other CPU regis-
ters are always accessed as 16-bit only. The data registers
can be·used without constraint in most arithmetic and
logic operations. In addition, some instructions use cere
tain registers implicitly (see Table 1-1), therefore allow-
ing compact yet powerful encoding.
The pointer and index registers can also be used in most
arithmetic and logic operations. All eight general regis-
ters fit the definition
of an "accumulator" as defined in
210912-001