Texas Instruments DM38x DaVinci User manual
DM38x DaVinci™
Digital Media Processor
High-Definition Video Processing Subsystem
(HDVPSS)
User's Guide
Literature Number: SPRUHI7A
December 2012–Revised June 2016
2SPRUHI7A–December 2012–Revised June 2016
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Contents
Contents
Preface....................................................................................................................................... 27
1 High-Definition Video Processing Subsystem (HDVPSS)......................................................... 28
1.1 Description of the Subsystem............................................................................................. 29
1.1.1 Overview............................................................................................................ 29
1.1.2 Acronyms and Definitions........................................................................................ 29
1.1.3 Features ............................................................................................................ 30
1.1.4 Functional Operation.............................................................................................. 35
1.1.5 HDVPSS Data Flow............................................................................................... 40
1.1.6 Example Data Flows.............................................................................................. 43
1.1.7 Interrupt Mapping.................................................................................................. 55
1.1.8 Clocking ............................................................................................................ 59
1.1.9 Reset................................................................................................................ 60
1.2 Internal Modules............................................................................................................ 61
1.2.1 Chroma Up-Sampler (CHR_US) ................................................................................ 61
1.2.2 Color Space Converter (CSC)................................................................................... 66
1.2.3 Compositor Module ............................................................................................... 72
1.2.4 Constrained Image Generator (CIG)............................................................................ 79
1.2.5 Graphics Module (GRPX)........................................................................................ 82
1.2.6 Standard-Definition Video Encoder (SD_VENC).............................................................. 94
1.2.7 High-Definition Video Encoder (HD_VENC).................................................................. 128
1.2.8 VIP Parser ........................................................................................................ 140
1.2.9 De-Interlacer (DEI) Module..................................................................................... 179
1.2.10 Noise Filter (NF) ................................................................................................ 185
1.2.11 Scaler (SC) ...................................................................................................... 191
1.2.12 Video Compositer (VCOMP) .................................................................................. 227
1.2.13 Video Port Direct Memory Access (VPDMA) ............................................................... 233
1.3 Registers................................................................................................................... 314
1.3.1 CHR_US Registers.............................................................................................. 316
1.3.2 CIG Registers .................................................................................................... 325
1.3.3 COMP Registers................................................................................................. 337
1.3.4 CSC Registers ................................................................................................... 344
1.3.5 DEI Registers..................................................................................................... 351
1.3.6 GRPX Registers ................................................................................................. 367
1.3.7 INTC_CLKC_CONTROL Registers ........................................................................... 368
1.3.8 VPDMA Registers ............................................................................................... 453
1.3.9 HD_VENC_D Registers......................................................................................... 753
1.3.10 NOISE_FILTER Registers..................................................................................... 782
1.3.11 SC_M Registers ................................................................................................ 793
1.3.12 SD_VENC Registers ........................................................................................... 817
1.3.13 VCOMP Registers.............................................................................................. 873
1.3.14 VIP_PARSER Registers....................................................................................... 887
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List of Figures
List of Figures
1-1. HDVPSS Detailed Block Diagram........................................................................................ 35
1-2. Primary Input Path (PRI) Detailed Block Diagram ..................................................................... 36
1-3. Auxiliary Input Path Detailed Block Diagram ........................................................................... 37
1-4. VIP Subsystem Detailed Block Diagram ................................................................................ 38
1-5. HDVPSS Dual Display (PIP) Data Flow................................................................................. 43
1-6. HDVPSS Tri Display Data Flow 1........................................................................................ 45
1-7. HDVPSS Tri Display Data Flow 2........................................................................................ 46
1-8. HDVPSS Tri Display Dual Transcode ................................................................................... 47
1-9. HDVPSS Tri Display Dual Transcode with Video Capture ........................................................... 49
1-10. HDVPSS Tri Display with Video Capture ............................................................................... 51
1-11. HDVPSS Tri Display with Video Capture and Noise Filter............................................................ 53
1-12. MMR Functionality ......................................................................................................... 55
1-13. Module to HDVPSS Interrupt Mapping Level 1 ........................................................................ 57
1-14. Module to HDVPSS Interrupt Mapping Level 2 ........................................................................ 58
1-15. Video Encoder Clock/Control Diagram.................................................................................. 59
1-16. 4:2:0 YCrCb Color Space with Chroma Left-aligned .................................................................. 61
1-17. Catmull-Rom Filter Definition ............................................................................................. 62
1-18. Definition of 'X'.............................................................................................................. 62
1-19. Anchor Pixels ............................................................................................................... 62
1-20. 4:2:0 Interlaced Scan ...................................................................................................... 63
1-21. Ideal 4:2:2 Chroma Upsampling for Interlaced Scan .................................................................. 63
1-22. Matrix Format............................................................................................................... 66
1-23. Conversion from RGB to YCbCr ......................................................................................... 67
1-24. Conversion from YCbCr to RGB ......................................................................................... 67
1-25. Conversion from RGB to YCbCr ......................................................................................... 67
1-26. Conversion from YCbCr to RGB ......................................................................................... 67
1-27. Conversion from RGB to YCbCr ......................................................................................... 69
1-28. Conversion from YCbCr to RGB ......................................................................................... 69
1-29. Conversion from RGB to YCbCr ......................................................................................... 70
1-30. Conversion from YCbCr to RGB ......................................................................................... 70
1-31. COMP Module Block Diagram............................................................................................ 73
1-32. Display Width and Height Parameters................................................................................... 74
1-33. Blender Diagram ........................................................................................................... 76
1-34. Blending and Reordering.................................................................................................. 77
1-35. Alpha Blender Block Diagram ............................................................................................ 78
1-36. CIG Block Diagram......................................................................................................... 80
1-37. GRPX Functional Block Diagram ........................................................................................ 83
1-38. GRPX Output ............................................................................................................... 83
1-39. Region Display Position and Gap Requirement Illustration........................................................... 87
1-40. VENC Block Diagram...................................................................................................... 95
1-41. Example of Multiple VENC Synchronization............................................................................ 96
1-42. Video Timing................................................................................................................ 96
1-43. Input I/F Horizontal Timing................................................................................................ 97
1-44. Input I/F Vertical Timing ................................................................................................... 98
1-45. Input Data Timing .......................................................................................................... 98
1-46. Interrupt Horizontal Timing................................................................................................ 99
1-47. Interrupt Vertical Timing................................................................................................... 99
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List of Figures
1-48. TVDETGP Horizontal Timing............................................................................................ 100
1-49. TVDETGP Vertical Timing............................................................................................... 100
1-50. SDTV Horizontal Timing ................................................................................................. 101
1-51. 525i Vertical Timing ...................................................................................................... 102
1-52. 625i Vertical Timing ...................................................................................................... 102
1-53. SDTV DAC Video Output Pipeline Delay (PXLR = 0) ............................................................... 103
1-54. SDTV DAC Video Output Pipeline Delay (PXLR = 1) ............................................................... 103
1-55. 262p (Non-Interlaced NTSC) Vertical Timing ......................................................................... 104
1-56. 312p (Non-Interlaced PAL) Vertical Timing ........................................................................... 104
1-57. Horizontal Blanking Shaping ............................................................................................ 105
1-58. Slave Mode Horizontal Timing .......................................................................................... 105
1-59. Interlaced Slave Vertical Timing (FMD = 0,1)......................................................................... 106
1-60. Interlaced Slave Vertical Timing (FMD = 2)........................................................................... 106
1-61. Interlaced Slave Vertical Timing (FMD = 3)........................................................................... 107
1-62. Field Detection Mode..................................................................................................... 108
1-63. Field Detection by VD Phase (FMD=3)................................................................................ 108
1-64. CVBS Video Amplitude .................................................................................................. 117
1-65. Limiter Configuration ..................................................................................................... 120
1-66. Sub-carrier Parameter Registers ....................................................................................... 121
1-67. WSS_Data Register Usage ............................................................................................. 122
1-68. WSS_Data Register Usage ............................................................................................. 122
1-69. VBI I/F Horizontal Timing ................................................................................................ 124
1-70. VBI I/F Vertical Timing ................................................................................................... 124
1-71. DAC I/F Logic ............................................................................................................. 127
1-72. HD VENC Block Diagram................................................................................................ 129
1-73. Vertical Sync Signals for OSD .......................................................................................... 130
1-74. Horizontal Sync-related Signal for OSD ............................................................................... 130
1-75. Video Data Interface Between OSD and Encoder ................................................................... 131
1-76. OSD Interface in Progressive Mode.................................................................................... 132
1-77. OSD Interface in Interlace Mode ....................................................................................... 133
1-78. Progressive Configuration of DVO ..................................................................................... 135
1-79. Interlace Configuration of DVO ......................................................................................... 136
1-80. Typical VBI Data Package............................................................................................... 137
1-81. NTSC Analog Video Waveform for One Horizontal Line ............................................................ 141
1-82. Digitized Video ............................................................................................................ 141
1-83. Code Word Embedded Video Format.................................................................................. 142
1-84. Digitized Video with F, V, and H Flags in EAV/SAV ................................................................. 142
1-85. Planar Buffer Storage Description...................................................................................... 143
1-86. 8b Interface Discrete Sync Pixel Multiplexing......................................................................... 144
1-87. 16b Interface Discrete Sync Pixel Multiplexing ....................................................................... 144
1-88. 24b Interface RGB or YUV444 Discrete Sync ........................................................................ 145
1-89. 24 Device Pins for Ports A and B....................................................................................... 145
1-90. Discrete Sync Signals.................................................................................................... 146
1-91. Type 1, First Horizontal Blanking Pixel ................................................................................ 147
1-92. Type 1, First Vertical Ancillary Data Pixel ............................................................................. 147
1-93. Type 1, Horizontal Blanking in Video Region ......................................................................... 148
1-94. Type 1, First Video Pixel................................................................................................. 148
1-95. 4-Pin Reduced ACTVID Signaling with Vertical Ancillary Data..................................................... 149
1-96. 4-Pin Reduced ACTVID Signaling with No Vertical Ancillary Data................................................. 149
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List of Figures
1-97. 4-Pin Reduced HSYNC Signaling with Vertical Ancillary Data ..................................................... 149
1-98. VSYNC Pre and Post Window.......................................................................................... 150
1-99. VSYNC Equivalence When Using Transition Window............................................................... 151
1-100. FID Registering When Using HSYNC.................................................................................. 152
1-101. FID Registering When Using ACTVID ................................................................................. 152
1-102. Field ID Determination By VSYNC Skew.............................................................................. 153
1-103. Example of 525-line FID Determination By VSYNC Skew .......................................................... 154
1-104. Horizontal Ancillary Data Packing When HSYNC Used as Sync Signal .......................................... 155
1-105. Interlaced Field Vertical Blanking Ancillary Data Storage........................................................... 155
1-106. Progressive Frame Vertical Blanking Ancillary Data Storage....................................................... 156
1-107. Embedded Sync Data Entry............................................................................................. 156
1-108. Code Word Format Example Followed by Video Data .............................................................. 157
1-109. Embedded Sync Packing................................................................................................ 159
1-110. RGB Frame Storage...................................................................................................... 160
1-111. 2-Way Multiplexing ....................................................................................................... 161
1-112. Example of 4-Way Multiplexing......................................................................................... 162
1-113. Example of Line Multiplexing............................................................................................ 162
1-114. 8-bit Line Mux Interface.................................................................................................. 163
1-115. 16-bit Line Mux Interface ................................................................................................ 163
1-116. BOP/EOP Definition of a Period........................................................................................ 164
1-117. Channel ID Inserted Into Horizontal Blanking......................................................................... 167
1-118. Vertical Ancillary Data Cropping Region............................................................................... 171
1-119. Active Video Region...................................................................................................... 171
1-120. Discrete Sync Interface Signals......................................................................................... 172
1-121. vsync and hblank Input Signals......................................................................................... 173
1-122. vsync and hsync Input Signals.......................................................................................... 173
1-123. vsync and actvid Input Signals.......................................................................................... 174
1-124. vblank and hsync Input Signals......................................................................................... 174
1-125. vblank and hblank Input Signals........................................................................................ 175
1-126. vblank and actvid Input Signals......................................................................................... 175
1-127. Line and Pixel Capture, vblank and hsync ............................................................................ 176
1-128. Line and Pixel Capture, hsync .......................................................................................... 176
1-129. Line and Pixel Capture, actvid .......................................................................................... 177
1-130. Block Diagram of Motion-Adaptive Deinterlacer...................................................................... 179
1-131. VPDMA Transfer Ports................................................................................................... 182
1-132. Auxiliary Data.............................................................................................................. 183
1-133. Noise Filter Architecture Block Diagram............................................................................... 186
1-134. Top-left Corner of a Tile After the Boundary Replication............................................................ 186
1-135. Motion versus Blending Factor Function .............................................................................. 187
1-136. α0versus totalFrame_noise function ................................................................................... 188
1-137. Hardware Implementation Block Diagram............................................................................. 188
1-138. Incomplete Boundary Tile Data Masking .............................................................................. 189
1-139. High Level Block Diagram............................................................................................... 191
1-140. SC Block Diagram ........................................................................................................ 192
1-141. Input Image Trimming.................................................................................................... 192
1-142. Filter Implementation and Parameter Description.................................................................... 193
1-143. Peaking Filter at fs/4 ..................................................................................................... 194
1-144. Vertical Scaler Block Diagram .......................................................................................... 194
1-145. Mixed 2-tap and 5-tap vertical interpolation........................................................................... 195
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1-146. Vertical Polyphase Scaler Block Diagram (SC)....................................................................... 195
1-147. Horizontal Scaler Block Diagram ....................................................................................... 197
1-148. Polyphase Filtering Example ........................................................................................... 198
1-149. Non-linear Scaling Example............................................................................................. 199
1-150. SRAM Layout for 7tap Coefficient...................................................................................... 202
1-151. SRAM Layout for 5tap Coefficient...................................................................................... 202
1-152. VPI Control I/F Coef Data Format (7tap) .............................................................................. 203
1-153. VPI Control I/F Coef Data Format (5tap) .............................................................................. 203
1-154. VPI Control I/F Coef Data Format (3tap) .............................................................................. 203
1-155. VPI Control I/F Memory Map (Write)................................................................................... 203
1-156. VPI Control I/F Memory Map (Read)................................................................................... 204
1-157. Main and Auxiliary Layers Over Background ......................................................................... 227
1-158. Overlap Region ........................................................................................................... 228
1-159. Cropping of Input Layers................................................................................................. 228
1-160. Single Plane Output ...................................................................................................... 229
1-161. Main Layer Only........................................................................................................... 230
1-162. Aux Layer Only............................................................................................................ 230
1-163. No Layer Enabled......................................................................................................... 230
1-164. Conditions Where Valid Configurations May Not Work in a System............................................... 231
1-165. Example.................................................................................................................... 232
1-166. Inbound Data Transfer Descriptor Format............................................................................. 236
1-167. Outbound Data Transfer Descriptor Format........................................................................... 236
1-168. HDVPSS Pressure and Priority Settings .............................................................................. 241
1-169. Block Diagram............................................................................................................. 253
1-170. Example Graphics Output ............................................................................................... 287
1-171. Y 4:4:4 (Data Type 0) .................................................................................................... 289
1-172. Y 4:2:2 (Data Type 1) .................................................................................................... 290
1-173. Y 4:2:0 (Data Type 2) .................................................................................................... 290
1-174. C 4:4:4 (Data Type 4).................................................................................................... 291
1-175. C 4:2:2 (Data Type 5).................................................................................................... 292
1-176. C 4:2:0 (Data Type 6).................................................................................................... 292
1-177. YC 4:2:2 (Data Type 7) .................................................................................................. 293
1-178. YC 4:4:4 (Data Type 8) .................................................................................................. 294
1-179. CY 4:2:2 (Data Type 23h) ............................................................................................... 295
1-180. Cb 4:4:4 (Data Type 14h)................................................................................................ 296
1-181. Cb 4:2:2 (Data Type 15h)................................................................................................ 296
1-182. Cb 4:2:0 (Data Type 16h)................................................................................................ 297
1-183. CbY 4:2:2 (Data Type 17h).............................................................................................. 297
1-184. YC 4:2:2 (Data Type 27h) ............................................................................................... 298
1-185. YC 4:2:2 (Data Type 37h) ............................................................................................... 298
1-186. RGB16-565 (Data Type 0)............................................................................................... 299
1-187. ARGB-1555 (Data Type 1) .............................................................................................. 300
1-188. ARGB-4444 (Data Type 2) .............................................................................................. 300
1-189. RGBA-5551 (Data Type 3) .............................................................................................. 301
1-190. RGBA-4444 (Data Type 4) .............................................................................................. 301
1-191. ARGB24-6666 (Data Type 5) ........................................................................................... 302
1-192. RGB24-888 (Data Type 6)............................................................................................... 302
1-193. ARGB32-8888 (Data Type 7) ........................................................................................... 303
1-194. RGBA24-6666 (Data Type 8) ........................................................................................... 304
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1-195. RGBA32-8888 (Data Type 9) ........................................................................................... 305
1-196. Bitmap-8 (Data Type 20h)............................................................................................... 306
1-197. Bitmap-4 Lower (Data Type 22h)....................................................................................... 306
1-198. Bitmap-4 Upper (Data Type 23h)....................................................................................... 307
1-199. Bitmap-2 Offset0 (Data Type 24h)...................................................................................... 307
1-200. Bitmap-2 Offset1 (Data Type 25h)...................................................................................... 308
1-201. Bitmap-2 Offset2 (Data Type 26h)...................................................................................... 308
1-202. Bitmap-2 Offset3 (Data Type 27h)...................................................................................... 309
1-203. Bitmap-1 Offset0 (Data Type 28h)...................................................................................... 309
1-204. Bitmap-1 Offset1 (Data Type 29h)...................................................................................... 310
1-205. Bitmap-1 Offset2 (Data Type 2Ah) ..................................................................................... 310
1-206. Bitmap-1 Offset3 (Data Type 2Bh) ..................................................................................... 311
1-207. Bitmap-1 Offset4 (Data Type 2Ch)..................................................................................... 311
1-208. Bitmap-1 Offset5 (Data Type 2Dh)..................................................................................... 312
1-209. Bitmap-1 Offset6 (Data Type 2Eh) ..................................................................................... 312
1-210. Bitmap-1 Offset7 (Data Type 2Fh) ..................................................................................... 313
1-211. CHR_US_reg0 Register ................................................................................................. 317
1-212. CHR_US_reg1 Register ................................................................................................. 318
1-213. CHR_US_reg2 Register ................................................................................................. 319
1-214. CHR_US_reg3 Register ................................................................................................. 320
1-215. CHR_US_reg4 Register ................................................................................................. 321
1-216. CHR_US_reg5 Register ................................................................................................. 322
1-217. CHR_US_reg6 Register ................................................................................................. 323
1-218. CHR_US_reg7 Register ................................................................................................. 324
1-219. CIG_reg0 Register........................................................................................................ 326
1-220. CIG_reg1 Register........................................................................................................ 327
1-221. CIG_reg2 Register........................................................................................................ 328
1-222. CIG_reg3 Register........................................................................................................ 329
1-223. CIG_reg4 Register........................................................................................................ 330
1-224. CIG_reg5 Register........................................................................................................ 331
1-225. CIG_reg6 Register........................................................................................................ 332
1-226. CIG_reg7 Register........................................................................................................ 333
1-227. CIG_reg8 Register........................................................................................................ 334
1-228. CIG_reg9 Register........................................................................................................ 335
1-229. CIG_reg10 Register ...................................................................................................... 336
1-230. COMP_status Register................................................................................................... 338
1-231. COMP_hdmi_settings Register ......................................................................................... 339
1-232. COMP_dvo2_settings Register ......................................................................................... 340
1-233. COMP_hdcomp_settings Register ..................................................................................... 341
1-234. COMP_sd_settings Register ............................................................................................ 342
1-235. COMP_back_color_settings Register.................................................................................. 343
1-236. CSC_csc00 Register ..................................................................................................... 345
1-237. CSC_csc01 Register ..................................................................................................... 346
1-238. CSC_csc02 Register ..................................................................................................... 347
1-239. CSC_csc03 Register ..................................................................................................... 348
1-240. CSC_csc04 Register ..................................................................................................... 349
1-241. CSC_csc05 Register ..................................................................................................... 350
1-242. dei_reg0 Register......................................................................................................... 352
1-243. dei_reg1 Register......................................................................................................... 353
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1-244. dei_reg2 Register......................................................................................................... 354
1-245. dei_reg3 Register......................................................................................................... 355
1-246. dei_reg4 Register......................................................................................................... 356
1-247. dei_reg5 Register......................................................................................................... 357
1-248. dei_reg6 Register......................................................................................................... 358
1-249. dei_reg7 Register......................................................................................................... 359
1-250. dei_reg8 Register......................................................................................................... 360
1-251. dei_reg9 Register......................................................................................................... 361
1-252. dei_reg10 Register ....................................................................................................... 362
1-253. dei_reg11 Register ....................................................................................................... 363
1-254. dei_reg12 Register ....................................................................................................... 364
1-255. dei_reg13 Register ....................................................................................................... 365
1-256. dei_reg14 Register ....................................................................................................... 366
1-257. pid Register................................................................................................................ 370
1-258. sysconfig Register ........................................................................................................ 371
1-259. intc_intr0_status_raw0 Register ........................................................................................ 372
1-260. intc_intr0_status_raw1 Register ........................................................................................ 374
1-261. intc_intr0_status_ena0 Register ........................................................................................ 376
1-262. intc_intr0_status_ena1 Register ........................................................................................ 378
1-263. intc_intr0_ena_set0 Register............................................................................................ 380
1-264. intc_intr0_ena_set1 Register............................................................................................ 382
1-265. intc_intr0_ena_clr0 Register............................................................................................. 384
1-266. intc_intr0_ena_clr1 Register............................................................................................. 386
1-267. intc_intr1_status_raw0 Register ........................................................................................ 388
1-268. intc_intr1_status_raw1 Register ........................................................................................ 390
1-269. intc_intr1_status_ena0 Register ........................................................................................ 392
1-270. intc_intr1_status_ena1 Register ........................................................................................ 394
1-271. intc_intr1_ena_set0 Register............................................................................................ 396
1-272. intc_intr1_ena_set1 Register............................................................................................ 398
1-273. intc_intr1_ena_clr0 Register............................................................................................. 400
1-274. intc_intr1_ena_clr1 Register............................................................................................. 402
1-275. intc_intr2_status_raw0 Register ........................................................................................ 404
1-276. intc_intr2_status_raw1 Register ........................................................................................ 406
1-277. intc_intr2_status_ena0 Register ........................................................................................ 408
1-278. intc_intr2_status_ena1 Register ........................................................................................ 410
1-279. intc_intr2_ena_set0 Register............................................................................................ 412
1-280. intc_intr2_ena_set1 Register............................................................................................ 414
1-281. intc_intr2_ena_clr0 Register............................................................................................. 416
1-282. intc_intr2_ena_clr1 Register............................................................................................. 418
1-283. intc_intr3_status_raw0 Register ........................................................................................ 420
1-284. intc_intr3_status_raw1 Register ........................................................................................ 422
1-285. intc_intr3_status_ena0 Register ........................................................................................ 424
1-286. intc_intr3_status_ena1 Register ........................................................................................ 426
1-287. intc_intr3_ena_set0 Register............................................................................................ 428
1-288. intc_intr3_ena_set1 Register............................................................................................ 430
1-289. intc_intr3_ena_clr0 Register............................................................................................. 432
1-290. intc_intr3_ena_clr1 Register............................................................................................. 434
1-291. intc_eoi Register .......................................................................................................... 436
1-292. clkc_clken Register....................................................................................................... 437
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1-293. clkc_rst Register .......................................................................................................... 439
1-294. clkc_dps Register......................................................................................................... 441
1-295. clkc_vip1dps Register.................................................................................................... 443
1-296. clkc_vip2dps Register.................................................................................................... 446
1-297. clkc_venc_clksel Register ............................................................................................... 449
1-298. clkc_venc_ena Register.................................................................................................. 450
1-299. clkc_range_map Register................................................................................................ 451
1-300. clkc_underflow Register.................................................................................................. 452
1-301. VPDMA_pid Register..................................................................................................... 456
1-302. VPDMA_list_addr Register .............................................................................................. 457
1-303. VPDMA_list_attr Register................................................................................................ 458
1-304. VPDMA_list_stat_sync Register ........................................................................................ 459
1-305. VPDMA_vpi_ctl_address Register...................................................................................... 461
1-306. VPDMA_vpi_ctl_data Register.......................................................................................... 462
1-307. VPDMA_bg_rgb Register................................................................................................ 463
1-308. VPDMA_bg_yuv Register................................................................................................ 464
1-309. VPDMA_descriptor_top Register ....................................................................................... 465
1-310. VPDMA_descriptor_bottom Register................................................................................... 466
1-311. VPDMA_current_descriptor Register................................................................................... 467
1-312. VPDMA_descriptor_status_control Register .......................................................................... 468
1-313. VPDMA_int0_channel0_int_stat Register ............................................................................. 469
1-314. VPDMA_int0_channel0_int_mask Register ........................................................................... 472
1-315. VPDMA_int0_channel1_int_stat Register ............................................................................. 474
1-316. VPDMA_int0_channel1_int_mask Register ........................................................................... 478
1-317. VPDMA_int0_channel2_int_stat Register ............................................................................. 481
1-318. VPDMA_int0_channel2_int_mask Register ........................................................................... 485
1-319. VPDMA_int0_channel3_int_stat Register ............................................................................. 488
1-320. VPDMA_int0_channel3_int_mask Register ........................................................................... 492
1-321. VPDMA_int0_channel4_int_stat Register ............................................................................. 495
1-322. VPDMA_int0_channel4_int_mask Register ........................................................................... 499
1-323. VPDMA_int0_channel5_int_stat Register ............................................................................. 502
1-324. VPDMA_int0_channel5_int_mask Register ........................................................................... 506
1-325. VPDMA_int0_channel6_int_stat Register ............................................................................. 509
1-326. VPDMA_int0_channel6_int_mask Register ........................................................................... 510
1-327. VPDMA_int0_client0_int_stat Register ................................................................................ 511
1-328. VPDMA_int0_client0_int_mask Register .............................................................................. 514
1-329. VPDMA_int0_client1_int_stat Register ................................................................................ 516
1-330. VPDMA_int0_client1_int_mask Register .............................................................................. 520
1-331. VPDMA_int0_list0_int_stat Register ................................................................................... 523
1-332. VPDMA_int0_list0_int_mask Register ................................................................................. 526
1-333. VPDMA_int1_channel0_int_stat Register ............................................................................. 529
1-334. VPDMA_int1_channel0_int_mask Register ........................................................................... 532
1-335. VPDMA_int1_channel1_int_stat Register ............................................................................. 534
1-336. VPDMA_int1_channel1_int_mask Register ........................................................................... 538
1-337. VPDMA_int1_channel2_int_stat Register ............................................................................. 541
1-338. VPDMA_int1_channel2_int_mask Register ........................................................................... 545
1-339. VPDMA_int1_channel3_int_stat Register ............................................................................. 548
1-340. VPDMA_int1_channel3_int_mask Register ........................................................................... 552
1-341. VPDMA_int1_channel4_int_stat Register ............................................................................. 555
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List of Figures
1-342. VPDMA_int1_channel4_int_mask Register ........................................................................... 559
1-343. VPDMA_int1_channel5_int_stat Register ............................................................................. 562
1-344. VPDMA_int1_channel5_int_mask Register ........................................................................... 566
1-345. VPDMA_int1_channel6_int_stat Register ............................................................................. 569
1-346. VPDMA_int1_channel6_int_mask Register ........................................................................... 570
1-347. VPDMA_int1_client0_int_stat Register ................................................................................ 571
1-348. VPDMA_int1_client0_int_mask Register .............................................................................. 574
1-349. VPDMA_int1_client1_int_stat Register ................................................................................ 576
1-350. VPDMA_int1_client1_int_mask Register .............................................................................. 580
1-351. VPDMA_int1_list0_int_stat Register ................................................................................... 583
1-352. VPDMA_int1_list0_int_mask Register ................................................................................. 586
1-353. VPDMA_int2_channel0_int_stat Register ............................................................................. 589
1-354. VPDMA_int2_channel0_int_mask Register ........................................................................... 592
1-355. VPDMA_int2_channel1_int_stat Register ............................................................................. 594
1-356. VPDMA_int2_channel1_int_mask Register ........................................................................... 598
1-357. VPDMA_int2_channel2_int_stat Register ............................................................................. 601
1-358. VPDMA_int2_channel2_int_mask Register ........................................................................... 605
1-359. VPDMA_int2_channel3_int_stat Register ............................................................................. 608
1-360. VPDMA_int2_channel3_int_mask Register ........................................................................... 612
1-361. VPDMA_int2_channel4_int_stat Register ............................................................................. 615
1-362. VPDMA_int2_channel4_int_mask Register ........................................................................... 619
1-363. VPDMA_int2_channel5_int_stat Register ............................................................................. 622
1-364. VPDMA_int2_channel5_int_mask Register ........................................................................... 626
1-365. VPDMA_int2_channel6_int_stat Register ............................................................................. 629
1-366. VPDMA_int2_channel6_int_mask Register ........................................................................... 630
1-367. VPDMA_int2_client0_int_stat Register ................................................................................ 631
1-368. VPDMA_int2_client0_int_mask Register .............................................................................. 634
1-369. VPDMA_int2_client1_int_stat Register ................................................................................ 636
1-370. VPDMA_int2_client1_int_mask Register .............................................................................. 640
1-371. VPDMA_int2_list0_int_stat Register ................................................................................... 643
1-372. VPDMA_int2_list0_int_mask Register ................................................................................. 646
1-373. VPDMA_int3_channel0_int_stat Register ............................................................................. 649
1-374. VPDMA_int3_channel0_int_mask Register ........................................................................... 652
1-375. VPDMA_int3_channel1_int_stat Register ............................................................................. 654
1-376. VPDMA_int3_channel1_int_mask Register ........................................................................... 658
1-377. VPDMA_int3_channel2_int_stat Register ............................................................................. 661
1-378. VPDMA_int3_channel2_int_mask Register ........................................................................... 665
1-379. VPDMA_int3_channel3_int_stat Register ............................................................................. 668
1-380. VPDMA_int3_channel3_int_mask Register ........................................................................... 672
1-381. VPDMA_int3_channel4_int_stat Register ............................................................................. 675
1-382. VPDMA_int3_channel4_int_mask Register ........................................................................... 679
1-383. VPDMA_int3_channel5_int_stat Register ............................................................................. 682
1-384. VPDMA_int3_channel5_int_mask Register ........................................................................... 686
1-385. VPDMA_int3_channel6_int_stat Register ............................................................................. 689
1-386. VPDMA_int3_channel6_int_mask Register ........................................................................... 690
1-387. VPDMA_int3_client0_int_stat Register ................................................................................ 691
1-388. VPDMA_int3_client0_int_mask Register .............................................................................. 694
1-389. VPDMA_int3_client1_int_stat Register ................................................................................ 696
1-390. VPDMA_int3_client1_int_mask Register .............................................................................. 700
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SPRUHI7A–December 2012–Revised June 2016
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List of Figures
1-391. VPDMA_int3_list0_int_stat Register ................................................................................... 703
1-392. VPDMA_int3_list0_int_mask Register ................................................................................. 706
1-393. VPDMA_dei_hq_1_chroma_cstat Register............................................................................ 709
1-394. VPDMA_dei_hq_1_luma_cstat Register............................................................................... 710
1-395. VPDMA_dei_hq_2_luma_cstat Register............................................................................... 711
1-396. VPDMA_dei_hq_2_chroma_cstat Register............................................................................ 712
1-397. VPDMA_dei_hq_3_luma_cstat Register............................................................................... 713
1-398. VPDMA_dei_hq_3_chroma_cstat Register............................................................................ 714
1-399. VPDMA_dei_hq_mv_in_cstat Register ................................................................................ 715
1-400. VPDMA_dei_hq_mv_out_cstat Register............................................................................... 716
1-401. VPDMA_dei_sc_out_cstat Register.................................................................................... 717
1-402. VPDMA_pip_wrbk_cstat Register ...................................................................................... 718
1-403. VPDMA_sc_in_chroma_cstat Register ................................................................................ 719
1-404. VPDMA_sc_in_luma_cstat Register ................................................................................... 720
1-405. VPDMA_sc_out_cstat Register ......................................................................................... 721
1-406. VPDMA_comp_wrbk_cstat Register ................................................................................... 722
1-407. VPDMA_grpx1_data_cstat Register.................................................................................... 723
1-408. VPDMA_grpx2_data_cstat Register.................................................................................... 724
1-409. VPDMA_grpx3_data_cstat Register.................................................................................... 725
1-410. VPDMA_vip1_lo_y_cstat Register...................................................................................... 726
1-411. VPDMA_vip1_lo_uv_cstat Register .................................................................................... 727
1-412. VPDMA_vip1_up_y_cstat Register..................................................................................... 728
1-413. VPDMA_vip1_up_uv_cstat Register ................................................................................... 729
1-414. VPDMA_vip2_lo_y_cstat Register...................................................................................... 730
1-415. VPDMA_vip2_lo_uv_cstat Register .................................................................................... 731
1-416. VPDMA_vip2_up_y_cstat Register..................................................................................... 732
1-417. VPDMA_vip2_up_uv_cstat Register ................................................................................... 733
1-418. VPDMA_grpx1_st_cstat Register....................................................................................... 734
1-419. VPDMA_grpx2_st_cstat Register....................................................................................... 735
1-420. VPDMA_grpx3_st_cstat Register....................................................................................... 736
1-421. VPDMA_nf_422_in_cstat Register ..................................................................................... 737
1-422. VPDMA_nf_420_y_in_cstat Register .................................................................................. 738
1-423. VPDMA_nf_420_uv_in_cstat Register................................................................................. 739
1-424. VPDMA_nf_420_y_out_cstat Register................................................................................. 740
1-425. VPDMA_nf_420_uv_out_cstat Register ............................................................................... 741
1-426. VPDMA_vbi_sdvenc_cstat Register.................................................................................... 742
1-427. VPDMA_vpi_ctl_cstat Register ......................................................................................... 743
1-428. VPDMA_hdmi_wrbk_out_cstat Register............................................................................... 744
1-429. VPDMA_trans1_chroma_cstat Register ............................................................................... 745
1-430. VPDMA_trans1_luma_cstat Register .................................................................................. 746
1-431. VPDMA_trans2_chroma_cstat Register ............................................................................... 747
1-432. VPDMA_trans2_luma_cstat Register .................................................................................. 748
1-433. VPDMA_vip1_anc_a_cstat Register ................................................................................... 749
1-434. VPDMA_vip1_anc_b_cstat Register ................................................................................... 750
1-435. VPDMA_vip2_anc_a_cstat Register ................................................................................... 751
1-436. VPDMA_vip2_anc_b_cstat Register ................................................................................... 752
1-437. HD_VENC_D_cfg0 Register ............................................................................................ 754
1-438. HD_VENC_D_cfg1 Register ............................................................................................ 756
1-439. HD_VENC_D_cfg2 Register ............................................................................................ 757
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List of Figures
1-440. HD_VENC_D_cfg3 Register ............................................................................................ 758
1-441. HD_VENC_D_cfg4 Register ............................................................................................ 759
1-442. HD_VENC_D_cfg5 Register ............................................................................................ 760
1-443. HD_VENC_D_cfg6 Register ............................................................................................ 761
1-444. HD_VENC_D_cfg7 Register ............................................................................................ 762
1-445. HD_VENC_D_cfg8 Register ............................................................................................ 763
1-446. HD_VENC_D_cfg9 Register ............................................................................................ 764
1-447. HD_VENC_D_cfg10 Register........................................................................................... 765
1-448. HD_VENC_D_cfg11 Register........................................................................................... 766
1-449. HD_VENC_D_cfg12 Register........................................................................................... 767
1-450. HD_VENC_D_cfg13 Register........................................................................................... 768
1-451. HD_VENC_D_cfg14 Register........................................................................................... 769
1-452. HD_VENC_D_cfg15 Register........................................................................................... 770
1-453. HD_VENC_D_cfg16 Register........................................................................................... 771
1-454. HD_VENC_D_cfg17 Register........................................................................................... 772
1-455. HD_VENC_D_cfg18 Register........................................................................................... 773
1-456. HD_VENC_D_cfg19 Register........................................................................................... 774
1-457. HD_VENC_D_cfg20 Register........................................................................................... 775
1-458. HD_VENC_D_cfg21 Register........................................................................................... 776
1-459. HD_VENC_D_cfg22 Register........................................................................................... 777
1-460. HD_VENC_D_cfg23 Register........................................................................................... 778
1-461. HD_VENC_D_cfg24 Register........................................................................................... 779
1-462. HD_VENC_D_cfg25 Register........................................................................................... 780
1-463. HD_VEND_D_GAMMA_LUT Register................................................................................. 781
1-464. nf_reg0 Register .......................................................................................................... 783
1-465. nf_reg1 Register .......................................................................................................... 784
1-466. nf_reg2 Register .......................................................................................................... 785
1-467. nf_reg3 Register .......................................................................................................... 786
1-468. nf_reg4 Register .......................................................................................................... 787
1-469. nf_reg5 Register .......................................................................................................... 788
1-470. nf_reg6 Register .......................................................................................................... 789
1-471. nf_reg7 Register .......................................................................................................... 790
1-472. nf_reg8 Register .......................................................................................................... 791
1-473. nf_reg9 Register .......................................................................................................... 792
1-474. SC_M_cfg_sc0 Register ................................................................................................. 794
1-475. SC_M_cfg_sc1 Register ................................................................................................. 796
1-476. SC_M_cfg_sc2 Register ................................................................................................. 797
1-477. SC_M_cfg_sc3 Register ................................................................................................. 798
1-478. SC_M_cfg_sc4 Register ................................................................................................. 799
1-479. SC_M_cfg_sc5 Register ................................................................................................. 800
1-480. SC_M_cfg_sc6 Register ................................................................................................. 801
1-481. SC_M_cfg_sc8 Register ................................................................................................. 802
1-482. SC_M_cfg_sc9 Register ................................................................................................. 803
1-483. SC_M_cfg_sc10 Register................................................................................................ 804
1-484. SC_M_cfg_sc11 Register................................................................................................ 805
1-485. SC_M_cfg_sc12 Register................................................................................................ 806
1-486. SC_M_cfg_sc13 Register................................................................................................ 807
1-487. SC_M_cfg_sc17 Register................................................................................................ 808
1-488. SC_M_cfg_sc18 Register................................................................................................ 809
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SPRUHI7A–December 2012–Revised June 2016
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List of Figures
1-489. SC_M_cfg_sc19 Register................................................................................................ 810
1-490. SC_M_cfg_sc20 Register................................................................................................ 811
1-491. SC_M_cfg_sc21 Register................................................................................................ 812
1-492. SC_M_cfg_sc22 Register................................................................................................ 813
1-493. SC_M_cfg_sc23 Register................................................................................................ 814
1-494. SC_M_cfg_sc24 Register................................................................................................ 815
1-495. SC_M_cfg_sc25 Register................................................................................................ 816
1-496. SD_VENC_pid Register.................................................................................................. 819
1-497. SD_VENC_vmod Register............................................................................................... 820
1-498. SD_VENC_slave Register............................................................................................... 821
1-499. SD_VENC_size Register ................................................................................................ 822
1-500. SD_VENC_pol Register.................................................................................................. 823
1-501. SD_VENC_dtvs0 Register............................................................................................... 824
1-502. SD_VENC_dtvs1 Register............................................................................................... 825
1-503. SD_VENC_dtvs2 Register............................................................................................... 826
1-504. SD_VENC_dtvs3 Register............................................................................................... 827
1-505. SD_VENC_dtvs4 Register............................................................................................... 828
1-506. SD_VENC_dtvs5 Register............................................................................................... 829
1-507. SD_VENC_dtvs6 Register............................................................................................... 830
1-508. SD_VENC_dtvs7 Register............................................................................................... 831
1-509. SD_VENC_tvdetgp0 Register........................................................................................... 832
1-510. SD_VENC_tvdetgp1 Register........................................................................................... 833
1-511. SD_VENC_irq0 Register................................................................................................. 834
1-512. SD_VENC_estat Register ............................................................................................... 835
1-513. SD_VENC_ectl Register................................................................................................. 836
1-514. SD_VENC_etmg0 Register.............................................................................................. 837
1-515. SD_VENC_etmg1 Register.............................................................................................. 838
1-516. SD_VENC_etmg2 Register.............................................................................................. 839
1-517. SD_VENC_etmg3 Register.............................................................................................. 840
1-518. SD_VENC_etmg4 Register.............................................................................................. 841
1-519. SD_VENC_cvbs0 Register .............................................................................................. 842
1-520. SD_VENC_cvbs1 Register .............................................................................................. 843
1-521. SD_VENC_ccsc0 Register .............................................................................................. 844
1-522. SD_VENC_ccsc1 Register .............................................................................................. 845
1-523. SD_VENC_ccsc2 Register .............................................................................................. 846
1-524. SD_VENC_ccsc3 Register .............................................................................................. 847
1-525. SD_VENC_ccsc4 Register .............................................................................................. 848
1-526. SD_VENC_ccsc5 Register .............................................................................................. 849
1-527. SD_VENC_ccsc6 Register .............................................................................................. 850
1-528. SD_VENC_ccsc7 Register .............................................................................................. 851
1-529. SD_VENC_ccsc8 Register .............................................................................................. 852
1-530. SD_VENC_cygclp Register.............................................................................................. 853
1-531. SD_VENC_cubclp Register ............................................................................................. 854
1-532. SD_VENC_cvrclp Register .............................................................................................. 855
1-533. SD_VENC_ylpf0 Register ............................................................................................... 856
1-534. SD_VENC_ylpf1 Register ............................................................................................... 857
1-535. SD_VENC_clpf0 Register ............................................................................................... 858
1-536. SD_VENC_clpf1 Register ............................................................................................... 859
1-537. SD_VENC_upf0 Register................................................................................................ 860
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14 SPRUHI7A–December 2012–Revised June 2016
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List of Figures
1-538. SD_VENC_upf1 Register................................................................................................ 861
1-539. SD_VENC_l21ctl Register............................................................................................... 862
1-540. SD_VENC_l21do Register............................................................................................... 863
1-541. SD_VENC_l21de Register............................................................................................... 864
1-542. SD_VENC_wss Register................................................................................................. 865
1-543. SD_VENC_scctl0 Register .............................................................................................. 866
1-544. SD_VENC_scctl1 Register .............................................................................................. 867
1-545. SD_VENC_dacsel Register ............................................................................................. 868
1-546. SD_VENC_dupf0 Register .............................................................................................. 869
1-547. SD_VENC_dupf1 Register .............................................................................................. 870
1-548. SD_VENC_dactst Register.............................................................................................. 871
1-549. SD_VENC_vtest Register ............................................................................................... 872
1-550. VCOMP_reg0 Register................................................................................................... 874
1-551. VCOMP_reg1 Register................................................................................................... 875
1-552. VCOMP_reg2 Register................................................................................................... 876
1-553. VCOMP_reg3 Register................................................................................................... 877
1-554. VCOMP_reg4 Register................................................................................................... 878
1-555. VCOMP_reg5 Register................................................................................................... 879
1-556. VCOMP_reg6 Register................................................................................................... 880
1-557. VCOMP_reg7 Register................................................................................................... 881
1-558. VCOMP_reg8 Register................................................................................................... 882
1-559. VCOMP_reg9 Register................................................................................................... 883
1-560. VCOMP_reg10 Register ................................................................................................. 884
1-561. VCOMP_reg11 Register ................................................................................................. 885
1-562. VCOMP_reg12 Register ................................................................................................. 886
1-563. VIP_PARSER_main Register ........................................................................................... 889
1-564. VIP_PARSER_port_a Register ......................................................................................... 890
1-565. VIP_PARSER_xtra_port_a Register ................................................................................... 893
1-566. VIP_PARSER_port_b Register ......................................................................................... 894
1-567. VIP_PARSER_xtra_port_b Register ................................................................................... 897
1-568. VIP_PARSER_fiq_mask Register ...................................................................................... 898
1-569. VIP_PARSER_fiq_clear Register....................................................................................... 900
1-570. VIP_PARSER_fiq_status Register ..................................................................................... 902
1-571. VIP_PARSER_output_port_a_src_fid Register....................................................................... 904
1-572. VIP_PARSER_output_port_a_enc_fid Register ...................................................................... 906
1-573. VIP_PARSER_output_port_b_src_fid Register....................................................................... 908
1-574. VIP_PARSER_output_port_b_enc_fid Register ...................................................................... 910
1-575. VIP_PARSER_output_port_a_src0_size Register ................................................................... 912
1-576. VIP_PARSER_output_port_a_src1_size Register ................................................................... 913
1-577. VIP_PARSER_output_port_a_src2_size Register ................................................................... 914
1-578. VIP_PARSER_output_port_a_src3_size Register ................................................................... 915
1-579. VIP_PARSER_output_port_a_src4_size Register ................................................................... 916
1-580. VIP_PARSER_output_port_a_src5_size Register ................................................................... 917
1-581. VIP_PARSER_output_port_a_src6_size Register ................................................................... 918
1-582. VIP_PARSER_output_port_a_src7_size Register ................................................................... 919
1-583. VIP_PARSER_output_port_a_src8_size Register ................................................................... 920
1-584. VIP_PARSER_output_port_a_src9_size Register ................................................................... 921
1-585. VIP_PARSER_output_port_a_src10_size Register.................................................................. 922
1-586. VIP_PARSER_output_port_a_src11_size Register.................................................................. 923
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SPRUHI7A–December 2012–Revised June 2016
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List of Figures
1-587. VIP_PARSER_output_port_a_src12_size Register.................................................................. 924
1-588. VIP_PARSER_output_port_a_src13_size Register.................................................................. 925
1-589. VIP_PARSER_output_port_a_src14_size Register.................................................................. 926
1-590. VIP_PARSER_output_port_a_src15_size Register.................................................................. 927
1-591. VIP_PARSER_output_port_b_src0_size Register ................................................................... 928
1-592. VIP_PARSER_output_port_b_src1_size Register ................................................................... 929
1-593. VIP_PARSER_output_port_b_src2_size Register ................................................................... 930
1-594. VIP_PARSER_output_port_b_src3_size Register ................................................................... 931
1-595. VIP_PARSER_output_port_b_src4_size Register ................................................................... 932
1-596. VIP_PARSER_output_port_b_src5_size Register ................................................................... 933
1-597. VIP_PARSER_output_port_b_src6_size Register ................................................................... 934
1-598. VIP_PARSER_output_port_b_src7_size Register ................................................................... 935
1-599. VIP_PARSER_output_port_b_src8_size Register ................................................................... 936
1-600. VIP_PARSER_output_port_b_src9_size Register ................................................................... 937
1-601. VIP_PARSER_output_port_b_src10_size Register.................................................................. 938
1-602. VIP_PARSER_output_port_b_src11_size Register.................................................................. 939
1-603. VIP_PARSER_output_port_b_src12_size Register.................................................................. 940
1-604. VIP_PARSER_output_port_b_src13_size Register.................................................................. 941
1-605. VIP_PARSER_output_port_b_src14_size Register.................................................................. 942
1-606. VIP_PARSER_output_port_b_src15_size Register.................................................................. 943
1-607. VIP_PARSER_port_a_vdet_vec Register............................................................................. 944
1-608. VIP_PARSER_port_b_vdet_vec Register............................................................................. 945
1-609. VIP_PARSER_xtra2_port_a Register.................................................................................. 946
1-610. VIP_PARSER_xtra3_port_a Register.................................................................................. 947
1-611. VIP_PARSER_xtra4_port_a Register.................................................................................. 948
1-612. VIP_PARSER_xtra5_port_a Register.................................................................................. 949
1-613. VIP_PARSER_xtra2_port_b Register.................................................................................. 950
1-614. VIP_PARSER_xtra3_port_b Register.................................................................................. 951
1-615. VIP_PARSER_xtra4_port_b Register.................................................................................. 952
1-616. VIP_PARSER_xtra5_port_b Register.................................................................................. 953
1-617. VIP_PARSER_xtra6_port_a Register.................................................................................. 954
1-618. VIP_PARSER_xtra7_port_b Register.................................................................................. 955
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List of Tables
List of Tables
1-1. HDVPSS Acronyms........................................................................................................ 29
1-2. HDVPSS Data Format..................................................................................................... 29
1-3. VPDMA Client Number.................................................................................................... 36
1-4. HDVPSS Mux Select Register 1 ......................................................................................... 44
1-5. HDVPSS Mux Select Register 2 ......................................................................................... 45
1-6. HDVPSS Mux Select Register 3 ......................................................................................... 46
1-7. HDVPSS Mux Select Register 4 ......................................................................................... 48
1-8. HDVPSS Mux Select Register 5 ......................................................................................... 50
1-9. HDVPSS Mux Select Register 6 ......................................................................................... 52
1-10. HDVPSS Mux Select Register 7 ......................................................................................... 54
1-11. HDVPSS Interrupts ........................................................................................................ 55
1-12. VPDMA Modes of Operation.............................................................................................. 64
1-13. Quantized Coefficients of HDTV Application with Video Data Range............................................... 68
1-14. Quantized Coefficients of HDTV Application with Graphics Data Range........................................... 68
1-15. Quantized Coefficients of SDTV Application with Video Data Range............................................... 71
1-16. Quantized Coefficients of SDTV Application with Graphics Data Range........................................... 71
1-17. Input Layers and Associated Blenders.................................................................................. 73
1-18. Frame Configuration Attribute (Configuration descriptor payload word 0-3) ....................................... 84
1-19. Region Configuration Attribute (Inbound data descriptor word 4-7)................................................. 85
1-20. Blending and Transparency Configuration.............................................................................. 88
1-21. Region Scaler Configuration Attributes 1 ............................................................................... 89
1-22. Region Scaler Attributes 2 ................................................................................................ 89
1-23. Region Scaler Attributes 3 ................................................................................................ 89
1-24. Region Scaler Attributes 4 ................................................................................................ 90
1-25. Region Scaler Attributes 5 ................................................................................................ 90
1-26. Region Scaler Attributes 6 ................................................................................................ 91
1-27. Region Scaler Attributes 7 ................................................................................................ 91
1-28. Region Scaler Attributes 8 ................................................................................................ 91
1-29. Region Scaler Attributes 9 ................................................................................................ 92
1-30. Region Scaler Attributes 10............................................................................................... 92
1-31. Region Scaler Attributes 11............................................................................................... 93
1-32. TV Formats.................................................................................................................. 97
1-33. SDTV Horizontal Timing Parameter.................................................................................... 101
1-34. Non-Interlaced Format ................................................................................................... 104
1-35. Color Bar Table .......................................................................................................... 109
1-36. 2× Interpolation Filter Coefficients...................................................................................... 109
1-37. Color Systems............................................................................................................. 110
1-38. Luma LPF Filter Coefficient ............................................................................................. 116
1-39. Chroma LPF Filter Coefficient........................................................................................... 116
1-40. Sub-carrier Increment Parameters ..................................................................................... 118
1-41. Typical Register Setting for Various Video Standards............................................................... 125
1-42. DAC Output Select ....................................................................................................... 126
1-43. DAC 2x Oversampling Filter Coefficients.............................................................................. 126
1-44. Display Ports and VENC Names ....................................................................................... 128
1-45. OSD Interface Signals ................................................................................................... 129
1-46. DVO Formats.............................................................................................................. 134
1-47. Definition of SAV and EAV words ...................................................................................... 134
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17
SPRUHI7A–December 2012–Revised June 2016
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List of Tables
1-48. JEIDA and VESA Format................................................................................................ 137
1-49. Programmable Capacity of First Line Encoder ....................................................................... 138
1-50. Programmable Capacity of Second Line Encoder ................................................................... 138
1-51. Gamma Correction LUT.................................................................................................. 138
1-52. Memory Map Addresses for Configuration Register and LUT Memories ......................................... 139
1-53. Valid Input Port Configurations ......................................................................................... 146
1-54. Polarity Table for FID Determination By VSYNC Skew.............................................................. 153
1-55. Fourth Byte of EAV/SAV Code Word .................................................................................. 157
1-56. Error Correction Matrix................................................................................................... 158
1-57. Multiplexing Configurations and Pixel Clock Rates .................................................................. 161
1-58. Split Line Table............................................................................................................ 164
1-59. Meta Data Layout......................................................................................................... 164
1-60. TI Line Mux Mode Channel ID Remapping............................................................................ 165
1-61. Channel ID Embedded in EAV/SAV.................................................................................... 166
1-62. Valid Embedded Sync Mux Mode and Data Bus Width Combinations............................................ 167
1-63. Register Layout ........................................................................................................... 167
1-64. VIP Parser Interrupts..................................................................................................... 168
1-65. Module Interrupts ......................................................................................................... 184
1-66. NF Configuration for Each Basic Mode................................................................................ 190
1-67. Vertical Scaler Configuration Parameters ............................................................................. 196
1-68. Horizontal Scaler Related Parameter Configuration ................................................................. 200
1-69. Horizontal Decimation Selection........................................................................................ 200
1-70. Horizontal Polyphase Filter Related Parameter Configuration...................................................... 201
1-71. Coefficient Data Files..................................................................................................... 205
1-72. Memory Databus Write Order........................................................................................... 235
1-73. Data Packet Descriptor Word 0 Field Descriptions................................................................... 237
1-74. Data Packet Descriptor Word 1 Field Description.................................................................... 239
1-75. Data Packet Descriptor Word 2 Field Descriptions................................................................... 240
1-76. Data Packet Descriptor Word 3 Field Descriptions................................................................... 240
1-77. Priority Bit Fields.......................................................................................................... 242
1-78. Data Packet Descriptor Word 4 Inbound Data Field Descriptions ................................................. 242
1-79. Data Packet Descriptor Word 4 Outbound Data Field Descriptions ............................................... 243
1-80. Data Packet Descriptor Word 5 Inbound Data Field Descriptions ................................................. 244
1-81. Data Packet Descriptor Word 5 Outbound Data Field Descriptions ............................................... 244
1-82. Configuration Descriptor Header Word0 Field Descriptions ........................................................ 245
1-83. Configuration Descriptor Header Word1 Field Descriptions ........................................................ 245
1-84. Configuration Descriptor Header Word2 Field Descriptions ........................................................ 245
1-85. Configuration Descriptor Header Word3 Field Descriptions ........................................................ 246
1-86. Address Data Block Format Field Descriptions....................................................................... 246
1-87. Destination Field Description............................................................................................ 247
1-88. Control Descriptor Header Description................................................................................. 247
1-89. Control Descriptor Types Summary.................................................................................... 248
1-90. Sync on Client Field Descriptions (Word - 1) ......................................................................... 248
1-91. Sync on Client Field Descriptions (Word - 3) ......................................................................... 249
1-92. Sync on List Field Descriptions (Word - 3)............................................................................ 249
1-93. Sync on External Event Field Descriptions (Word - 3)............................................................... 249
1-94. Sync on Channel Field Descriptions (Word - 3) ...................................................................... 250
1-95. Change Client Interrupt Field Descriptions (Word - 1)............................................................... 250
1-96. Change Client Interrupt Field Descriptions (Word - 2)............................................................... 250
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18 SPRUHI7A–December 2012–Revised June 2016
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List of Tables
1-97. Change Client Interrupt Field Descriptions (Word - 3)............................................................... 250
1-98. Send Interrupt Field Descriptions (Word - 3).......................................................................... 251
1-99. Reload List Field Descriptions (Word - 0) ............................................................................. 251
1-100. Reload List Field Descriptions (Word - 1) ............................................................................. 251
1-101. Reload List Field Descriptions (Word - 3) ............................................................................. 251
1-102. Abort Channel Field Descriptions (Word - 3).......................................................................... 252
1-103. Toggle LM Field Field Descriptions (Word - 2) ....................................................................... 252
1-104. Toggle LM Field Field Descriptions (Word - 3) ....................................................................... 252
1-105. VPDMA Channels ........................................................................................................ 254
1-106. VPDMA Client Buffering ................................................................................................. 261
1-107. HDVPSS Client Functionality............................................................................................ 264
1-108. HDVPSS Interrupt from VPDMA........................................................................................ 265
1-109. HDVPSS Interrupt Sources.............................................................................................. 266
1-110. Graphics Region Descriptor Format.................................................................................... 283
1-111. Frame Configuration Descriptor Format ............................................................................... 284
1-112. Frame with Resizer Configuration Descriptor Format................................................................ 284
1-113. Example Graphics List Description..................................................................................... 288
1-114. HDVPSS Module Instances ............................................................................................. 314
1-115. HDVPSS Registers....................................................................................................... 315
1-116. CHR_US REGISTERS................................................................................................... 316
1-117. CHR_US_reg0 Register Field Descriptions ........................................................................... 317
1-118. CHR_US_reg1 Register Field Descriptions ........................................................................... 318
1-119. CHR_US_reg2 Register Field Descriptions ........................................................................... 319
1-120. CHR_US_reg3 Register Field Descriptions ........................................................................... 320
1-121. CHR_US_reg4 Register Field Descriptions ........................................................................... 321
1-122. CHR_US_reg5 Register Field Descriptions ........................................................................... 322
1-123. CHR_US_reg6 Register Field Descriptions ........................................................................... 323
1-124. CHR_US_reg7 Register Field Descriptions ........................................................................... 324
1-125. CIG REGISTERS......................................................................................................... 325
1-126. CIG_reg0 Register Field Descriptions ................................................................................. 326
1-127. CIG_reg1 Register Field Descriptions ................................................................................. 327
1-128. CIG_reg2 Register Field Descriptions ................................................................................. 328
1-129. CIG_reg3 Register Field Descriptions ................................................................................. 329
1-130. CIG_reg4 Register Field Descriptions ................................................................................. 330
1-131. CIG_reg5 Register Field Descriptions ................................................................................. 331
1-132. CIG_reg6 Register Field Descriptions ................................................................................. 332
1-133. CIG_reg7 Register Field Descriptions ................................................................................. 333
1-134. CIG_reg8 Register Field Descriptions ................................................................................. 334
1-135. CIG_reg9 Register Field Descriptions ................................................................................. 335
1-136. CIG_reg10 Register Field Descriptions................................................................................ 336
1-137. COMP REGISTERS...................................................................................................... 337
1-138. COMP_status Register Field Descriptions ............................................................................ 338
1-139. COMP_hdmi_settings Register Field Descriptions................................................................... 339
1-140. COMP_dvo2_settings Register Field Descriptions................................................................... 340
1-141. COMP_hdcomp_settings Register Field Descriptions ............................................................... 341
1-142. COMP_sd_settings Register Field Descriptions...................................................................... 342
1-143. COMP_back_color_settings Register Field Descriptions............................................................ 343
1-144. CSC REGISTERS ........................................................................................................ 344
1-145. CSC_csc00 Register Field Descriptions............................................................................... 345
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SPRUHI7A–December 2012–Revised June 2016
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List of Tables
1-146. CSC_csc01 Register Field Descriptions............................................................................... 346
1-147. CSC_csc02 Register Field Descriptions............................................................................... 347
1-148. CSC_csc03 Register Field Descriptions............................................................................... 348
1-149. CSC_csc04 Register Field Descriptions............................................................................... 349
1-150. CSC_csc05 Register Field Descriptions............................................................................... 350
1-151. DEI REGISTERS ......................................................................................................... 351
1-152. dei_reg0 Register Field Descriptions................................................................................... 352
1-153. dei_reg1 Register Field Descriptions................................................................................... 353
1-154. dei_reg2 Register Field Descriptions................................................................................... 354
1-155. dei_reg3 Register Field Descriptions................................................................................... 355
1-156. dei_reg4 Register Field Descriptions................................................................................... 356
1-157. dei_reg5 Register Field Descriptions................................................................................... 357
1-158. dei_reg6 Register Field Descriptions................................................................................... 358
1-159. dei_reg7 Register Field Descriptions................................................................................... 359
1-160. dei_reg8 Register Field Descriptions................................................................................... 360
1-161. dei_reg9 Register Field Descriptions................................................................................... 361
1-162. dei_reg10 Register Field Descriptions ................................................................................. 362
1-163. dei_reg11 Register Field Descriptions ................................................................................. 363
1-164. dei_reg12 Register Field Descriptions ................................................................................. 364
1-165. dei_reg13 Register Field Descriptions ................................................................................. 365
1-166. dei_reg14 Register Field Descriptions ................................................................................. 366
1-167. INTC_CLKC_CONTROL REGISTERS ................................................................................ 368
1-168. pid Register Field Descriptions.......................................................................................... 370
1-169. sysconfig Register Field Descriptions.................................................................................. 371
1-170. intc_intr0_status_raw0 Register Field Descriptions .................................................................. 372
1-171. intc_intr0_status_raw1 Register Field Descriptions .................................................................. 374
1-172. intc_intr0_status_ena0 Register Field Descriptions.................................................................. 376
1-173. intc_intr0_status_ena1 Register Field Descriptions.................................................................. 378
1-174. intc_intr0_ena_set0 Register Field Descriptions...................................................................... 380
1-175. intc_intr0_ena_set1 Register Field Descriptions...................................................................... 382
1-176. intc_intr0_ena_clr0 Register Field Descriptions ...................................................................... 384
1-177. intc_intr0_ena_clr1 Register Field Descriptions ...................................................................... 386
1-178. intc_intr1_status_raw0 Register Field Descriptions .................................................................. 388
1-179. intc_intr1_status_raw1 Register Field Descriptions .................................................................. 390
1-180. intc_intr1_status_ena0 Register Field Descriptions.................................................................. 392
1-181. intc_intr1_status_ena1 Register Field Descriptions.................................................................. 394
1-182. intc_intr1_ena_set0 Register Field Descriptions...................................................................... 396
1-183. intc_intr1_ena_set1 Register Field Descriptions...................................................................... 398
1-184. intc_intr1_ena_clr0 Register Field Descriptions ...................................................................... 400
1-185. intc_intr1_ena_clr1 Register Field Descriptions ...................................................................... 402
1-186. intc_intr2_status_raw0 Register Field Descriptions .................................................................. 404
1-187. intc_intr2_status_raw1 Register Field Descriptions .................................................................. 406
1-188. intc_intr2_status_ena0 Register Field Descriptions.................................................................. 408
1-189. intc_intr2_status_ena1 Register Field Descriptions.................................................................. 410
1-190. intc_intr2_ena_set0 Register Field Descriptions...................................................................... 412
1-191. intc_intr2_ena_set1 Register Field Descriptions...................................................................... 414
1-192. intc_intr2_ena_clr0 Register Field Descriptions ...................................................................... 416
1-193. intc_intr2_ena_clr1 Register Field Descriptions ...................................................................... 418
1-194. intc_intr3_status_raw0 Register Field Descriptions .................................................................. 420
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List of Tables
1-195. intc_intr3_status_raw1 Register Field Descriptions .................................................................. 422
1-196. intc_intr3_status_ena0 Register Field Descriptions.................................................................. 424
1-197. intc_intr3_status_ena1 Register Field Descriptions.................................................................. 426
1-198. intc_intr3_ena_set0 Register Field Descriptions...................................................................... 428
1-199. intc_intr3_ena_set1 Register Field Descriptions...................................................................... 430
1-200. intc_intr3_ena_clr0 Register Field Descriptions ...................................................................... 432
1-201. intc_intr3_ena_clr1 Register Field Descriptions ...................................................................... 434
1-202. intc_eoi Register Field Descriptions.................................................................................... 436
1-203. clkc_clken Register Field Descriptions................................................................................. 437
1-204. clkc_rst Register Field Descriptions.................................................................................... 439
1-205. clkc_dps Register Field Descriptions................................................................................... 441
1-206. clkc_vip1dps Register Field Descriptions.............................................................................. 443
1-207. clkc_vip2dps Register Field Descriptions.............................................................................. 446
1-208. clkc_venc_clksel Register Field Descriptions......................................................................... 449
1-209. clkc_venc_ena Register Field Descriptions ........................................................................... 450
1-210. clkc_range_map Register Field Descriptions ......................................................................... 451
1-211. clkc_underflow Register Field Descriptions ........................................................................... 452
1-212. VPDMA REGISTERS .................................................................................................... 453
1-213. VPDMA_pid Register Field Descriptions .............................................................................. 456
1-214. VPDMA_list_addr Register Field Descriptions........................................................................ 457
1-215. VPDMA_list_attr Register Field Descriptions ......................................................................... 458
1-216. VPDMA_list_stat_sync Register Field Descriptions.................................................................. 459
1-217. VPDMA_vpi_ctl_address Register Field Descriptions ............................................................... 461
1-218. VPDMA_vpi_ctl_data Register Field Descriptions.................................................................... 462
1-219. VPDMA_bg_rgb Register Field Descriptions.......................................................................... 463
1-220. VPDMA_bg_yuv Register Field Descriptions ......................................................................... 464
1-221. VPDMA_descriptor_top Register Field Descriptions................................................................. 465
1-222. VPDMA_descriptor_bottom Register Field Descriptions ............................................................ 466
1-223. VPDMA_current_descriptor Register Field Descriptions ............................................................ 467
1-224. VPDMA_descriptor_status_control Register Field Descriptions.................................................... 468
1-225. VPDMA_int0_channel0_int_stat Register Field Descriptions....................................................... 469
1-226. VPDMA_int0_channel0_int_mask Register Field Descriptions..................................................... 472
1-227. VPDMA_int0_channel1_int_stat Register Field Descriptions....................................................... 474
1-228. VPDMA_int0_channel1_int_mask Register Field Descriptions..................................................... 478
1-229. VPDMA_int0_channel2_int_stat Register Field Descriptions....................................................... 481
1-230. VPDMA_int0_channel2_int_mask Register Field Descriptions..................................................... 485
1-231. VPDMA_int0_channel3_int_stat Register Field Descriptions....................................................... 488
1-232. VPDMA_int0_channel3_int_mask Register Field Descriptions..................................................... 492
1-233. VPDMA_int0_channel4_int_stat Register Field Descriptions....................................................... 495
1-234. VPDMA_int0_channel4_int_mask Register Field Descriptions..................................................... 499
1-235. VPDMA_int0_channel5_int_stat Register Field Descriptions....................................................... 502
1-236. VPDMA_int0_channel5_int_mask Register Field Descriptions..................................................... 506
1-237. VPDMA_int0_channel6_int_stat Register Field Descriptions....................................................... 509
1-238. VPDMA_int0_channel6_int_mask Register Field Descriptions..................................................... 510
1-239. VPDMA_int0_client0_int_stat Register Field Descriptions .......................................................... 511
1-240. VPDMA_int0_client0_int_mask Register Field Descriptions ........................................................ 514
1-241. VPDMA_int0_client1_int_stat Register Field Descriptions .......................................................... 516
1-242. VPDMA_int0_client1_int_mask Register Field Descriptions ........................................................ 520
1-243. VPDMA_int0_list0_int_stat Register Field Descriptions ............................................................. 523
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