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4SPRUHI7A–December 2012–Revised June 2016
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List of Figures
1-48. TVDETGP Horizontal Timing............................................................................................ 100
1-49. TVDETGP Vertical Timing............................................................................................... 100
1-50. SDTV Horizontal Timing ................................................................................................. 101
1-51. 525i Vertical Timing ...................................................................................................... 102
1-52. 625i Vertical Timing ...................................................................................................... 102
1-53. SDTV DAC Video Output Pipeline Delay (PXLR = 0) ............................................................... 103
1-54. SDTV DAC Video Output Pipeline Delay (PXLR = 1) ............................................................... 103
1-55. 262p (Non-Interlaced NTSC) Vertical Timing ......................................................................... 104
1-56. 312p (Non-Interlaced PAL) Vertical Timing ........................................................................... 104
1-57. Horizontal Blanking Shaping ............................................................................................ 105
1-58. Slave Mode Horizontal Timing .......................................................................................... 105
1-59. Interlaced Slave Vertical Timing (FMD = 0,1)......................................................................... 106
1-60. Interlaced Slave Vertical Timing (FMD = 2)........................................................................... 106
1-61. Interlaced Slave Vertical Timing (FMD = 3)........................................................................... 107
1-62. Field Detection Mode..................................................................................................... 108
1-63. Field Detection by VD Phase (FMD=3)................................................................................ 108
1-64. CVBS Video Amplitude .................................................................................................. 117
1-65. Limiter Configuration ..................................................................................................... 120
1-66. Sub-carrier Parameter Registers ....................................................................................... 121
1-67. WSS_Data Register Usage ............................................................................................. 122
1-68. WSS_Data Register Usage ............................................................................................. 122
1-69. VBI I/F Horizontal Timing ................................................................................................ 124
1-70. VBI I/F Vertical Timing ................................................................................................... 124
1-71. DAC I/F Logic ............................................................................................................. 127
1-72. HD VENC Block Diagram................................................................................................ 129
1-73. Vertical Sync Signals for OSD .......................................................................................... 130
1-74. Horizontal Sync-related Signal for OSD ............................................................................... 130
1-75. Video Data Interface Between OSD and Encoder ................................................................... 131
1-76. OSD Interface in Progressive Mode.................................................................................... 132
1-77. OSD Interface in Interlace Mode ....................................................................................... 133
1-78. Progressive Configuration of DVO ..................................................................................... 135
1-79. Interlace Configuration of DVO ......................................................................................... 136
1-80. Typical VBI Data Package............................................................................................... 137
1-81. NTSC Analog Video Waveform for One Horizontal Line ............................................................ 141
1-82. Digitized Video ............................................................................................................ 141
1-83. Code Word Embedded Video Format.................................................................................. 142
1-84. Digitized Video with F, V, and H Flags in EAV/SAV ................................................................. 142
1-85. Planar Buffer Storage Description...................................................................................... 143
1-86. 8b Interface Discrete Sync Pixel Multiplexing......................................................................... 144
1-87. 16b Interface Discrete Sync Pixel Multiplexing ....................................................................... 144
1-88. 24b Interface RGB or YUV444 Discrete Sync ........................................................................ 145
1-89. 24 Device Pins for Ports A and B....................................................................................... 145
1-90. Discrete Sync Signals.................................................................................................... 146
1-91. Type 1, First Horizontal Blanking Pixel ................................................................................ 147
1-92. Type 1, First Vertical Ancillary Data Pixel ............................................................................. 147
1-93. Type 1, Horizontal Blanking in Video Region ......................................................................... 148
1-94. Type 1, First Video Pixel................................................................................................. 148
1-95. 4-Pin Reduced ACTVID Signaling with Vertical Ancillary Data..................................................... 149
1-96. 4-Pin Reduced ACTVID Signaling with No Vertical Ancillary Data................................................. 149