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Analog Devices ADM1026 Instruction manual

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=
PRELIMINARY
TECHNICAL
DATA
VersatilePC
SystemsMonitorASIC
ADM1026
FEATURES
Upto19AnalogMeasurementChannels(IncludingInter-
nalMeasurements)
Upto8FanSpeedMeasurementChannels
Upto13General-PurposeLogicI/OPins
RemoteTemperatureMeasurementwithRemoteDiode
(Two Channels)
On-ChipTemperatureSensor
AnalogandPWMFanSpeedControlOutputs
I2CCompatibleSystemManagementBus(SMBus)
8kbyteson-chipE2PROM
FUNCTIONAL BLOCK DIAGRAM
REV. PrL 06/00
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
PreliminaryTechnicalData
I
2
C is a registered trademark of Philips Corporation
ChassisIntrusionDetect
InterruptOutput
ResetInput,Reset Outputs
ThermalInterrupt(THERM)Output
ShutdownModetoMinimizePowerConsumption
LimitComparisonofallMonitoredValues
APPLICATIONS
NetworkServersandPersonalComputers
Microprocessor-BasedOfficeEquipment
TestEquipmentandMeasuringInstruments
3.3V STBY
RESET
GENERATOR
3.3V MAIN
RESET
GENERATOR
INPUT
ATTENUATORS
AND
ANALOG
MULTIPLEXER
+VBAT(0 - +4.0V)
+5VIN(0 - +6.66V)
-12VIN(0 - -16V)
+12VIN(0 - +16V)
+VCCPIN(0 - +3V)
AIN0(0 - +3V)
AIN1(0 - +3V)
AIN2(0 - +3V)
AIN3(0 - +3V)
AIN4(0 - +3V)
AIN5(0 - +3V)
AIN6(0 - +2.5V)
AIN7(0 - +2.5V)
D2+/AIN8(0 - +2.5V)
D2-/AIN9(0 - +2.5V)
D1+
D1-/NTESTIN
BANDGAP
TEMP. SENSOR
DGND
DAC
RESETSTBY
BANDGAP
REFERENCE
AGND VREF (1.82V OR 2.5V)
PWM REGISTER
AND CONTROLLER
VALUE AND
LIMIT
REGISTERS
LIMIT
COMPARATORS
SERIAL BUS
INTERFACE
SCLSDA 3.3V MAIN
GPIO
REGISTERS
ADD/
NTESTOUT
ADDRESS
POINTER
REGISTER
FAN7/GPIO7
FAN6/GPIO6
FAN5GPIO5
FAN4/GPIO4
FAN3/GPIO3
FAN2/GPIO2
FAN1/GPIO1
FAN0/GPIO0
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO9
GPIO8
PWM
3.3VSTBY
INT MASK
REGISTERS
GPIO16/THERM
CONFIGURATION
REGISTERS
INTERRUPT
STATUS
REGISTERS CI
ADM1026
TEMPERATURE
CONFIGURATION
REGISTER
INTERRUPT
MASKING
FAN SPEED
COUNTER
8-BIT ADC
8KBYTES
E2PROM
ANALOG
OUTPUT REGISTER
AND 8-BIT DAC
RESETMAIN
INT
100k⍀
⍀⍀
⍀
TO GPIO
REGISTERS
RESET IN
VCC
100k⍀
⍀⍀
⍀
VCC
VCC
100k⍀
⍀⍀
⍀
VCC
100k⍀
⍀⍀
⍀
PRELIMINARY
TECHNICAL
DATA
Parameter Min Typ Max Units Test Conditions/Comments
POWER SUPPLY
SupplyVoltage,3.3VMAIN,3.3VSTBY 2.8 3.30 5.5 V
SupplyCurrent,I
CC
1.4 2.0 mA InterfaceInactive,ADCActive
1.0 mA ADCInactive,DACActive
3 100 µA ShutdownMode
TEMP. -TO-DIGITAL CONVERTER
InternalSensorAccuracy ±3
o
C
Resolution ±1
o
C
ExternalDiodeSensorAccuracy ±5
o
C0
o
C ≤T
A
≤+100
o
C
Resolution ±1
o
C
RemoteSensorSourceCurrent 90 µA HighLevel
5.5 µΑLowLevel
ANALOG-TO-DIGITAL CONVERTER
(INCLUDING MUX AND ATTENUATORS)
TotalUnadjustedError,TUE ±2 % Note 3
DifferentialNon-Linearity,DNL ±1 LSB
PowerSupplySensitivity ±1 %/V
ConversionTime(AnalogInputorInt.Temp) 11.38 12.06 ms See Note 4
ConversionTime(ExternalTemperature) 34.13 36.18 ms See Note 4
InputResistance(+12V, +5V,V
BAT
, V
CCP
100 140 200 k⍀
AIN0-AIN5)
InputResistance of -12V pin 10 k⍀
InputResistance(AIN6-AIN9) HighResistance
ANALOG OUTPUT
OutputVoltageRange 0 2.5 V
TotalUnadjustedError,TUE ±3 % I
L
= 2mA
Full-ScaleError ±1 ±3 %
ZeroError 2 LSB NoLoad
DifferentialNon-Linearity,DNL ±1 LSB MonotonicbyDesign
IntegralNon-Linearity ±1 LSB
OutputSourceCurrent 2 mA
OutputSinkCurrent 1 mA
REFERENCE OUTPUT
OutputVoltage 1.8 1.82 1.84 V Bit 2 of Register 07h = 1
OutputVoltage 2.47 2.50 2.53 V Bit 2 of Register 07h = 0
LineRegulation ? %/V
LoadRegulation ? µV/mA
Short-CircuitCurrent ? mA
OutputCurrentSource 2 mA
OutputCurrentSink 2 mA
REV. PrL
–2–
ADM1026–SPECIFICATIONS
(TA= TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted)
PRODUCT DESCRIPTION
TheADM1026isacompletesystemhardwaremonitorformicroprocessor-basedsystems,providingmeasurementandlimitcomparisonofvarious
systemparameters.TheADM1026hasupto19analogmeasurementchannels.Fifteenanalogvoltageinputsareprovided,ofwhichfivearededi-
catedtomonitoring+3.3V,+5Vand±12Vpowersuppliesandtheprocessorcorevoltage.TheADM1026canmonitortwofurtherpower-supply
voltagesbymeasuringitsownanaloganddigitalV
CC
.Oneinput(twopins)isdedicatedtoaremotetemperature-sensingdiode.Twofurtherpins
canbeconfiguredasgeneral-purposeanaloginputstomeasure0to2.5V,orasasecondtemperaturesensinginput.The8remainingremaininginputs
aregeneral-purpose analoginputswitharange of0to2.5Vor0 to3V.Finally,theADM1026 hasonon-chiptemperaturesensor.
TheADM1026haseightpinsthatcanbeconfiguredforfan-speedmeasurementorasgeneralpurposelogicI/Opins.Afurther8pinsarededi-
cated to general-purpose logic I/O. One pin can be configured as a general purpose I/O or as the THERM output.
MeasuredvaluescanbereadoutviaanI
2
C-compatibleserialSystemManagementBus,andvaluesforlimitcomparisonscanbeprogrammedin
overthesameserialbus.Thehigh-speedsuccessive-approximationADCallowsfrequentsamplingofallanalogchannelstoensureafastinterrupt
responsetoanyout-of-limitmeasurement.
TheADM1026’s 2.8V to 5.5V supply voltage range, lowsupplycurrent,andI
2
Ccompatible interface makeitidealforawiderangeofapplica-
tions.Theseincludehardwaremonitoringandprotectionapplicationsinpersonalcomputers,electronictestequipment,andofficeelectronics.
PRELIMINARY TECHNICAL DATA ADM1026
–3–
REV. PrL
PRELIMINARY
TECHNICAL
DATA
Specifications(Continued)
Parameter Min Typ Max Units Test Conditions/Comments
FAN RPM-TO-DIGITAL CONVERTER See Note 5
Accuracy ±6 %
Full-ScaleCount 255
FAN0TOFAN7NominalInputRPM 8800 RPM Divisor =1, Fan Count= 153
(Note 5) 4400 RPM Divisor = 2,Fan Count =153
2200 RPM Divisor= 4, FanCount =153
1100 RPM Divisor= 8, FanCount =153
InternalClockFrequency 21.1 22.5 23.9 kHz
DIGITAL OUTPUTS, PWM, GPIO0-16
Output High Voltage, V
OH
2.4 V I
OUT
= 3.0mA,
V
CC
= 2.85V - 3.60V
Output Low Voltage, V
OL
0.4 V I
OUT
= -3.0mA,
V
CC
= 2.85V - 3.60V
PWMOutputFrequency 75 Hz
OPEN-DRAIN DIGITAL OUTPUTS
((
((
(INTINT
INTINT
INT,,
,,
,RESETMAINRESETMAIN
RESETMAINRESETMAIN
RESETMAIN,,
,,
,RESETSTBYRESETSTBY
RESETSTBYRESETSTBY
RESETSTBY))
))
)
Output Low Voltage, V
OL
0.4 V I
OUT
= -3.0mA, V
CC
= 3.60V
HighLevelOutput Current, I
OH
0.1 100 µA V
OUT
= V
CC
RESET Pulse Width 140 180 240 ms
OPEN-DRAIN SERIAL DATA
BUS OUTPUT (SDA)
Output Low Voltage, V
OL
0.4 V I
OUT
= -3.0mA,
V
CC
= 2.85V - 3.60V
HighLevelOutput Current, I
OH
0.1 100 µA V
OUT
= V
CC
SERIAL BUS DIGITAL INPUTS
(SCL, SDA)
InputHigh Voltage, V
IH
2.2 V
InputLow Voltage, V
IL
0.8 V
Hysteresis 500 mV
DIGITAL INPUT LOGIC LEVELS
(ADD, CI, FAN0-7, GPIO0-16) See Notes 6 and 7
InputHigh Voltage, V
IH
2.4 V V
CC
= 2.85V - 5.5V
InputLow Voltage, V
IL
0.8 V V
CC
= 2.85V - 5.5V
Hysteresis(Fan0-7) 250 mV V
CC
= 3.3V
RESETMAINRESETMAIN
RESETMAINRESETMAIN
RESETMAIN, RESETSTBYRESETSTBY
RESETSTBYRESETSTBY
RESETSTBY
ResetThreshold(Resetoutputisactive(low)below 2.9 3.05 V RESETMAIN triggered from AV
CC
thisthreshold.Resetinactiveabovethisthreshold 3.1 3.2 RESETSTBY triggered from DV
CC
Hysteresis 30 mV
DIGITAL INPUT CURRENT
InputHighCurrent,I
IH
-1 µA V
IN
= V
CC
InputLowCurrent,I
IL
1µAV
IN
= 0
InputCapacitance,C
IN
20 pF
SERIAL BUS TIMING
ClockFrequency,f
SCLK
400 kHz SeeFigure1
Glitch Immunity, t
SW
50 ns SeeFigure1
Bus Free Time, t
BUF
4.7 µs SeeFigure1
Start Setup Time, t
SU;STA
4.7 µs SeeFigure1
Start Hold Time, t
HD;STA
4 µs SeeFigure1
SCL Low Time, t
LOW
4.7 µs SeeFigure1
SCL High Time, t
HIGH
4 µs SeeFigure1
SCL,SDARiseTime,t
r
1000 ns SeeFigure1
SCL,SDAFallTime,t
f
300 µs SeeFigure1
Data Setup Time, t
SU;DAT
250 ns SeeFigure1
Data Hold Time, t
HD;DAT
300 ns SeeFigure1
ADM1026 PRELIMINARY TECHNICAL DATA
–4– REV. PrL
PRELIMINARY
TECHNICAL
DATA
ABSOLUTE MAXIMUM RATINGS*
Positive Supply Voltage (V
CC
) . . . . . . . . . . . . . . . . . 6.5 V
Voltage on 12V V
IN
Pin . .. ... ... ... ... ... .. .. .. +20V
Voltage on -12V V
IN
Pin . . . . . . . . . . . . . . . . . . . . . . . -20V
Voltage on DAC, ADD . . . . . . . . . . -0.3V to (V
CC
+0.3V)
Voltage on Any Other Input or Output Pin . . -0.3V to 6.5V
Input Current at any pin (Note 2) . . . . . . . . . . . . . . ±5mA
Package Input Current (Note 2) . . . . . . . . . . . . . . ±20mA
Maximum Junction Temperature (T
J
max) . . . . . . .150 °C
Storage Temperature Range . . . . . . . . .–65°C to +150°C
Lead Temperature, Soldering
Vapor Phase 60 sec . . . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infra-Red 15 sec . . . . . . . . . . . . . . . . . . . . . . . . . +200°C
ESD Rating -12V
IN
pin . . . . . . . . . . . . . . . . . . . . . 1000 V
ESD Rating all other pins . . . . . . . . . . . . . . . . . . . 2000 V
*Stressesabovethoselistedunder“AbsoluteMaximumRatings”maycausepermanent
damagetothedevice. Thisisastressratingonly;functionaloperationofthedevice
attheseoranyotherconditionsabovethoseindicatedintheoperationalsectionofthis
specification is not implied. Exposure to absolute maximum rating conditions for
extendedperiodsmayaffectdevicereliability.
THERMAL CHARACTERISTICS
48-Pin LQFP Package:
θ
JA
= 50°C/Watt,θ
JC
= 10°C/Watt
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
ADM1026AST 0°C to +85°C 48-Pin LQFP ST48
P SSP
tHD;STA tHD;DAT
tHIGH tSU;DAT
tSU;STA tSU;STO
tLOW
tRtFtHD;STA
SCL
SDA
tBUF
Figure 1. Diagram for Serial Bus Timing
PIN CONFIGURATION
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
ADM1026
TOP VIEW
(Not to Scale)
PIN 1 IDENTIFIER
GPIO9
GPIO8
FAN0/GPIO0
FAN1/GPIO1
FAN2/GPIO2
FAN3/GPIO3
3.3V MAIN
DGND
FAN4/GPIO4
FAN5/GPIO5
FAN6/GPIO6
FAN7/GPIO7
SCL
SDA
ADD/NTESTOUT
CI
INT
PWM
RESETSTBY
RESETMAIN
AGND
3.3V STBY
DAC
V
REF
AIN5(0 - 3V)
AIN6(0 - 2.5V)
AIN7(0 - 2.5V)
VCCP(0 - 3V)
+12VIN(0 - 16V)
-12VIN(0 - 16V)
+5VIN(0 - 6.66V)
+VBAT(0 - 4.4V)
D2+/AIN8(0 - 2.5V)
D2-/AIN9(0 - 2.5V)
D1+
D1-/NTESTIN
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16/THERM
A
IN0
(0 - 3V)
A
IN1
(0 - 3V)
A
IN2
(0 - 3V)
A
IN3
(0 - 3V)
A
IN4
(0 - 3V)
1
2
3
4
5
6
7
8
9
10
11
12
NOTES
1
All voltages are measured with respect to GND, unless otherwise specified
2
TypicalsareatT
A
=25°Candrepresentmostlikelyparametricnorm.Shutdowncurrenttypismeasuredwith V
CC
=3.3V
3
TUE(TotalUnadjustedError)includesOffset,GainandLinearityerrors oftheADC, multiplexerandon-chip inputattenuators,includinganexternalseriesinputpro-
tectionresistorvaluebetweenzeroand1k⍀.
4
Total analog monitoring cycle time is nominally 273ms, made up of 18 ⫻11.38ms measurements on analog input and internal tempeerature channels, and 2 ⫻34.13ms
measurementsonexternaltemperaturechannels.
5
The total fan count is based on 2 pulses per revolution of the fan tachometer output. The total fan monitoring time depends on the number of fans connected and the
fan speed. See section on Fan Speed Monitoring for more details.
6
ADD is a three-state input that may be pulled high, low or left open-circuit.
7
Logic inputs will accept input high voltages up to 5V even when device is operating at supply voltages below 5V.
8
Timing specifications are tested at logic levels of V
IL
= 0.8V for a falling edge and V
IH
= 2.2V for a rising edge.
PRELIMINARY TECHNICAL DATA ADM1026
–5–
REV. PrL
PRELIMINARY
TECHNICAL
DATA
PIN FUNCTION DESCRIPTION
PIN NO. MNEMONIC TYPE DESCRIPTION
1 GPIO9 Digital Input General purpose I/O pin can be configured as a digital input or output.
2 GPIO8 Digital Input General purpose I/O pin can be configured as a digital input or output.
3 FAN0/GPIO0 Digital I/O Fan tachometer input, or can be re-configured as a general purpose
digital I/O pin. This pin has an internal 10k⍀pullup resistor.
4 FAN1/GPIO1 Digital I/O Fan tachometer input, or can be re-configured as a general purpose
digital I/O pin. This pin has an internal 10k⍀pullup resistor.
5 FAN2/GPIO2 Digital I/O Fan tachometer input, or can be re-configured as a general purpose
digital I/O pin. This pin has an internal 10k⍀pullup resistor.
6 FAN3/GPIO3 Digital I/O Fan tachometer input, or can be re-configured as a general purpose
digital I/O pin. This pin has an internal 10k⍀pullup resistor.
7 3.3V MAIN Power Main 3.3V power supply.
8 DGND Ground Ground pin for digital circuits.
9 FAN4/GPIO4 Digital Input Fan tachometer input, or can be re-configured as a general purpose
digital I/O pin. This pin has an internal 10k⍀pullup resistor.
10 FAN5/GPIO5 Digital Input Fan tachometer input, or can be re-configured as a general purpose
digital I/O pin. This pin has an internal 10k⍀pullup resistor.
11 FAN6/GPIO6 Digital Input Fan tachometer input, or can be re-configured as a general purpose
digital I/O pin. This pin has an internal 10k⍀pullup resistor.
12 FAN7/GPIO7 Digital Input Fan tachometer input, or can be re-configured as a general purpose
digital I/O pin. This pin has an internal 10k⍀pullup resistor.
13 SCL Digital Input Open-drain Serial Bus Clock. Requires 2.2k⍀pullup resistor.
14 SDA Digital I/O Serial Bus Data. Open-drain output. Requires 2.2k⍀pullup resistor.
15 ADD/ Digital Input This is a three-state input that controls the two LSBs of the Serial Bus
NTESTOUT Address. It also functions as the output for NAND tree testing.
16 CI Digital Input An active high input which captures a Chassis Intrusion event in Bit 7
of Status Register 4. This bit will remain set until cleared, so long as
battery voltage is applied to the V
BAT
input, even when the ADM1026
is powered off.
17 INT Digital Output Interrupt Request (open drain). The output is enabled when Bit 1 of
the Configuration Register is set to 1. The default state is disabled.
It has an on-chip 100k⍀pullup resistor.
18 PWM Digital Output Pulse-width modulated output for control of fan speed. Open drain.
19 RESETSTBY Digital Output Power-on Reset. 5 mA driver (open drain), active low output with a
200 ms minimum pulse width. RESETSTBY is asserted whenever
3.3VSTBY is below the reset threshold. It remains asserted for approx.
200ms after 3.3VSTBY rises above the reset threshold.
20 RESETMAIN Digital I/O Power-on Reset. 5 mA driver (open drain), active low output with a
200 ms minimum pulse width. RESETMAIN is asserted whenever
3.3V MAIN is below the reset threshold. It remains asserted forapprox.
200ms after 3.3V MAIN rises above the reset threshold. If, however,
3.3V STBY rises with or before 3.3V MAIN, then RESETMAIN
remains asserted for 200ms after RESETSTBY is de-asserted. Pin 21
also functions as an active low RESET input.
21 AGND Ground Ground pin for analog circuits
22 3.3V STBY Power Standby 3.3V power supply.
ADM1026 PRELIMINARY TECHNICAL DATA
–6– REV. PrL
PRELIMINARY
TECHNICAL
DATA
PIN FUNCTION DESCRIPTION (CONTINUED)
PIN NO. MNEMONIC TYPE DESCRIPTION
23 DAC Analog Output 0 to 2.5V output for analog control of fan speed.
24 VREF Analog Output Reference voltage output. Can be selected as 1.8V (default) or 2.5V.
25 D1-/NTESTIN Analog Input Connected to cathode of 1st remote temperature sensing diode. If held
high at power up it activates NAND tree test mode.
26 D1+ Analog Input Connected to anode of 1st remote temperature sensing diode.
27 D2-/AIN9 Programmable Connected to cathode of 2nd remote temperature sensing diode, or
Analog Input may be re-configured as a 0 - 2.5V analog input
28 D2+/AIN8 Programmable Connected to anode of 2nd remote temperature sensing diode, or
Analog Input may be re-configured as a 0 - 2.5V analog input
29 V
BAT
Analog Input Monitors battery voltage, nominally +3.3 V.
30 +5V
IN
Analog Input Monitors +5 V supply.
31 -12V
IN
Analog Input Monitors -12 V supply.
32 +12V
IN
Analog Input Monitors +12 V supply.
33 +V
CCP
Analog Input Monitors processor core voltage (0 to 3.0V).
34 AIN7 Analog Input General-purpose 0 to 2.5V analog input.
35 AIN6 Analog Input General-purpose 0 to 2.5V analog input.
36 AIN5 Analog Input General-purpose 0 to 3V analog input.
37 AIN4 Analog Input General-purpose 0 to 3V analog input.
38 AIN3 Analog Input General-purpose 0 to 3V analog input.
39 AIN2 Analog Input General-purpose 0 to 3V analog input.
40 AIN1 Analog Input General-purpose 0 to 3V analog input.
41 AIN0 Analog Input General-purpose 0 to 3V analog input.
42 GPIO16/ Digital I/O General purpose I/O pin can be configured as a digital input or output.
THERM Can also be configured as THERM output.
43 GPIO15 Digital I/O General purpose I/O pin can be configured as a digital input or output.
44 GPIO14 Digital I/O General purpose I/O pin can be configured as a digital input or output.
45 GPIO13 Digital I/O General purpose I/O pin can be configured as a digital input or output.
46 GPIO12 Digital I/O General purpose I/O pin can be configured as a digital input or output.
47 GPIO11 Digital I/O General purpose I/O pin can be configured as a digital input or output.
48 GPIO10 Digital I/O General purpose I/O pin can be configured as a digital input or output.
PRELIMINARY TECHNICAL DATA ADM1026
–7–
REV. PrL
PRELIMINARY
TECHNICAL
DATA
FUNCTIONAL DESCRIPTION
GENERAL DESCRIPTION
The ADM1026 is a complete system hardware monitor for
microprocessor-based systems. The device communicates
with the system via a serial System Management Bus. The
serial bus controller has a hardwired address line for device
selection (ADD, pin 15), a serial data line for reading and
writing addresses and data (SDA, pin 14), and an input line
for the serial clock (SCL, pin 13). All control and pro-
gramming functions of the ADM1026 are performed over
the serial bus.
MEASUREMENT INPUTS
Programmability of the analog and digital measurement
inputs makes the ADM1026 extremely flexible and versa-
tile. The device has an 8 bit A to D converter, and 17 ana-
log measurement input pins that can be configured in
different ways.
Pins 25 and 26 are dedicated temperature inputs and may
be connected to the cathode and anode of a remote tem-
perature-sensing diode.
Pins 27 and 28 may be configured as a temperature input
and connected to a second temperature-sensing diode, or
they may be re-configured as analog inputs with a range of
0 to +2.5V.
Pins 29 to 33 are dedicated analog inputs with on-chip at-
tenuators, configured to monitor V
BAT
, +5V, -12V, +12V,
and the processor core voltage V
CCP
, respectively.
Pins 34 to 41 are general-purpose analog inputs with a
range of 0 to +2.5V or 0 to +3V. These are mainly in-
tended for monitoring SCSI termination voltages, but may
be used for other purposes.
The ADC also accepts input from an on-chip bandgap tem-
perature sensor that monitors system ambient temperature.
Finally, the ADM1026 monitors the supplies from which it
is powered, 3.3VMAIN and 3.3VSTBY, so there is no need
for separate pins to monitor these power supply voltages.
The ADM1026 has 8 pins that are general-purpose logic
I/O pins (pins 1,2 and 43 to 48), 1 pin that can be config-
ured as GPIO or as a thermal interrupt (THERM) output
(pin 42) and 8 pins that can be configured for fan speed
measurement or as general-purpose logic pins (pins 3 to 6
and 9 to 12).
SEQUENTIAL MEASUREMENT
When the ADM1026 monitoring sequence is started, it
cycles sequentially through the measurement of analog in-
puts and the temperature sensor, while at the same time
the fan speed inputs are independently monitored. Mea-
sured values from these inputs are stored in Value Regis-
ters. These can be read out over the serial bus, or can be
compared with programmed limits stored in the Limit
Registers. The results of out of limit comparisons are
stored in the Interrupt Status Registers, and will generate
an interrupt on the INT line (pin 17).
Any or all of the Interrupt Status Bits can be masked by
appropriate programming of the Interrupt Mask Registers.
CHASSIS INTRUSION
A chassis intrusion input (pin 16) is provided to detect
unauthorised tampering with the equipment. This event is
latched in a battery-backed up register bit.
RESETS
The ADM1026 has two power on reset outputs,
RESETMAIN and RESETSTBY, that are asserted when
3.3VMAIN or 3.3VSTBY fall below the reset threshold.
These give a 180ms reset pulse at power up. RESETMAIN
also functions as an active-low RESET input.
FAN SPEED CONTROL OUTPUTS
The ADM1026 has two outputs intended to control fan
speed, though they can also be used for other purposes.
Pin 22 is a pulse-width modulated (PWM) output with a
programmable duty-cycle and an output frequency of typi-
cally 75Hz.
Pin 23 is connected to the output of an on-chip, 8-bit
digital-to-analog converter with an output range of zero to
2.5V.
Either or both of these outputs may be used to implement
a temperature-controlled fan by controlling the speed of a
fan dependent upon the temperature measured by the on-
chip temperature sensor or remote temperature sensors.
INTERNAL REGISTERS OF THE ADM1026
The ADM1026 contains a large number of data registers.
A brief description of the principal registers is given be-
low. More detailed descriptions are given in the relevant
sections and in the tables at the end of the data sheet.
Address Pointer Register: This register contains the address
that selects one of the other internal registers. When writing to
the ADM1026, the first byte of data is always a register ad-
dress, which is written to the Address Pointer Register.
Configuration Registers: Provide control and configuration
for various operating parameters of the ADM1026.
Fan Divisor Registers: Contain counter pre-scaler values
for fan speed measurement.
Fan Speed Registers: Contain speed values for PWM and
DAC fan drive outputs.
GPIO Configuration Registers: These configure the
GPIO pins as input or output and for signal polarity.
Value and Limit Registers: The results of analog voltage
inputs, temperature and fan speed measurements are
stored in these registers, along with their limit values.
Status Registers: These registers store events from the
various interrupt sources.
Mask Registers: Allow masking of individual interrupt
sources.
EEPROM
The ADM1026 has 8kbytes of non-volatile, Electrically-
Erasable Programmable Read-Only Memory (EEPROM),
from register addresses 8000h to 9FFFh. This may be
used for permanent storage of data that will not be lost
when the ADM1026 is powered down, unlike the data in
ADM1026 PRELIMINARY TECHNICAL DATA
–8– REV. PrL
PRELIMINARY
TECHNICAL
DATA
the volatile registers. Although referred to as Read Only
Memory, the EEPROM can be written to (as well as read
from) via the serial bus in exactly the same way as the
other registers. The only major differences between the
E
2
PROM and other registers are:
1. An EEPROM location must be blank before it can be
written to. If it contains data, it must first be erased.
2. Writing to EEPROM is slower than writing to RAM.
3. Writing to the EEPROM should be restricted because
it has a limited write/cycle life of typically 10,000 write
operations, due to the usual EEPROM wear-out
mechanisms.
SERIAL BUS INTERFACE
Control of the ADM1026 is carried out via the serial Sys-
tem Management Bus (SMBus). The ADM1026 is con-
nected to this bus as a slave device, under the control of a
master device.
The ADM1026 has a 7-bit serial bus slave address. When
the device is powered up, it will do so with a default serial
bus address. The five MSB's of the address are set to
01011, the two LSB's are determined by the logical states
of pin 15 (ADD/NTESTOUT). This is a three-state in-
put that can be grounded, connected to V
CC
or left open-
circuit to give three different addresses.
TABLE 1. ADDRESS PIN TRUTH TABLE
ADD Pin A1 A0
GND 0 0
No Connect 1 0
V
CC
01
If ADD is left open-circuit the default address will be
0101110. ADD is sampled only at power-up, so any changes
made while power is on will have no immediate effect.
The facility to make hardwired changes to A1 and A0 al-
lows the user to avoid conflicts with other devices sharing
the same serial bus, for example if more than one
ADM1026 is used in a system.
GENERAL SMBUS TIMING
Figures 2a and 2b show timing diagrams for general read
and write operations using the SMBus. The SMBus speci-
fication defines specific conditions for different types of
read and write operation, which are discussed later.
The general SMBus protocol operates as follows:
1. The master initiates data transfer by establishing a
START condition, defined as a high to low transition
on the serial data line SDA whilst the serial clock line
SCL remains high. This indicates that an data stream
will follow. All slave peripherals connected to the serial
bus respond to the START condition, and shift in the
next 8 bits, consisting of a 7-bit slave address (MSB
first) plus a R/Wbit, which determines the direction of
the data transfer, i.e. whether data will be written to or
read from the slave device (0 = write, 1 = read).
The peripheral whose address corresponds to the trans-
mitted address responds by pulling the data line low
during the low period before the ninth clock pulse,
known as the Acknowledge Bit, and holding it low dur-
ing the high period of this clock pulse. All other de-
vices on the bus now remain idle whilst the selected
device waits for data to be read from or written to it. If
the R/Wbit is a 0 then the master will write to the slave
device. If the R/Wbit is a 1 the master will read from
the slave device.
2. Data is sent over the serial bus in sequences of 9 clock
pulses, 8 bits of data followed by an Acknowledge Bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal
and remain stable during the high period, as a low to
high transition when the clock is high may be inter-
preted as a STOP signal.
If the operation is a write operation, the first data byte
after the slave address is a command byte. This tells the
slave device what to expect next. It may be an instruc-
tion such as telling the slave device to expect a block
write, or it may simply be a register address that tells
the slave where subsequent data is to be written.
R/W
0
SCL
SDA 1 0 1 1 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
SLAVE
START BY
MASTER
FRAME 1
SLAVE ADDRESS FRAME 2
COMMAND CODE
191
ACK. BY
SLAVE
9
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
SLAVE STOP BY
MASTER
FRAME N
DATA BYTE
1 99
SCL
(CONTINUED)
SDA
(CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
SLAVE
FRAME 3
DATA BYTE
1
Figure 2a. General SMBus Write Timing Diagram
PRELIMINARY TECHNICAL DATA ADM1026
–9–
REV. PrL
PRELIMINARY
TECHNICAL
DATA
Since data can flow in only one direction as defined by
the R/Wbit, it is not possible to send a command to a
slave device during a read operation. Before doing a
read operation, it may first be necessary to do a write
operation to tell the slave what sort of read operation to
expect and/or the address from which data is to be read.
3. When all data bytes have been read or written, stop con-
ditions are established. In WRITE mode, the master
will pull the data line high during the 10th clock pulse
to assert a STOP condition. In READ mode, the mas-
ter device will release the SDA line during the low pe-
riod before the 9th clock pulse, but the slave device will
not pull it low. This is known as No Acknowledge. The
master will then take the data line low during the low
period before the 10th clock pulse, then high during the
10th clock pulse to assert a STOP condition.
Note:
If it is required to perform several read or write operations
in succession, the master can send a repeat start condition
instead of a stop condition to begin a new operation.
SMBUS PROTOCOLS FOR RAM AND EEPROM
The ADM1026 contains volatile registers (RAM) and
non-volatile EEPROM. RAM occupies address locations
from 00h to 6Fh, whilst EEPROM occupies addresses
from 8000h to 9FFFh.
Data can be written to and read from both RAM and
EEPROM as single data bytes and as block (sequential)
read or write operations of 32 data bytes, which is the
maximum block size allowed by the SMBus specification.
Data can only be written to unprogrammed EEPROM lo-
cations. To write new data to a programmed location it is
first necessary to erase it. EEPROM erasure cannot be
done at the byte level, the EEPROM is arranged as 128
pages of 64 bytes, and an entire page must be erased.
The EEPROM has three RAM registers associated with it,
EEPROM Registers 1, 2 and 3 at addresses 06h, 0Ch and
13h. EEPROM Registers 1 and 2 are for factory use only.
EEPROM Register 3 is used to set up the EEPROM op-
erating mode.
Setting bit 0 of EEPROM Register 3 puts the EEPROM
into Read Mode. Setting bit 1 puts it into Programming
Mode. Setting Bit 2 puts it into Erase Mode.
One, and only one of these bits must be set before the
EEPROM may be accessed, Setting no bit or more than
one of them will cause the device to respond with No Ac-
knowledge if an EEPROM read, program or erase opera-
tion is attempted.
It is important to distinguish between SMBus write opera-
tions such as sending an address or command, and
EEPROM programming operations. It is possible write an
EEPROM address over the SMBus whatever the state of
EEPROM register 3. However, EEPROM Register 3
must be correctly set before a subsequent EEPROM op-
eration can be performed. For example, when reading
from the EEPROM, bit 0 of EEPROM Register 3 can be
set, even though SMBus write operations are required to
set up the EEPROM address for reading.
Bit 3 of EEPROM Register 3 is used for EEPROM write
protection. Setting this bit will prevent accidental pro-
gramming or erasure of the EEPROM. If a an EEPROM
write or erase operation is attempted with this bit set, the
ADM1026 will respond with No Acknowledge. This bit is
write once and can only be cleared by power-on reset.
EEPROM Register bit 7 is used for clock extend. Pro-
gramming an EEPROM byte takes approximately 250µs,
which would limit the SMBus clock for repeated or block
write operations. Setting bit 7 of EEPROM register 3 en-
ables the SMBus clock extend function. This allows the
ADM1026 to pull SCL low and extend the clock pulse
when it cannot accept any more data.
R/W
0
SCL
SDA 10
11A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
MASTER
START BY
MASTER
FRAME 1
SLAVE ADDRESS FRAME 2
DATA BYTE
191
ACK. BY
SLAVE
9
D7 D6 D5 D4 D3 D2 D1 D0
NO ACK. STOP BY
MASTER
FRAME N
DATA BYTE
1 99
SCL
(CONTINUED)
SDA
(CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
MASTER
FRAME 3
DATA BYTE
1
Figure 2b. General SMBus Read Timing Diagram
ADM1026 PRELIMINARY TECHNICAL DATA
–10– REV. PrL
PRELIMINARY
TECHNICAL
DATA
ADM1026 WRITE OPERATIONS
The SMbus specification defines several protocols for dif-
ferent types of read and write operations. The ones used in
the ADM1026 are discussed below. The following abbre-
viations are used in the diagrams:
S - START
P - STOP
R - READ
W - WRITE
A - ACKNOWLEDGE
A- NO ACKNOWLEDGE
The ADM1026 uses the following SMBus write protocols.
SendByte
In this operation the master device sends a single com-
mand byte to a slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by
the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a STOP condition on SDA and the
transaction ends.
In the ADM1026, the send byte protocol is used to write a
register address to RAM for a subsequent single byte read
from the same address or block read or write starting at
that address. This is illustrated in Figure 3a.
SSLAVE
ADDRESS WA RAM
ADDRESS
(00h TO 6Fh) AP
12 3 4 56
Figure 3a. Setting A RAM Address For Subsequent Read
If it is required to read data from the RAM immediately
after setting up the address, the master can assert a repeat
start condition immediately after the final ACK and carry
out a single byte read, block read or block write opera-
tion, without asserting an intermediate stop condition.
WriteByte/Word
In this operation the master device sends a command byte
and one or two data bytes to the slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by
the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master sends a data byte (or may assert STOP at
this point).
9. The slave asserts ACK on SDA.
10.The master asserts a STOP condition on SDA to end
the transaction.
In the ADM1026, the write byte/word protocol is used for
four purposes. The ADM1026 knows how to respond by
the value of the command byte and EEPROM register 3.
1. Write a single byte of data to RAM. In this case the
command byte is the RAM address from 00h to 6Fh
and the (only) data byte is the actual data. This is il-
lustrated in Figure 3b.
SSLAVE
ADDRESS WA RAM
ADDRESS
(00h TO 6Fh) ADATA AP
12 345678
Figure 3b. Single Byte Write To RAM
2. Set up a two byte EEPROM address for a subsequent
read or block read. In this case the command byte is
the high byte of the EEPROM address from 80h to
9Fh. The (only) data byte is the low byte of the
EEPROM address. This is illustrated in Figure 3c.
SSLAVE
ADDRESS WA
EEPROM
ADDRESS
HIGH BYTE
(80h TO 9Fh)
EEPROM
ADDRESS
LOW BYTE
(00h TO FFh)
AAP
12 3 4 5 6 78
Figure 3c. Setting An EEPROM Address
If it is required to read data from the EEPROM imme-
diately after setting up the address, the master can as-
sert a repeat start condition immediately after the final
ACK and carry out a single byte read, block read or
block write operation, without asserting an intermedi-
ate stop condition. In this case bit 0 of EEPROM Reg-
ister 3 should be set.
3. Erase a page of EEPROM memory. EEPROM
memory can be written to only if it is unprogrammed.
Before writing to one or more EEPROM memory lo-
cations that are already programmed, the page or pages
containing those locations must first be erased.
EEPROM memory is erased by writing an EEPROM
page address plus an arbitrary byte of data with bit 2 of
EEPROM Register 3 set to 1.
As the EEPROM consists of 128 pages of 64 bytes, the
EEPROM page address consists of the EEPROM ad-
dress high byte (from 80h to 9Fh) and the two MSB's
of the low byte. The lower 6 bits of the EEPROM ad-
dress low byte only specificy addresses within a page
and are ignored during an erase operation.
SSLAVE
ADDRESS WA
EEPROM
ADDRESS
HIGH BYTE
(80h TO 9Fh)
EEPROM
ADDRESS
LOW BYTE
(00h TO FFh)
AAARBITRARY
DATA AP
12 3 4 5 6 7 8 910
Figure 3d. EEPROM Page Erasure
Page erasure takes approximately 20ms. If the
EEPROM is accessed before erasure is complete, it
will respond with No Acknowledge.
4. Write a single byte of data to EEPROM. In this case
the command byte is the high byte of the EEPROM
address from 80h to 9Fh. The first data byte is the low