Analog Devices ADAU1962 User manual

Evaluation Board User Guide
UG-416
One Technology Way •P. O. Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: [phone] •Fax: [phone] •www.analog.com
Evaluating the ADAU1962/ADAU1966 High Performance,
Low Power, Multibit Sigma-Delta DACs
PACKAGE CONTENTS
ADAU1962/ADAU1966 evaluation board
USBi control interface board
USB cable
D-sub 25-pin to (8) XLR male
12 V desktop supply
OTHER SUPPORTING DOCUMENTATION
ADAU1962 data sheet
ADAU1966 data sheet
EVALUATION BOARD OVERVIEW
This user guide details the design and setup of the evaluation
board for the ADAU1962/ADAU1966. Because the ADAU1962
is a 12-channel device and the ADAU1966 is a 16-channel
device, the DAC 13 through DAC 16 outputs do not function
on the ADAU1962 evaluation board. The evaluation board must
be connected to an external 12 V dc power supply and ground; the
board draws approximately 150 mA.
On-board regulators derive 9 V, 5 V, and 3.3 V supplies for the
ADAU1962/ADAU1966 and peripherals. The ADAU1962/
ADAU1966 can be controlled through either an I2C or SPI
interface. A small external interface board, E VA L -ADUSB2EBZ,
also called an USBi, connects to a PC USB port and provides
either I2C or SPI access to the evaluation board through a ribbon
cable. A graphical user interface (GUI) program, the Automated
Register Window Builder, is provided for easy programming of
the chip in a Microsoft® Windows® PC environment. The
evaluation board allows demonstration and performance testing
of most ADAU1962/ADAU1966 features, including high
performance digital-to-analog converter (DAC) operation.
The board has an S/PDIF receiver with RCA and optical
connectors, as well as a discrete serial audio interface that is
available on the Analog Devices, Inc. system development
platform (SDP) interface. Analog outputs are accessible with two
D-sub, 25-pin connectors using the professional audio standard. A
single D-sub, 25-pin to XLR male cable is included with the board
for connecting individual DAC channels to an audio system.
EVALUATION BOARD DIAGRAM
Figure 1.
S/PDIF
INTERFACE
DSP
INTERFACE
CONTROL
INTERFACE
CLOCK
AND
DATA
ROUTING
DAC 9 TO
DAC 16
DAC 1 TO
DAC 8
POWER SUPPLY
ADAU1966/
ADAU1962
10717
-001
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.Rev. A | Page 1 of 28

UG-416 Evaluation Board User Guide
TABLE OF CONTENTS
Package Contents.............................................................................. 1
Other Supporting Documentation................................................. 1
Evaluation Board Overview ............................................................ 1
Evaluation Board Diagram.............................................................. 1
Revision History ............................................................................... 2
Setting Up the Evaluation Board .................................................... 3
Standalone Mode.......................................................................... 3
I2C and SPI Control...................................................................... 4
Automated Register Window Builder Software Installation .. 4
Hardware Setup—USBi ............................................................... 4
Powering the Board.......................................................................5
Reset for the Evaluation Board....................................................5
Setting Up the Master Clock (MCLK)........................................6
Crystal Operation..........................................................................6
PLL Selection .................................................................................7
Digital Audio Connections and Routing ...................................7
Connecting Analog Audio Cables ..............................................8
Using the ADAU1962/ADAU1966 .............................................8
Schematics and Artwork ..................................................................9
REVISION HISTORY
1/14—Rev. 0 to Rev. A
Added ADAU1962..............................................................Universal
Changes to Evaluation Board Overview Section and Figure 1 .. 1
5/12—Revision 0: Initial Version
Rev. A | Page 2 of 28

Evaluation Board User Guide UG-416
SETTING UP THE EVALUATION BOARD
STANDALONE MODE
The ADAU1962/ADAU1966 have a standalone mode that allows
the user to choose between a limited number of operation modes
without the need for a control interface. Applying a jumper across
JP21, as shown in Figure 2, pulls SA_MODE (Pin 46) high,
enabling the standalone mode in the ADAU1962/ADAU1966.
The SA_MODE selections are listed in Table 1.
Table 1. Standalone Modes
Pin(s) Jumper Setting Description
42 0 Serial audio interface, master mode
1 Serial audio interface, slave mode
43 0 MCLK select: 256 × fS, PLL
1 MCLK select: 384 × fS, PLL
44 0 CM = 2.25 V (for AVDD = 5 V)
1 CM = 1.50 V (for AVDD = 3.3 V)
45 0 Serial audio interface, I2S mode
1 Serial audio interface, TDM mode
32:31 00 TDM4, pulse
01 TDM8, pulse
10 TDM16, pulse
11 TDM8, 50% duty
On the ADAU1962/ADAU1966 evaluation board, each of the four
ADAU1962/ADAU1966 control port pins is brought to a block of
jumpers, allowing each pin to be assigned to either the I2C port or
the SPI port. In standalone mode, these jumpers can connect the
individual pins to high or low to put the ADAU1962/ADAU1966
in the desired mode.
Figure 2. SA_MODE—Slave, 256 × fS, CM = 2.25 V, I2S
The ADAU1962/ADAU1966 evaluation board arrives configured
for S/PDIF input. The S/PDIF receiver operates as a clock master,
putting out an I2S stream at 256 × fS. For a quick startup, the
ADAU1962/ADAU1966 are in standalone mode with the settings
shown in Figure 2. Pin 42 is pulled high (1) and Pin 43 to Pin 45 are
pulled low (0). According to Table 1, this puts the ADAU1962/
ADAU1966 in slave mode, running at 256 × fS, while common
mode (CM) is set to 2.25 V and the audio serial port is in I2S mode.
Notice in Figure 2 that the jumper for Pin 42 is assigned to 1 and
that the other pins are assigned to 0.
Figure 3. SA_MODE—Master, 384 × fS, CM = 1.50 V, TDM
Figure 3 shows the other options for each SA_MODE configuration
pin; master mode, running at 384 × fS, CM set to 1.50 V, and
the audio serial port in TDM mode. In the case where the
ADAU1962/ADAU1966 are put in TDM mode, Pin 31 and
Pin 32 can be pulled high or low to achieve the modes listed in
Table 1. The correct pins are outlined in the top left corner of
Figure 3, as DSD8 and DSD7.
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UG-416 Evaluation Board User Guide
I2C AND SPI CONTROL
The evaluation board can be configured for live control over
the registers in the ADAU1962/ADAU1966. When the
Automated Register Window Builder software is installed
and the USBi control interface is plugged into the board, the
software can control the ADAU1962/ADAU1966. For this
configuration, the ADAU1962/ADAU1966 must be assigned to
I2C mode using Address 00. See Figure 4 for the correct jumper
positions.
Figure 4. ADAU1962/ADAU1966 I2C Control, Address 00
The Automated Register Window Builder controls the
ADAU1962/ADAU1966 and is available for download under
the Tools, Software, & Simulation Models section of the
ADAU1962 and ADAU1966 product pages.
In addition, the ADAU1962/ADAU1966 can be put into SPI
mode for control by other means. See Figure 5 for the correct
jumper positions.
Figure 5. ADAU1962/ADAU1966 SPI Control
AUTOMATED REGISTER WINDOW BUILDER
SOFTWARE INSTALLATION
The Automated Register Window Builder is a program that
launches a graphical interface for direct, live control of the
ADAU1962/ADAU1966 registers. The GUI content for a
specific part is defined in a part-specific .xml file; these files are
included in the software installation. To install the Automated
Register Window Builder software, follow these steps:
1. Go to the ADAU1962 and ADAU1966 product pages and
download the 64-Bit OS (ARWB_64BIT.zip) or 32-Bit OS
(ARWB_32Bit.zip) file, which can be found under the
Tools, Software, & Simulation Models section of the
ADAU1962 and ADAU1966 product pages.
2. Open the downloaded.zip file and extract the files to an
empty folder on your PC.
3. Install the Automated Register Window Builder by
double-clicking setup.exe and following the prompts. A
computer restart is not required.
4. Copy the .xml file for the ADAU1962/ADAU1966 from the
extraction folder into the C:\ProgramFiles\Analog
Devices Inc\AutomatedRegWin folder, if it is not already
installed.
HARDWARE SETUP—USBi
To set up the USBi hardware, follow these steps:
1. Plug the USBi ribbon cable into J12, the I2C/SPI port.
2. Connect the USB cable to the PC and to the USBi.
3. When prompted for drivers, follow these steps:
a. Choose Install from a list or a specific location.
b. Choose Search for the best driver in these locations.
c. Check the box for Include this location in the search.
d. Find the USBi driver C:\Program Files\Analog
Devices Inc\AutomatedRegWin\USB drivers.
e. Click Next.
f. If prompted to choose a driver, select CyUSB.sys.
g. If the PC is running Windows XP and a message
appears saying that the software has not passed
Windows logo testing, click Continue Anyway.
4. Open the Automated Register Window Builder application
and load the .xml file for the part on the evaluation board.
Plug the 10-way ribbon cable on the USBi into the I2C/SPI
port (J12) on the evaluation board.
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Evaluation Board User Guide UG-416
POWERING THE BOARD
The ADAU1962/ADAU1966 evaluation board requires a power
supply input of 12 V dc and ground to the power jack; 12 V
draws ~150 mA at higher sample rates with all channels running.
The on-board regulators provide 9.0 V, 5.0 V, and 3.3 V rails. The
9.0 V rail is derived from 12 V by a linear regulator; it provides
voltage to the audio op amp in the active output filter for
Channel 1 and Channel 2. The 5.0 V rail is derived from 12 V
by a switching regulator; it can supply AVDD as well as IOVDD
for the ADAU1962/ADAU1966 and other peripherals. The 3.3 V
rail is derived from the 5.0 V supply by an LDO linear regulator;
it provides voltage to AVDD and IOVDD as well as other active
peripherals.
AVDD and IOVDD are selected on the board using 0 Ω, 0805
package resistors. Install only one resistor for each load, AVDD
and IOVDD, as described in Figure 6. Figure 6 shows AVDD
fed from 5.0 V and IOVDD fed from 3.3 V.
Figure 6. AVDD and IOVDD Selection Resistors
The ADAU1962/ADAU1966 have an internal voltage regulator
that allows the user to derive DVDD and PLLVDD from the
AVDD voltage source. The external PNP transistor, Q1, and
passives, C36, C40 and R56, make the regulator circuit shown in
Figure 7. Short both JP9 and JP11 to activate the circuit; JP9
supplies the emitter of the PNP, and JP11 powers the VSUPPLY
pin (Pin 25) on the ADAU1962/ADAU1966.
Figure 7. ADAU1962/ADAU1966 Internal Regulator Jumpers
Links are provided along each ADAU1962/ADAU1966 power rail
to give access for current measurement (see Figure 8). These
links also allow directly supplying voltage from an outside
source.
Figure 8. ADAU1962/ADAU1966 Power Links
RESET FOR THE EVALUATION BOARD
The ADAU1962/ADAU1966 evaluation board has provision for
resetting and powering down the ADAU1962/ADAU1966. S2 on
the evaluation board, shown in Figure 9, is a momentary reset
switch that pulls the master reset (MR) line low; this line
controls the reset generator U10. MR is also connected to the
USBi and SDP INTF connectors through steering diodes and
protection resistors so that outside devices can control the reset
state of the evaluation board, as shown in Figure 26. The power
down jumper, JP5, allows the MR line to be tied low. The output
of the reset generator drives the PU_/RST line.
The PU_/RST line is directly connected to two devices: the S/PDIF
receiver and the ADAU1962/ADAU1966. A pull-down resistor
holds the line low until the reset generator, U10, asserts the line
high, as shown in Figure 26. The PU_/RST line is also connected
to a pin on the SDP INTF through a steering diode and protection
resistor, allowing external reset control.
Figure 9. RESET Switch and Power-Down Jumper
10717-006
10717-007
10717-008
10717-009
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UG-416 Evaluation Board User Guide
SETTING UP THE MASTER CLOCK (MCLK)
The MCLK routing on the evaluation board is handled by a block
of jumpers, J5, allowing any one of four sources to be selected:
SPDIF, SMA connector, active OSC, and INTF connector. The
board comes with SPDIF selected, as shown in Figure 10.
Figure 10. SPDIF Selected as MCLK Source
The evaluation board has a 12.288 MHz active oscillator that
can be selected by shorting the OSC_EN jumper, JP8, and
selecting OSC on J5, as shown in Figure 11.
Figure 11. Active OSC-Enabled and Selected as MCLK
When using the SDP interface to add serial audio onto the
evaluation board, MCLK can either be supplied by the SDP
board, or it can be supplied by the MCLKO pin of the
ADAU1962/ADAU1966.
To route MCLK from the SDP interface to the ADAU1962/
ADAU1966, apply a shorting jumper across JP6 (MCLK_SEL),
as shown in Figure 12; this sets the direction of the level
translators on the board to receive an MCLK signal from the
SDP interface, EI3 1A, Pin 119 (EI3_MCLK), as shown in
Figure 28. Next, select INTF on JP5 to route the output of
the MCLK level translator to the MCLKI pin of the
ADAU1962/ADAU1966.
Figure 12. INTF Input Enabled and Selected
To route MCLK from the ADAU1962/ADAU1966 to the SDP
interface, remove the shorting jumper from JP6 (MCLK_SEL); this
changes the direction of the level translators and feeds a buffered
version of the MCLKO signal from the ADAU1962/ADAU1966 to
the EI3_MCLK pin on the SDP interface.
CRYSTAL OPERATION
The ADAU1962/ADAU1966 evaluation board is shipped
without R49 on the board, effectively disabling the crystal circuit.
For operation with a crystal, install a 150 Ω, 0402 resistor and
remove any jumpers from J5. For permanent use of the crystal,
remove the 0 Ω resistor, R39.
Figure 13. Crystal Circuit Near ADAU1962/ADAU1966
10717-010
10717-011
10717-012
10717-013
Rev. A | Page 6 of 28

Evaluation Board User Guide UG-416
PLL SELECTION
The PLL in the ADAU1962/ADAU1966 is very flexible,
allowing the part to run from a wide range of either MCLK or
LRCLK frequencies. It is also possible to shut the PLL off
altogether and use the part in direct MCLK mode; functionality
with no PLL is limited to 256 × fS.
By default, the ADAU1962/ADAU1966 run from the PLL using
MCLK as the clock source. The MCLK loop filter must be
selected using JP2, as shown in Figure 14.
Figure 14. MCLK Selection for PLL Loop Filter
DLRCLK can be selected as the PLL clock source using the PLL
and Clock Control Register 0, Register 0x00, Bits[7:6]. In this
case, the LRCLK loop filter must be selected, as shown in Figure 15.
If DLRCLK is selected as the PLL clock, there is no need for an
MCLK signal.
Figure 15. LRCLK Selection for PLL Loop Filter
DIGITAL AUDIO CONNECTIONS AND ROUTING
The ADAU1962/ADAU1966 evaluation board has two separate
inputs for digital audio signals: S/PDIF and SDP interface.
The S/PDIF receiver can handle either of two options: COAX
uses the RCA jack, J1, and OPT uses the Toslink jack, U1. The
S/PDIF input is selected using S1, as shown in Figure 16.
Figure 16. S/PDIF Input Selector Switch, SW1
A series of resistors is provided to set the functional mode of the
S/PDIF receiver. By default, the S/PDIF receiver runs in master
mode, 256 × fS, I2S format; consult the data sheet for the S/PDIF
receiver to make changes to the hardware mode.
The jumpers shown in Figure 17 are set for the S/PDIF receiver
to drive the DBCLK and DLRCLK clock ports and the eight
DSDATAx lines of the ADAU1962/ADAU1966. JP22 selects the
input to the buffer; the output of this buffer shows up on the right-
hand column of JP13 to JP20. The pins in the middle column of
these jumpers are connected to the DSDATAx pins of the
ADAU1962/ADAU1966 through the appropriate line termination.
DBCLK and DLRCLK selections are made with JP10 and JP12,
respectively, where the middle pins are connected to the
DBCLK and DLRCLK pins of the ADAU1962/ADAU1966.
Figure 17. S/PDIF Data and Clock Routing
The SDP interface, J6 and J8, make up a standard interconnect
within Analog Devices. They provide for transfer of digital audio,
clocks, and control between boards. For additional information,
see the pinout included in the schematic in Figure 28.
10717-014
10717-015
10717-016
10717-017
Rev. A | Page 7 of 28

UG-416 Evaluation Board User Guide
Figure 18 shows the jumpers configuration for using the SDP
interface connector as the digital audio source. JP22 is set so
that the DSDATA1 source from the SDP interface is driving the
buffer, and this buffer is connected to all eight/six DSDATAx
inputs of the ADAU1962/ADAU1966. JP10 and JP12 are set for
the ADAU1962/ADAU1966 to run in slave mode from clocks
supplied by the SDP interface.
Figure 18. SDP Interface DSDATA1 Distribution
CONNECTING ANALOG AUDIO CABLES
There are two forms of the analog outputs of the ADAU1962/
ADAU1966 evaluation board: differential outputs and single-
ended outputs.
The differential outputs appear on through hole test points as well
as on 25-way, female D-sub connectors. The pinout of these D-sub
connectors follows the professional audio standard for eight
differential signals on a single jack. A single 25-pin male D-sub
to XLR male harness has been provided for testing and evaluation
purposes. These cables are widely available on the open market.
The differential outputs of the ADAU1962/ADAU1966 drive
the connectors directly through a simple 1-pole RC filter and
appropriate ac coupling.
Channel 1 and Channel 2 are also available as single-ended outputs
on a stereo, 3.5 mm stereo jack, J14. The J9 and J10 jumpers assign
the differential outputs of the DAC to either the passive differential
output or the active single-ended filter.
Figure 19 shows J9 and J10 set for the passive differential output
available on the D-sub connector.
Figure 19. Channel 1 and Channel 2 in Passive Differential Output Mode
Figure 20. Channel 1 and Channel 2 in Active Single-Ended Output Mode
Figure 20 shows J9 and J10 set for the active single-ended output
available on the 3.5 mm TRS connector, J14.
USING THE ADAU1962/ADAU1966
When the ADAU1962/ADAU1966 start in standalone mode, it is
operational upon power up.
If the ADAU1962/ADAU1966 are not powered up in
standalone mode, the USBi must be connected to set the
appropriate registers to make the part operational. First, the
ADAU1962/ADAU1966 must be activated using the PLL and
Clock Control 0 register (Address 0x00) by setting the PUP bit
(Bit 0) to 1 for master power-up. Next, using the DAC Control 0
register (Address 0x06) set the MMUTE bit (Bit 0) to 0 for
normal operation. The ADAU1962/ADAU1966 now pass audio
in its default mode: I2S, 256 × fS, slave mode, and CM = 2.25 V.
If different settings are desired, it is recommended to program
the custom settings before unmuting the part.
10717-018
10717-019
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Rev. A | Page 8 of 28

Evaluation Board User Guide UG-416
SCHEMATICS AND ARTWORK
Figure 21. ADAU1962/ADAU1966 Evaluation Board Block Diagram Schematic, Page 1
ADAU1966
DAC Diff Out 3-8 Passive RC 1 pole DAC Diff Out 9-16 Passive RC 1 pole
1 Pole Passive 1 Pole Active
DAC Diff Out 1-2 Passive RC 1 Pole
DAC SE Out 1-2 Active Filter
Power Supply Regulators
5v0 = Switching Supply 3v3 = Linear Supply derived from 5v0
Int Reg
Xistor
DVDD
PLLVDD
AVDD = 5v0 / 3v3
IOVDD = 5v0 / 3v3
Single jumpers for each supply
for current measurement
MCLK Sources
SPDIF
Crystal
DSP Intf EXT In Active OSC
USBi Control port SA_Mode Jumps
COM Port Jumps
PD Jump
SPDIF Receiver
DSP/FPGA Interface
BCLK, LRCLK
SDATA Jumps
with Buffer
12 VDC Input
Optical and Coax In
Allows for Direct
Connect to DUT
SE output on TRS Mini Jack
Diff Outs on d-sub 25
Reset Switch
3v3 for SPDIF Core
IOVDD comes from DUT IOVDD
Control Jumpers
Hardware Mode
Desktop Supply
CM Output on TP
Buffered MCLKO
OP AMP = 9v0 Linear Adjustable
CLKs
CLKs and DATA
3v3 / 2v5
IOVDD and AVDD select using 0R00
24 VDC Input MAX!
10717-021
Rev. A | Page 9 of 28

UG-416 Evaluation Board User Guide
Figure 22. ADAU1962/ADAU1966 Evaluation Board, PLL LF Selection and Internal Regulator Schematic, Page 2
Enable
ADAU1966 Voltage Regulator
MCLK LRCLK
See pages5&6 for jumpers
Stand-Alone Modes
Master SAI Slave SAI
256xFs, PLL
382xFs,PLL
CM=2v25 CM=1v50 I2S TDM TDM4, Pulse TDM8, Pulse TDM16, Pulse TDM8, 50% Duty Cycle
0 1 0 1 0 1 0 1
00 01 10
11
Pin 42 Pin 43 Pin 44 Pin 45
Pins 32:31
C76
0.47uF
C37
C68 C65
C77
C43
0.47uF
C72
0.47uF
C45
0.47uF
C75
C41
C71 C67
C42
C47
C44C53
JP1
JP3
+
C134 10uF
+
C130
10uF
TP66 TP63
TP26
TP21
TP25
TP44
B
C
E
C
Q1
ZX5T953GTA
C36C40
+
C126
10uF
R56
1k50
TP50
TP53
C18
2.2nF NP0
C21
39nF
R25
3k32
BA
JP2
C17
390pF
C20
5.6nF
R27
562R
1 3 5 7 9
2 4 6 8 10
11 13 15 17 19
12 14 16 18 20 2221 2423 2625
27 28
J11
HEADER_28WAY_UNSHROUD
+
C125
10uF
+
C127
10uF
+
C129
10uF
JP11
+
C128
10uF
+
C131
10uF
+
C133
10uF
27 DBCLK 28 DLRCLK 31 DSDATA8 32 DSDATA7 33 DSDATA6 34 DSDATA5 35 DSDATA4 36 DSDATA3 37 DSDATA2 38 DSDATA1
30DGND
21 DGND
19 MCLKO 18 XTALO 17 MCLKI/XTALI 16 PLLVDD
15 LF 14 PLLGND 47 PU/RST
46 SA_MODE
45 CLATCH/ADDR0
44 CCLK/SCL
43 COUT/SDA 42 CDATA/ADDR1
50
DAC1P 51
DAC1N
52
DAC2P 53
DAC2N
54
DAC3P 55
DAC3N
56
DAC4P 57
DAC4N
59
DAC_BIAS1 60
DAC_BIAS2
64
DAC5P 65
DAC5N
66
DAC6P 67
DAC6N
68
DAC7P 69
DAC7N
70
DAC8P 71
DAC8N
72
DAC9P 73
DAC9N
74
DAC10P 75
DAC10N
76
DAC11P 77
DAC11N
78
DAC12P 79
DAC12N
1
DAC_BIAS3 2 DAC_BIAS4
4
DAC13P 5
DAC13N
63
TS_REF 62
CM
40DGND
24
VDRIVE
23
VSENSE
25
VSUPPLY
39
IOVDD
41
DVDD
22
IOVDD
29
DVDD
12
AVDD4
3
AVDD3
58
AVDD2
49
AVDD1
20
DVDD
6
DAC14P 7
DAC14N
8
DAC15P 9
DAC15N
10
DAC16P11
DAC16N
13 AGND4
80 AGND3
61AGND2
48 AGND1
26 DGND
U6
ADAU1966WBSTZ
JP21
R138 10k0
TP57
JP9
JP7
JP4
TP27
TP45 TP71
[2]1966_CDATA/ADDR1
[2]1966_COUT/SDA
[2]1966_CCLK/SCL
[2]1966_CLATCH/ADDR0
[6,9] PU_RST
[3]
DAC1P [3] DAC1N
[3]
DAC2P [3] DAC2N
[3]
DAC3P [3] DAC3N
[3]
DAC4P [3] DAC4N
TS_REF
[4]
DAC5P [4] DAC5N
[4]
DAC6P [4] DAC6N
[4]
DAC7P [4] DAC7N
[4]
DAC8P [4] DAC8N
[4]
DAC9P [4] DAC9N
[4]
DAC10P [4]
DAC10N
[4]
DAC11P [4]
DAC11N
[4]
DAC12P [4]
DAC12N
[4]
DAC13P [4]
DAC13N
[4]
DAC14P [4]
DAC14N
[4]
DAC15P [4]
DAC15N
[4]
DAC16P [4] DAC16N
LF
[6] MCLKI/XTALI
[2]
VDRIVE
[2]
VSENSE
[2]
VSUPPLY
AVDD
IOVDD
[2]
VSENSE
[2]
VSUPPLY
[2]
VDRIVE
[2]
VSENSE
[2]
VSENSE
1966_IOVDD
1966_DVDD
AVDD
PLLVDD
PLLVDD
USBI_CDATA
USBI_CDATA
[6] XTALO
[6] MCLKO
IOVDD
[5] 1966_DSDATA1
[5] 1966_DSDATA2
[5] 1966_DSDATA3
[5] 1966_DSDATA4
[5] 1966_DSDATA8
[5] 1966_DSDATA7
[5] 1966_DSDATA6
[5] 1966_DSDATA5
[5]1966_DLRCLK
[5]1966_DBCLK
SA_MODE
[2]
1966_CLATCH/ADDR0
[2]
1966_COUT/SDA
[2]
1966_CCLK/SCL
[6,7] USBI_CLATCH_A
[6,7] USBI_CCLK
[6,7] USBI_SCL
CM
[2]
1966_AVDD
1966_AVDD
[2]
1966_CDATA/ADDR1
[6,7] USBI_COUT
[6,7] USBI_SDA
[2,6,7] USBI_CDATA
IOVDD
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Evaluation Board User Guide UG-416
Figure 23. ADAU1962/ADAU1966 Evaluation Board, DAC Outputs, CH1 and CH2 Active Buffer and CH1 to CH4 Passive Filters Schematic, Page 3
C100
R115
1k27
TP107
6-
5+
7
O
U7-B
ADA4841-2YRZ
C101
1.0nF
R118
1k27
R114
1k50
R119
1k50
R116
49R9
R117
100k
TP43
+
C102
47uF
C1031.0nF
4
V-
8
V+
U7-C
ADA4841-2YRZ
R92
237R
R91
237R
TP79
TP78
C84
2.7nF
RING
SLEEVE
TIPJ14
R107
1k27
TP103
C96
1.0nF
R108
1k27
R113
1k50
R109
1k50
R110
49R9
R112
100k
+
C98
47uF
C97 1.0nF
R94
237R
R93
237R
TP81
TP80
C85
2.7nF
R98
237R
R97
237R
TP85
TP84
C87
2.7nF
R96
237R
R95
237R
TP83
TP82
C86
2.7nF
2-
3+
1
O
U7-A
ADA4841-2YRZ
+
C91
10uF
+
C90
10uF
+
C89
10uF
+
C88
10uF
R102
49k9R101
49k9
R100
49k9R99
49k9
+
C95
10uF
+
C94
10uF
+
C93
10uF
+
C92
10uF
R106
49k9R105
49k9
R104
49k9R103
49k9
TP101TP100
TP99 TP98
TP97TP93
TP91 TP90
1 2
3 4
5 6
J9
12
3 4
5 6
J10
R159
1k50
R158
1k50
+
C155
10uF
+
C153
10uF
+
C148
10uF
+
C150
10uF
+C156
10uF
C99
9VDD
[2]
DAC1N
[2]
DAC1P
[3] ANALOG_OUT1P
[3]
ANALOG_OUT1N
[3]
VREF
[2]
DAC2N
[2]
DAC2P
[3] ANALOG_OUT2P
[3]
ANALOG_OUT2N
[3]
VREF
[2]
DAC4N
[2]
DAC4P
[2]
DAC3N
[2]
DAC3P
[3]
ANALOG_OUT1N
[3]
ANALOG_OUT1P
[3]
ANALOG_OUT2N
[3]
ANALOG_OUT2P
[4]
OUT4N
[4]
OUT4P
[4]
OUT3N
[4]
OUT3P
[4]
OUT2N
[4]
OUT2P
[4]
OUT1N
[4]
OUT1P
[3]
VREF
10717-023
Rev. A | Page 11 of 28

UG-416 Evaluation Board User Guide
Figure 24. ADAU1962/ADAU1966 Evaluation Board, RC Output Filters and D-Sub 25-Pin Connectors Schematic, Page 4
R30
237R
R31
237R
TP28
TP29
C23
2.7nF
R32
237R
R33
237R
TP30
TP31
C24
2.7nF
R34
237R
R35
237R
TP32
TP33
C25
2.7nF
R36
237R
R37
237R
TP34
TP35
C26
2.7nF
R40
237R
R44
237R
TP39
TP41
C31
2.7nF
R47
237R
R51
237R
TP46
TP48
C38
2.7nF
R54
237R
R57
237R
TP51
TP54
C48
2.7nF
R60
237R
R64
237R
TP58 TP59
C54
2.7nF
R68
237R
R70
237R
TP61 TP62
C61
2.7nF
R74
237R
R76
237R
TP64
TP67
C73
2.7nF
R80
237R
R82
237R
TP69 TP72
C79
2.7nF
R86
237R
R88
237R
TP74 TP76
C82
2.7nF
1
2
3 4
5
6 7
8 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
J7
D- SUB25_ALT_FEMALE_PCMOUNT
1
2
3
4 5
6 7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
J3
D- SUB25_ALT_FEMALE_PCMOUNT
+
C83
10uF
+
C81
10uF
R89
49k9 R87
49k9
+
C80
10uF
+
C78
10uF
R83 49k9 R81
49k9
+
C74
10uF
+
C69
10uF
R77 49k9 R75
49k9
+
C62
10uF
+
C59
10uF
R71
49k9 R69
49k9
+
C55
10uF
+
C51
10uF
R65
49k9 R61
49k9
+
C49
10uF
+
C46
10uF
R58
49k9 R55
49k9
+
C39
10uF
+
C35
10uF
R52
49k9 R48
49k9
+
C32
10uF
+
C30
10uF
R45
49k9 R41
49k9
+
C22
10uF
+
C19
10uF
R29
49k9 R28
49k9
+
C16
10uF
+
C15
10uF
R26
49k9 R23
49k9
+
C14
10uF
+
C13
10uF
R22
49k9 R19
49k9
+
C9
10uF
+
C8
10uF
R8 49k9 R7
49k9
TP89 TP87
TP77 TP75
TP73 TP70
TP68 TP65
TP55 TP52
TP49 TP47
TP42 TP40
TP37 TP24
TP22 TP19
TP18 TP16
TP12 TP11
TP10 TP7
[2]
DAC16N
[2]
DAC16P
[2]
DAC15N
[2]
DAC15P
[2]
DAC14N
[2]
DAC14P
[2]
DAC13N
[2]
DAC13P
[2]
DAC12N
[2]
DAC12P
[2]
DAC11N
[2]
DAC11P
[2]
DAC10N
[2]
DAC10P
[2]
DAC9N
[2]
DAC9P
[2]
DAC8N
[2]
DAC8P
[2]
DAC7N
[2]
DAC7P
[2]
DAC6N
[2]
DAC6P
[2]
DAC5N
[2]
DAC5P
[4]
OUT5P
[4] OUT5N
[4]
OUT6P
[4]
OUT6N
[4]
OUT7P
[4] OUT7N
[4] OUT10N
[4]
OUT10P
[4] OUT9N
[4]
OUT9P
[4]
OUT8N
[4]
OUT8P
[4]
OUT11P
[4]
OUT11N
[4]
OUT12P
[4]
OUT12N
[4]
OUT13P
[4] OUT13N
[4]
OUT14N
[4]
OUT14P
[4]
OUT15P
[4]
OUT15N
[4]
OUT16N
[4]
OUT16P
[4] OUT16P
[4] OUT16N
[4] OUT15P
[4] OUT15N
[4] OUT14P
[4] OUT14N
[4] OUT13P
[4] OUT13N
[4] OUT12P
[4] OUT12N
[4] OUT11P
[4] OUT11N
[4] OUT10P
[4] OUT10N
[4] OUT9P
[4] OUT9N
[4] OUT8P
[4] OUT8N
[4] OUT7P
[4]OUT7N
[4] OUT6P
[4] OUT6N
[4] OUT5P
[4] OUT5N
[3] OUT4P
[3] OUT4N
[3] OUT3P
[3] OUT3N
[3] OUT2P
[3] OUT2N
[3] OUT1P
[3] OUT1N
10717-024
Rev. A | Page 12 of 28

Evaluation Board User Guide UG-416
Figure 25. ADAU1962/ADAU1966 Evaluation Board, BCLK, LRCLK, and SDATA Jumpers and Routing Schematic, Page 5
BA
JP13
BA
JP14
BA
JP15
BA
JP16
BA
JP17
BA
JP18
BA
JP19
BA
JP20
2A
1OE
4
Y
U18
SN74LVC1G125DRLR
A B
JP22
C7
C70 4.7pF
C66 4.7pF
C64 4.7pF
C63 4.7pF
C60 4.7pF C58 4.7pF C57 4.7pF C56 4.7pF C52 2.2pF
C50 2.2pF
R62
33R2
R59
33R2
R63
33R2
R90
68R1
R85
68R1
R84
68R1
R79
68R1
R78
68R1
R73
68R1
R72
68R1
R67
68R1
R66
33R2
C141 2.2pF
R141
33R2
BA
JP12 BA
JP10
[9]
8416_SDATA
[7] INTF_DSDATA1
[7] INTF_DBCLK
[7]
INTF_DLRCLK
[7] INTF_DSDATA8
[7] INTF_DSDATA7
[7] INTF_DSDATA6
[7] INTF_DSDATA5 [7] INTF_DSDATA4 [7] INTF_DSDATA3 [7] INTF_DSDATA2
[9]8416_BCLK
[9]8416_LRCLK
IOVDD
DBCLK
DLRCLK
DSDATA8 DSDATA7 DSDATA6 DSDATA5 DSDATA4 DSDATA3 DSDATA2 DSDATA1
[2] 1966_DBCLK
[2] 1966_DLRCLK
[2] 1966_DSDATA8
[2] 1966_DSDATA7
[2] 1966_DSDATA6 [2] 1966_DSDATA5
[2] 1966_DSDATA4
[2] 1966_DSDATA3
[2] 1966_DSDATA2
[2] 1966_DSDATA1
10717-025
Rev. A | Page 13 of 28

UG-416 Evaluation Board User Guide
Figure 26. ADAU1962/ADAU1966 Evaluation Board, MCLK Source, USBi Interface, CLKOUT Feed, and Reset Generator Schematic, Page 6
MCLK sources CLKOUT Feed
USBi or Aardvark
USBi Interface
MR line comes from USBi Board Reset
Reset
MCLK Source
Power down
12 34 56 78
J5
TP38
1OE
2
GND
3OUTPUT
4
VDD
U5
OSC_CPPFXC7-12.288MHZ_7MMX5MM_SMD
R42
49R9
L7
C33 Y1
12.288MHz
R49
150R
C29 22pF C34 22pF R53
49R9
2A
1OE
4
Y
U4
SN74LVC1G125DRLR
J2
R24
49R9
C111
TP20
1 3 5 7 9
2
4 6 8
10
J12
HEADER_10WAY_POL
R111
3k01 R155
3k01
4VCC 3
MR
1GND 2
RESET
U10
ADM811R
C27
12
3 4
S2
R126
100k
R157
10k0
JP8
R46 10k0
R132
49R9
C124
10pF
R39
0R00
J4
R38
49R9
C28
10pF
R129
49R9
R43
0R00
JP5
R50
1M00
D10 MBR0530T1G
[2]
MCLKI / XTALI
IOVDD
[2]
XTALO [2]
MCLKO
IOVDD
[9]
8416_MCLKI
[6,8]
MR
[2,7] USBI_SCL
[2,7] USBI_SDA
[2,7]USBI_CCLK
[2,7] USBI _CLATCH_A [ 2,7]
USBI_CDATA
IOVDD
[2,9] PU_RST
[6,8]
MR
IOVDD
[7]
EI3_MCLKI
[9] OMCK_FEED
[2,7] USBI_COUT
[7]
USBI_5V00
[7]
EI3_MCLKO
10717-026
Rev. A | Page 14 of 28

Evaluation Board User Guide UG-416
Figure 27. ADAU1962/ADAU1966 Evaluation Board, Level Shift and Clock Direction Control Schematic, Page 7
1VCCA
2DIR 3A1 4A2
5A3 6A4
7A5
8A6 9A7
10 A8 11 GND 12 GND 13
GND 14
B8 15
B7 16
B6 17 B5 18
B4 19
B3 20
B2 21
B122
OE 23
VCCB 24
VCCB
U13
SN74LVCH8T245DBR_8BITLVLSHFT
R137 10k0
R134
10k0
1VCCA 2DIR 3A1 4A2
5A3 6A4 7A5
8A6 9A7
10 A8 11 GND 12GND 13
GND 14
B8 15
B716 B6 17 B5 18
B4 19 B320 B2 21
B1 22
OE 23
VCCB 24
VCCB
U16
SN74LVCH8T245DBR_8BITLVLSHFT
R139
10k0
2A1
3A2
7
B1 6 B2
1
VCCA
8
VCCB
4GND
5DIR U11
SN74LVC2T45DCTR_2BITLVLSHFT
R127
10k0
R146
1k50
R145
3k32
1 2 3 4 5 6 7 8 9
10 11 12
13 14 15
16
R135 33R0
C135
C137
C138
C145
C122
C120
2A
1
OE
4
Y
U14
SN74LVC1G125DRLR
R130 10k0
JP6
C136
C123
2
A
4Y
1
OE
U12
SN74LVC1G126DRLR
R147 49R9
R148 49R9
R152 49R9
R128
49R9
R150 49R9
R151 49R9 TP96
TP95
[2,6]
USBI_COUT
DDVOIDDVOI_
3IE
[8]EI3_DSDATA1 [8] EI3_DSDATA2
[8] EI3_DSDATA3
[8] EI3_DSDATA4 [8] EI3_DSDATA5
[8] EI3_DSDATA6
[8] EI3_DSDATA7
[8] EI3_DSDATA8
EI3_IOVDDIOVDD
IOVDDEI3_IOVDD
[6]
USBI_5V00
EI3_SPI_EN
[5]
INTF_DSDATA8[5]
INTF_DSDATA7[5]
INTF_DSDATA6[5]
INTF_DSDATA5[5]
INTF_DSDATA4[5]
INTF_DSDATA3[5]
INTF_DSDATA2[5]
INTF_DSDATA1
[7,8]
EI3_MCLK
[6]
EI3_MCLKI
[7,8] EI3_MCLK
[7] MCLK_SEL
[7]
MCLK_SEL
EI3_IOVDD
[7]
MCLK_SEL
EI3_IOVDD EI3_IOVDD
[8] EI3_CCLK
[2,6]
USBI_CCLK
[8]EI3_CDATA
[8]EI3_CLATCH_A
[8]EI3_CLATCH_B [8]EI3_CLATCH_C
[2,6]
USBI_CLATCH_A
[2,6]
USBI_CDATA
[6]
EI3_MCLKO
[8]EI3_COUT
USBI_CLATCH_B
USBI_CLATCH_C
R143 49R9
R142
49R9
2SCLA 3SDAA 7
SCLB 6
SDAB
1VCCA8
VCCB
4GND 5
EN
U15
PCA9517DP-T_I2CBUSRPT_LVLTRANS_TSSOP8
R144 10k0
C142
C140
[2,6]
USBI_SCL [2,6]
USBI_SDA
DDVOID
DVOI_3I
E
[8] EI3_SCL
[8] EI3_SDA
1VCCA 2DIR 3A1 4A2 5A3 6A4 7A5 8A6 9A7
10 A8
11 GND
12 GND 13
GND 14
B8 15 B7 16
B6 17 B5 18
B4 19
B3 20 B2 21 B1 22
OE 23
VCCB 24
VCCB
U17
SN74LVCH8T245DBR_8BITLVLSHFT
R149
10k0
R140 10k0
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16
R136 33R0
C146
C139
[5]
INTF_DLRCLK
[5]
INTF_DBCLK
IOVDD
IOVDD
IOVDD
EI3_IOVDD
[8]EI3_DLRCLK0
[8] EI3_DBCLK0
[8] EI3_DBCLK1
[8] EI3_DBCLK2
[8] EI3_DBCLK3
[8]EI3_DLRCLK1
[8]EI3_DLRCLK2
[8]EI3_DLRCLK3
10717-027
Rev. A | Page 15 of 28

UG-416 Evaluation Board User Guide
Figure 28. ADAU1962/ADAU1966 Evaluation Board, SDP Interface Connectors Schematic, Page 8
EI3 1A EI3 1B
SPORT1_D0
SPORT1_D1
SPORT1_CLK
SPORT1_FS
SPORT0_D1 SPORT0_D0
SPORT0_FS
SPORT0_CLK
SPORT3_D0
SPORT3_D1
SPORT3_CLK
SPORT3_FS
SPORT2_D1 SPORT2_D0
SPORT2_FS
SPORT2_CLK
SPI0_SEL_A
SPI0_MISO
SPI0_MOSI
SPI0_CLK
SDA0'
SCL0'SDA0'
SCL0'
RESET_OUT' RESET_OUT'
DAU_MCLK
SPI0_SEL_B
SPI0_SEL_C
R133 OPEN 1
2 3
4 5 6 7 8
9
10 11
12 13
14
15 16
17
18 19
20 21
22 23
24 25
26 27
28
29 30
31 32
33
34 35
36
37 38 39
40 41
42
43 44
45
46 47
48
49 50
51 52
53
54 55
56 57 58
59
1
606
62
63
64
65
66 67
68 69
70
71
72 73
74
75
76
77
78
79
80
81
82
83 84
85
86 87
88
89 90
91 92
93
94
95
96 97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
J6
HIROSE_FX8-120S-SV(21)_SOCKET
1 2
3 4
5
6
7
8
9
10 11 12
13
14 15
16 17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
160
6
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86 87
88 89 90
91 92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
J8
HIROSE_FX8-120S-SV(21)_SOCKET
R156 OPEN
D9
Schottky
R131 49R9
+
C132
47uF
EI3_IOVDD
5V0DD 5V0DD
EI3_IOVDD
[7]
EI3_SCL[7]
EI3_SDA
[7]
EI3_DSDATA1
[7] EI3_DSDATA2
[7]
EI3_DSDATA3
[7] EI3_DSDATA4
[7]
EI3_DSDATA5
[7] EI3_DSDATA6
[7]
EI3_DSDATA7
[7] EI3_DSDATA8
[7]
EI3_CLATCH_A [7]
EI3_CDATA
[7]
EI3_CCLK
[7]
EI3_COUT
[6] MR
[7]
EI3_DLRCLK0
[7]
EI3_DBCLK0
[7]
EI3_DLRCLK1 [7]
EI3_DLRCLK2
[7]
EI3_DLRCLK3
[7]
EI3_DBCLK1
[7]
EI3_DBCLK2
[7]
EI3_DBCLK3
[7]
EI3_MCLK
[7]EI3_CLATCH_B
[7] EI3_CLATCH_C
10717-028
Rev. A | Page 16 of 28

Evaluation Board User Guide UG-416
Figure 29. ADAU1962/ADAU1966 Evaluation Board, S/PDIF Receiver Schematic, Page 9
Error
High
Norm
On Off
RERR
NVERR
ERRORSEMPHPH DET RATE
Valid Audio
>88kHz
MASTER
SLAVE
SERIAL PORT Control
128xFs
256xFs
RMCK Freq|-------- SERIAL PORT Format -------|
SFSEL [1:0]
00 = LJ 24bit
01 = I2S 24bit
10 = RJ 24bit
11 = Direct AES
1 0
1 0
SFSEL1 SFSEL0
C6
10nF
C5
10nF
C12
C4
L4
D4
Red Diffused
R3
392R
D3
Green Diffused
R2
392R
L1
C110
11A 2
1Y
U3-A
74HC04D-T
32A 4
2Y
U3-B
74HC04D-T
53A 6
3Y
U3-C
74HC04D-T
4RXP0 5RXN
8FILT
6
VA
23
VD
26
SDOUT 28
OLRCK 27
OSCLK 24
RMCK
10 RXSEL1
11 RXSEL0
12 TXSEL1
13 TXSEL0
19
C18
U17
RCBL 14
NV/RERR 15
AUDIO
3RXP1 2RXP2
1RXP3
20
TX
16
96KHZ
21
VL
9RST
25
OMCK
7
AGND
22
DGND
U2
CS8416
C2 22nF
C3 1.0nF
R6
3k01
C11
R125
47k5
94A 8
4Y
U3-D
74HC04D-T
11 5A 10
5Y
U3-E
74HC04D-T
13 6A 12
6Y
U3-F
74HC04D-T
D2
Yellow Diffused
R1
392R
R11 150R
R12
150R
R21
150R
R10
150R
+
C10
10uF
Default
RS6
47k5
Default
RS5
47k5
2
GND
3
DVDD
1
OUT
U1
TORX147L(FT)
L3
C112
R4 10k0
12
3
45 6
S1
DPDT Slide
J1
CTP-021A-S-YEL
R5
75R0
R20 10k0
R9 10k0
Default
RS2
47k5
Default
RS4 47k5
Default
RS1 47k5
Default
RS3
47k5
Default
RS7 47k5
IOVDD
[5]
8416_SDATA[5] 8416_LRCLK[5]
8416_BCLK [6]
8416_MCLKI
IOVDD
3V3DD
[2,6]
PU_RST
IOVDD
IOVDDIOVDD
IOVDD
3V3DD
[6]
OM CK_FEED
10717-029
Rev. A | Page 17 of 28

UG-416 Evaluation Board User Guide
Figure 30. ADAU1962/ADAU1966 Evaluation Board, Power Supply Schematic, Page 10
3v3 Linear Supply
5v0Switching Supply
+12VDC MAX
GND
op amp supply = 9v
It is very important
that each load onlyhave
one0R00 installed
Plane decoupling
C117
C116
C114
47uF
C108C105
+
C119
47uF
D1
TP88
TP2
L2
600 Ohm @ 100 MHz
L5
600 Ohm@ 100 MHz
C1
+
C107
47uF
+
C118
47uF
TP8
TP9
R13
475R
D5
Green Diffused
R18
475R
D6
Green Diffused
TP60 TP86TP92TP5TP1TP3 TP17 TP6 TP4 TP13 TP56 TP23 TP94 TP36
2 1
3
J13
R124
243R
+
C115
10uF
3
OUT
1
ADJ
2IN
U9
LM317MDT
R123
402R
+
C151
100uF
C149C147
L8
600 Ohm @ 100 MHz
+
C144
47uF
7GND
8IN
6GND
4
ADJ
1
OUT
2GND
3GND
5ON/OFF
U19
R153
178k
R154
27k4
7GND
8IN
6SD
4
FB
1
SWITCH
2
BOOST
3
BIAS
5COMP
U8
ADP3050ARZ
C106
68nF
C104
390pF
R120
1k15
R121
10k2
R122
32k4
D8
BAT54T1G
C109
0.47uF
C113
47uF
1 2
L6
22uH
MSS12778-223MLB
D7
1N5819HW-7-F
R14
0R00
R15
OPEN
R16
OPEN
R17
0R00
C152 C154 C121 C143
TP15
TP14
TP106TP105TP102TP104
5V0DD
3V3DD
+12VDC
3V3DD
9VDD
5V0DD
AVDD
IOVDD
IOVDD
AVDD
10717-030
Rev. A | Page 18 of 28

Evaluation Board User Guide UG-416
Figure 31. ADAU1962/ADAU1966 Evaluation Board, Top Assembly
10717-031
Rev. A | Page 19 of 28

UG-416 Evaluation Board User Guide
Figure 32. ADAU1962/ADAU1966 Evaluation Board, Top Layer Copper
10717-032
Rev. A | Page 20 of 28