Analog Devices ADV8003 User manual

ADV8003
Video Signal Processor with Motion Adaptive De-
interlacing, Scaling, Bitmap OSD, Dual HDMI Tx
and Video Encoder
HARDWARE MANUAL
Rev. B
August 2013

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TABLE OF CONTENTS
Understanding the ADV8003 Hardware Manual ............................................................................................................ 10
Description of the Hardware Manual..........................................................................................................................................10
Disclaimer .......................................................................................................................................................................................10
Trademark and Service Mark Notice...........................................................................................................................................10
Number Notations .........................................................................................................................................................................10
Register Access Conventions ........................................................................................................................................................10
Acronyms and Abbreviations........................................................................................................................................................10
Field Function Description ...........................................................................................................................................................13
References........................................................................................................................................................................................14
1. Introduction to the ADV8003................................................................................................................................. 15
1.1. Overview..........................................................................................................................................................................15
1.1.1. Digital Video Input.............................................................................................................................................................16
1.1.2. Flexible Digital Core...........................................................................................................................................................17
1.1.3. Video Signal Processor.......................................................................................................................................................17
1.1.4. Bitmap On Screen Display.................................................................................................................................................18
1.1.5. External DDR2 Memory....................................................................................................................................................19
1.1.6. HDMI Transmitter..............................................................................................................................................................19
1.1.7. Video Encoder.....................................................................................................................................................................19
1.2. Main Features of the ADV8003 ....................................................................................................................................19
1.2.1. Video Signal Processor.......................................................................................................................................................19
1.2.1.1. Primary VSP ..........................................................................................................................................................................................19
1.2.1.2. Secondary VSP ......................................................................................................................................................................................20
1.2.2. OSD.......................................................................................................................................................................................20
1.2.3. Video Encoder.....................................................................................................................................................................20
1.2.4. HDMI 1.4 Transmitter .......................................................................................................................................................20
1.3. ADV8003 Functional Block Diagram..........................................................................................................................21
1.4. ADV8003 Pinouts...........................................................................................................................................................22
1.5. Protocol for Main I2C Port ............................................................................................................................................67
1.6. Configuring the ADV8003............................................................................................................................................68
2. ADV8003 Top Level Control .................................................................................................................................. 69
2.1. ADV8003 Modes of Operation.....................................................................................................................................70
2.1.1. Selecting a Mode.................................................................................................................................................................71
2.1.2. Mode 1..................................................................................................................................................................................71
2.1.3. Mode 2..................................................................................................................................................................................73
2.1.4. Mode 3..................................................................................................................................................................................74
2.1.5. Mode 4..................................................................................................................................................................................75
2.1.6. Mode 5..................................................................................................................................................................................76
2.1.7. Mode 6..................................................................................................................................................................................77
2.1.8. Mode 7..................................................................................................................................................................................78
2.1.9. Mode 8..................................................................................................................................................................................79
2.1.10. Mode 9 - Bypass ..................................................................................................................................................................80
2.1.11. Mode 10 – Picture in Picture (PiP) (External OSD Less Than 720p)..........................................................................81
2.1.12. Mode 11 – PIP (External OSD Greater Than or Equal To 720p) .................................................................................82
2.1.13. Mode 12 – Dual Zone OSD ...............................................................................................................................................83

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2.1.14. Mode 13 – OSD from HDMI RX .....................................................................................................................................84
2.1.15. Mode 14 – Handling Triple Inputs ...................................................................................................................................85
2.2. ADV8003 Top Level Overview .....................................................................................................................................85
2.2.1. Video Muxing......................................................................................................................................................................85
2.2.2. Digital Video Input.............................................................................................................................................................89
2.2.2.1. Video TTL Input ...................................................................................................................................................................................90
2.2.2.2. EXOSD TTL Input................................................................................................................................................................................90
2.2.2.3. TTL Output............................................................................................................................................................................................91
2.2.2.4. Serial Video Rx ......................................................................................................................................................................................93
2.2.2.5. Primary Input Channel........................................................................................................................................................................93
2.2.2.6. Secondary Input Channel....................................................................................................................................................................100
2.2.2.7. RX Input Channel.................................................................................................................................................................................105
2.2.3. Updither Configuration.....................................................................................................................................................106
2.2.4. Clock Configuration...........................................................................................................................................................106
2.2.4.1. PVSP Output Timing............................................................................................................................................................................111
2.2.4.2. SVSP Output Timing............................................................................................................................................................................111
2.2.4.3. Frame Tracking .....................................................................................................................................................................................112
2.2.5. DDR2 Interface ...................................................................................................................................................................113
2.2.5.1. DDR2 Configuration............................................................................................................................................................................113
2.2.5.2. DDR2 Bandwidth and Memory Selection ........................................................................................................................................115
2.2.5.3. Single DDR2 Memory Configuration................................................................................................................................................117
2.2.5.4. DDR2 Loopback Test ...........................................................................................................................................................................117
2.2.6. I2C Auto Increment.............................................................................................................................................................118
2.2.7. SPI Loop Through ..............................................................................................................................................................119
2.2.8. VBI Data Insertion .............................................................................................................................................................119
2.2.8.1. Extraction Overview ............................................................................................................................................................................119
2.2.8.2. Ancillary Data Extraction....................................................................................................................................................................120
2.2.8.3. SPI Data Extraction ..............................................................................................................................................................................121
2.2.8.4. VBI Data Delay .....................................................................................................................................................................................121
2.2.9. Resets ....................................................................................................................................................................................122
2.2.10. Image Processing Colorimetry Breakdown ....................................................................................................................125
2.2.11. AV-Codes.............................................................................................................................................................................125
2.2.12. Color Space Conversion.....................................................................................................................................................130
2.2.12.1. Primary Input Channel CSC.........................................................................................................................................................130
2.2.12.2. Secondary Input Channel CSC.....................................................................................................................................................133
2.2.12.3. RX Input Channel CSC..................................................................................................................................................................136
2.2.12.4. HDMI Transmitter CSCs...............................................................................................................................................................139
2.2.13. ADV8003 Silicon Revision ................................................................................................................................................142
2.2.14. System Configuration.........................................................................................................................................................143
3. Video Signal Processing .......................................................................................................................................... 144
3.1. Introduction ....................................................................................................................................................................144
3.2. Primary VSP ....................................................................................................................................................................144
3.2.1. Introduction to PVSP.........................................................................................................................................................144
3.2.1.1. Autoconfiguration ................................................................................................................................................................................146
3.2.1.2. Customized Input/Output Video Format Configuration ...............................................................................................................148
3.2.1.3. Field/Frame Buffer Number................................................................................................................................................................149
3.2.1.4. Field/Frame Buffer Address and Size.................................................................................................................................................149
3.2.1.5. Frame Latency .......................................................................................................................................................................................151
3.2.1.6. Game Mode ...........................................................................................................................................................................................153

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3.2.1.7. Low Latency Mode ...............................................................................................................................................................................154
3.2.1.8. Freezing Output Video.........................................................................................................................................................................155
3.2.1.9. Progressive Cadence Detection ..........................................................................................................................................................155
3.2.2. PVSP Video Input Module.................................................................................................................................................156
3.2.2.1. VIM Cropper.........................................................................................................................................................................................156
3.2.2.2. Horizontal Down Scaler ......................................................................................................................................................................158
3.2.2.3. Scaler Interpolation Mode...................................................................................................................................................................158
3.2.2.4. Scaler Controls ......................................................................................................................................................................................159
3.2.2.5. Pixel Packer............................................................................................................................................................................................159
3.2.3. PVSP Video Output Module .............................................................................................................................................160
3.2.3.1. Pixel Unpacker ......................................................................................................................................................................................161
3.2.3.2. VOM Cropper .......................................................................................................................................................................................161
3.2.3.3. Motion Detection..................................................................................................................................................................................163
3.2.3.4. Low Angle De-interlacing....................................................................................................................................................................164
3.2.3.5. Cadence Detection ...............................................................................................................................................................................164
3.2.3.6. CUE Correction ....................................................................................................................................................................................166
3.2.3.7. Random Noise Reduction ...................................................................................................................................................................166
3.2.3.8. Mosquito Noise Reduction..................................................................................................................................................................167
3.2.3.9. Block Noise Reduction.........................................................................................................................................................................168
3.2.3.10. Sharpness Enhancement................................................................................................................................................................170
3.2.3.11. Scaler ................................................................................................................................................................................................170
3.2.3.12. Panorama Mode..............................................................................................................................................................................172
3.2.3.13. Output Port......................................................................................................................................................................................173
3.2.3.14. Demo Function...............................................................................................................................................................................177
3.2.3.15. Progressive to Interlaced Converter.............................................................................................................................................179
3.2.3.16. Automatic Contrast Enhancement ..............................................................................................................................................180
3.3. Secondary VSP................................................................................................................................................................180
3.3.1. Introduction to SVSP .........................................................................................................................................................180
3.3.1.1. Autoconfiguration ................................................................................................................................................................................182
3.3.1.2. Customized Input/Output Video Format Configuration ...............................................................................................................184
3.3.1.3. Frame Buffer Number..........................................................................................................................................................................185
3.3.1.4. Frame Buffer Address and Size ...........................................................................................................................................................185
3.3.1.5.Frame Latency.......................................................................................................................................................................................187
3.3.1.6. Freezing Output Video.........................................................................................................................................................................189
3.3.2. SVSP Video Input Module (VIM) ....................................................................................................................................189
3.3.2.1. VIM Cropper.........................................................................................................................................................................................189
3.3.2.2. Scaler.......................................................................................................................................................................................................191
3.3.2.3. Scaler Interpolation Mode...................................................................................................................................................................192
3.3.2.4. VIM Miscellaneous Control................................................................................................................................................................192
3.3.2.5. Panorama Mode....................................................................................................................................................................................193
3.3.2.6. Pixel Packer............................................................................................................................................................................................194
3.3.3. SVSP Video Output Module..............................................................................................................................................194
3.3.3.1. Pixel Unpacker ......................................................................................................................................................................................195
3.3.3.2. VOM Cropper .......................................................................................................................................................................................195
3.3.3.3. Output Port............................................................................................................................................................................................197
3.3.3.4. DDR Bypass Mode................................................................................................................................................................................201
3.3.3.5. Progressive to Interlaced Converter in SVSP....................................................................................................................................201
3.4. VSP Register Access Protocols ......................................................................................................................................202
3.4.1. Bootup Protocol ..................................................................................................................................................................202
3.4.2. Reboot Protocol ..................................................................................................................................................................203

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3.4.3. Gentle Reboot Protocol......................................................................................................................................................205
3.4.4. VOM Set Protocol...............................................................................................................................................................206
3.4.5. Free Access Protocol ...........................................................................................................................................................206
3.5. Progressive to Interlaced Conversion ..........................................................................................................................207
4. On Screen Display ................................................................................................................................................... 208
4.1. Introduction ....................................................................................................................................................................208
4.1.1. Features ................................................................................................................................................................................208
4.1.2. OSD System Application Diagram ...................................................................................................................................208
4.1.3. Typical OSD Component Sizes .........................................................................................................................................209
4.2. Architecture Overview...................................................................................................................................................209
4.2.1. Introduction ........................................................................................................................................................................209
4.2.2. Top Level Diagram .............................................................................................................................................................209
4.2.3. OSD Blending......................................................................................................................................................................210
4.2.4. External Alpha Blending....................................................................................................................................................211
4.2.5. OSD Core .............................................................................................................................................................................211
4.2.5.1. OSD Core Region Definition..............................................................................................................................................................212
4.2.5.2. OSD Color Space ..................................................................................................................................................................................213
4.2.6. OSD Timers .........................................................................................................................................................................213
4.2.7. OSD Scaler...........................................................................................................................................................................217
4.2.8. OSD Master/Slave SPI Interface .......................................................................................................................................217
4.2.8.1. Overview ................................................................................................................................................................................................218
4.2.8.2. SPI Slave Interface.................................................................................................................................................................................223
4.2.8.3. SPI Master Interface .............................................................................................................................................................................225
4.2.9. OSD Initialization...............................................................................................................................................................226
5. Serial Video Receiver .............................................................................................................................................. 227
5.1. + 5 V Detect.....................................................................................................................................................................227
5.2. TMDS Clock Activity Detection...................................................................................................................................228
5.3. Clock and Data Termination Control..........................................................................................................................229
5.4. AV Mute Status ...............................................................................................................................................................229
5.5. Deep Color Mode Support ............................................................................................................................................229
5.6. Video FIFO......................................................................................................................................................................230
5.7. Pixel Repetition...............................................................................................................................................................232
5.8. Sync Signal Polarity Readbacks ....................................................................................................................................233
5.9. InfoFrame Registers .......................................................................................................................................................235
5.9.1. InfoFrame Collection Mode..............................................................................................................................................235
5.9.2. InfoFrame Checksum Error Flags ....................................................................................................................................235
5.9.3. AVI InfoFrame Registers ...................................................................................................................................................236
5.9.4. SPD InfoFrame Registers...................................................................................................................................................237
5.9.5. MPEG Source InfoFrame Registers..................................................................................................................................238
5.9.6. Vendor Specific InfoFrame Registers...............................................................................................................................238
5.10. Packet Registers ..............................................................................................................................................................239
5.10.1. ISRC Packet Registers.........................................................................................................................................................239
5.10.2. Gamut Metadata Packets ...................................................................................................................................................241
5.11. Customizing Packet/InfoFrame Storage Registers.....................................................................................................242
5.12. HDMI Section Reset Strategy .......................................................................................................................................244
6. HDMI Transmitter .................................................................................................................................................. 245

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6.1. General Controls ............................................................................................................................................................246
6.2. Reset Strategy ..................................................................................................................................................................247
6.3. HDMI DVI Selection .....................................................................................................................................................248
6.4. AV Mute ...........................................................................................................................................................................248
6.5. Source Product Description InfoFrame ......................................................................................................................249
6.6. Spare Packets ...................................................................................................................................................................250
6.7. System Monitoring .........................................................................................................................................................252
6.7.1. General Status and Interrupts ...........................................................................................................................................252
6.8. EDID/HDCP Controller Status ....................................................................................................................................252
6.9. EDID/HDCP Controller Error Codes .........................................................................................................................253
6.10. Video Setup .....................................................................................................................................................................253
6.10.1. Input Format........................................................................................................................................................................253
6.10.2. Video Mode Detection.......................................................................................................................................................254
6.10.3. Pixel Repetition...................................................................................................................................................................255
6.10.4. Video Related Packets and InfoFrames............................................................................................................................256
6.10.5. AVI InfoFrame ....................................................................................................................................................................256
6.10.6. MPEG InfoFrame ...............................................................................................................................................................257
6.10.7. Gamut Metadata .................................................................................................................................................................258
6.11. Audio Setup.....................................................................................................................................................................260
6.11.1. Audio Architecture .............................................................................................................................................................260
6.11.2. Audio Configuration ..........................................................................................................................................................261
6.11.2.1. I2S Audio..........................................................................................................................................................................................263
6.11.2.2. SPDIF Audio....................................................................................................................................................................................270
6.11.2.3. DSD Audio.......................................................................................................................................................................................271
6.11.2.4. HBR Audio.......................................................................................................................................................................................271
6.11.3. N and CTS Parameters.......................................................................................................................................................272
6.11.3.1. N Parameter.....................................................................................................................................................................................273
6.11.3.2. CTS Parameter................................................................................................................................................................................273
6.11.3.3. Recommended N and Expected CTS Values..............................................................................................................................273
6.11.4. Audio Sample Packets ........................................................................................................................................................275
6.11.5. Audio InfoFrame.................................................................................................................................................................280
6.11.6. ACP Packet ..........................................................................................................................................................................280
6.11.7. ISRC Packet .........................................................................................................................................................................281
6.12. EDID Handling...............................................................................................................................................................283
6.12.1. Reading the EDID...............................................................................................................................................................283
6.12.2. EDID Definitions................................................................................................................................................................283
6.12.3. Additional Segments ..........................................................................................................................................................284
6.12.4. edid_tries Control...............................................................................................................................................................285
6.12.5. EDID Reread Control.........................................................................................................................................................285
6.13. HDCP Handling .............................................................................................................................................................285
6.13.1. One Sink and No Upstream Devices................................................................................................................................285
6.13.2. Multiple Sinks and No Upstream Devices.......................................................................................................................286
6.13.3. Software Implementation ..................................................................................................................................................288
6.13.4. AV Mute ...............................................................................................................................................................................290
6.14. Audio Return Channel...................................................................................................................................................290
6.15. Charge Injection Settings ..............................................................................................................................................291
7. Consumer Electronics Control ............................................................................................................................... 293

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7.1. Main Controls .................................................................................................................................................................294
7.2. CEC Transmit Section....................................................................................................................................................294
7.3. CEC Receive Section ......................................................................................................................................................296
7.3.1. Logical Address Configuration .........................................................................................................................................296
7.3.2. Receive Buffers ....................................................................................................................................................................297
7.3.3. CEC Message Reception Overview ..................................................................................................................................300
7.4. Antiglitch Filter Module ................................................................................................................................................301
7.5. Typical Operation Flow .................................................................................................................................................302
7.5.1. Initializing CEC Module....................................................................................................................................................302
7.5.2. Using CEC Module as Initiator.........................................................................................................................................302
7.5.3. Using CEC Module as Follower........................................................................................................................................304
7.6. Low Power CEC Message Monitoring .........................................................................................................................305
8. Video Encoder ......................................................................................................................................................... 307
8.1. Introduction ....................................................................................................................................................................307
8.2. Input Configuration .......................................................................................................................................................307
8.3. Output Configuration....................................................................................................................................................310
8.4. Additional Design Features...........................................................................................................................................312
8.4.1. Output Oversampling ........................................................................................................................................................312
8.4.2. Subcarrier Frequency Lock (SFL) Mode ........................................................................................................................313
8.4.3. SD VCR FF/RW Synchronization.....................................................................................................................................313
8.4.4. Vertical Blanking Interval..................................................................................................................................................314
8.4.5. SD Subcarrier Frequency Control ....................................................................................................................................314
8.4.5.1. Programming the FSC .........................................................................................................................................................................315
8.4.6. SD Noninterlaced Mode (240p/288p)..............................................................................................................................315
8.4.7. Filters ....................................................................................................................................................................................315
8.4.7.1. SD Filters................................................................................................................................................................................................315
8.4.7.2. ED/HD Filters .......................................................................................................................................................................................318
8.4.8. ED/HD Test Pattern Generator.........................................................................................................................................319
8.4.9. Color Space Conversion Matrix........................................................................................................................................321
8.4.10. ED/HD Manual CSC Matrix Adjust Feature...................................................................................................................321
8.4.10.1. Programming the CSC Matrix......................................................................................................................................................322
8.4.11. SD Luma and Color Scale Control ...................................................................................................................................322
8.4.12. SD Hue Adjust Control ......................................................................................................................................................324
8.4.13. SD Brightness Detect..........................................................................................................................................................325
8.4.14. SD Brightness Control .......................................................................................................................................................325
8.4.15. Double Buffering ................................................................................................................................................................326
8.4.15.1. ED/HD Doubling Buffering..........................................................................................................................................................326
8.4.15.2. SD Doubling Buffering ..................................................................................................................................................................326
8.4.16. Programmable DAC Gain Control...................................................................................................................................327
8.4.17. Gamma Correction.............................................................................................................................................................329
8.4.17.1. ED/HD Gamma Correction .........................................................................................................................................................330
8.4.17.2. SD Gamma Correction..................................................................................................................................................................331
8.4.18. ED/HD Sharpness Filter and Adaptive Filter Controls..................................................................................................332
8.4.18.1. ED/HD Sharpness Filter Mode.....................................................................................................................................................332
8.4.18.2. ED/HD Adaptive Filters.................................................................................................................................................................334
8.4.18.3. ED/HD Adaptive Filter Modes .....................................................................................................................................................336
8.4.18.4. ED/HD Sharpness Filter and Adaptive Filter Application Examples......................................................................................337

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8.4.19. SD Digital Noise Reduction ..............................................................................................................................................339
8.4.19.1. Coring Gain Border .......................................................................................................................................................................340
8.4.19.2. Coring Gain Data ...........................................................................................................................................................................340
8.4.19.3. DNR Threshold...............................................................................................................................................................................341
8.4.19.4. Border Area .....................................................................................................................................................................................341
8.4.19.5. Block Size Control ..........................................................................................................................................................................342
8.4.19.6. DNR Input Select Control.............................................................................................................................................................342
8.4.19.7. DNR Mode Control........................................................................................................................................................................342
8.4.19.8. DNR Block Offset Control............................................................................................................................................................343
8.4.19.9. SD Active Video Edge Control......................................................................................................................................................343
8.5. Vertical Blanking Interval..............................................................................................................................................345
8.6. DAC Configurations ......................................................................................................................................................346
8.6.1. Voltage Reference................................................................................................................................................................346
8.6.2. Video Output Buffer and Optional Output Filter ..........................................................................................................346
9. Interrupts................................................................................................................................................................. 349
9.1. Interrupt Pins ..................................................................................................................................................................349
9.1.1. Interrupt Duration..............................................................................................................................................................349
9.1.2. Storing Masked Interrupts.................................................................................................................................................350
9.2. Serial Video Rx Interrupts.............................................................................................................................................350
9.2.1. Introduction ........................................................................................................................................................................350
9.2.2. Interrupt Architecture Overview......................................................................................................................................354
9.2.2.1. Multiple Interrupt Events ....................................................................................................................................................................355
9.2.3. Serial Video Interrupts Validity Checking Process ........................................................................................................355
9.3. VSP and OSD Section ....................................................................................................................................................355
9.3.1. Interrupt Architecture Overview......................................................................................................................................355
9.4. HDMI Tx core.................................................................................................................................................................356
9.4.1. Introduction ........................................................................................................................................................................356
9.4.2. Interrupt Architecture Overview......................................................................................................................................356
9.4.3. HDMI Tx Interrupt Polarity..............................................................................................................................................357
Appendix A........................................................................................................................................................................ 358
PCB Layout Recommendations....................................................................................................................................................358
Analogue/Digital Video Interface Outputs......................................................................................................................................358
External DDR2 Memory Requirements...........................................................................................................................................358
Power Supply Bypassing .....................................................................................................................................................................359
General Digital Inputs and Outputs .................................................................................................................................................360
XTAL and Load Cap Value Selection................................................................................................................................................360
Encoder Component Placement .......................................................................................................................................................361
HDMI Transmitter Component Placement.....................................................................................................................................361
Power Supply Design and Sequencing..............................................................................................................................................361
Appendix B........................................................................................................................................................................ 363
ADV8003 Evaluation Board Schematics.....................................................................................................................................363
Appendix C ....................................................................................................................................................................... 393
ADV8003 Evaluation Board Layout ............................................................................................................................................394
Appendix D ....................................................................................................................................................................... 402
Package Outline Drawing..............................................................................................................................................................402
Appendix E........................................................................................................................................................................ 403
Unused Pin List ..............................................................................................................................................................................403

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Appendix F ........................................................................................................................................................................ 416
Pixel Input and Output Formats...................................................................................................................................................416
List of Figures.................................................................................................................................................................... 431
List of Tables ..................................................................................................................................................................... 435
List of Equations ............................................................................................................................................................... 437
Revision History ............................................................................................................................................................... 438

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UNDERSTANDING THE ADV8003 HARDWARE MANUAL
DESCRIPTION OF THE HARDWARE MANUAL
This manual provides a detailed description of the functionality and features supported by the ADV8003.
DISCLAIMER
The information contained in this document is proprietary of Analog Devices Inc. (ADI). This document must not be made available to
anybody other than the intended recipient without the written permission of ADI.
The content of this document is believed to be correct. If any errors are found within this document or, if clarification is needed, contact
the authors at [e-mail].
TRADEMARK AND SERVICE MARK NOTICE
The Analog Devices logo is a registered trademark of Analog Devices, Inc. All other brand and product names are trademarks or service
marks of their respective owners.
NUMBER NOTATIONS
Notation Description
bit N
Bits are numbered in little endian format, that is, the least
significant bit of a number is referred to as Bit 0
V[X:Y] Bit field representation covering bit X to Y of a value or a field V
0xNN Hexadecimal (base-16) numbers are preceded by the prefix‘0x’
0bNN Binary (base-2) numbers are preceded by the prefix‘0b’
NN
Decimal (base-10) are represented using no additional prefixes
or suffixes
REGISTER ACCESS CONVENTIONS
Mode Description
R/W Memory location has read and write access.
R Memory location has read access only. A read always returns 0
unless specified otherwise.
W Memory location has write access only.
ACRONYMS AND ABBREVIATIONS
This is a list of common acronyms and abbreviations found in Analog Devices Hardware Manuals.
Acronym/Abbreviation Description
ACP Audio Content Protection
ACR Audio Clock Regeneration
ADC Analog to Digital Converter
AFE Analog Front End
AGC Automatic Gain Control
Ainfo HDCP register. Refer to HDCP documentation.
AKSV HDCP Transmitter Key Selection Vector. Refer to HDCP documentation.
An 64-bit pseudo-random value generated by HDCP cipher function of device A
ARC Audio Return Channel
AUD_IN Audio Input Pin
AVI Auxiliary Video Information
Aux Auxiliary
Bcaps HDCP register. Refer to HDCP documentation.