Analog Devices ADV8005 Quick user guide

ADV8005 Hardware Reference Manual
UG-707
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: [phone] • Fax: [phone] • www.analog.com
ADV8005 Functionality and Features
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS. Rev. A | Page 1 of 317

UG-707 ADV8005 Hardware Reference Manual
TABLE OF CONTENTS
Understanding the ADV8005 Hardware Manual............................................................................................................ 10
Description of the Hardware Manual..........................................................................................................................................10
Disclaimer .......................................................................................................................................................................................10
Trademark and Service Mark Notice...........................................................................................................................................10
Number Notations..........................................................................................................................................................................10
Register Access Conventions ........................................................................................................................................................10
Acronyms and Abbreviations .......................................................................................................................................................10
Field Function Description ...........................................................................................................................................................13
References........................................................................................................................................................................................14
1. Introduction to the ADV8005 ................................................................................................................................ 15
1.1. Overview..........................................................................................................................................................................15
1.1.1. Digital Video Input .............................................................................................................................................................16
1.1.2. Flexible Digital Core...........................................................................................................................................................17
1.1.3. Video Signal Processor.......................................................................................................................................................17
1.1.4. Bitmap On Screen Display.................................................................................................................................................18
1.1.5. External DDR2 Memory....................................................................................................................................................19
1.1.6. HDMI Transmitter .............................................................................................................................................................19
1.1.7. Video Encoder.....................................................................................................................................................................19
1.1.8. Digital Video Output..........................................................................................................................................................19
1.2. Main Features of the ADV8005 ....................................................................................................................................20
1.2.1. Video Signal Processor.......................................................................................................................................................20
1.2.1.1. Primary VSP ..........................................................................................................................................................................................20
1.2.1.2. Horizontal Pre-Scaler...........................................................................................................................................................................20
1.2.1.3. Secondary VSP ......................................................................................................................................................................................20
1.2.2. OSD.......................................................................................................................................................................................20
1.2.3. Video Encoder.....................................................................................................................................................................21
1.2.4. HDMI 1.4 Transmitter .......................................................................................................................................................21
1.2.5. Additional Features.............................................................................................................................................................21
1.3. Protocol for Main I2C Port ............................................................................................................................................23
1.4. Configuring the ADV8005............................................................................................................................................24
2. ADV8005 Top Level Control .................................................................................................................................. 25
2.1. ADV8005 Modes of Operation.....................................................................................................................................26
2.1.1. Selecting a Mode .................................................................................................................................................................27
2.1.2. Mode 1..................................................................................................................................................................................28
2.1.3. Mode 2..................................................................................................................................................................................29
2.1.4. Mode 3..................................................................................................................................................................................30
2.1.5. Mode 4..................................................................................................................................................................................31
2.1.6. Mode 5..................................................................................................................................................................................32
2.1.7. Mode 6..................................................................................................................................................................................33
2.1.8. Mode 7..................................................................................................................................................................................34
2.1.9. Mode 8..................................................................................................................................................................................35
2.1.10. Mode 9 - Bypass ..................................................................................................................................................................36
2.1.11. Mode 10 – Picture in Picture (PiP) (External OSD Less Than 720p) .........................................................................37
2.1.12. Mode 11 – PIP (External OSD Greater Than or Equal To 720p).................................................................................38
2.1.13. Mode 12 – Dual Zone OSD ...............................................................................................................................................39
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2.1.14. Mode 13 – OSD from HDMI RX .....................................................................................................................................40
2.1.15. Mode 14 – Handling Triple Inputs ...................................................................................................................................41
2.2. ADV8005 Top Level Overview.....................................................................................................................................41
2.2.1. Video Muxing......................................................................................................................................................................41
2.2.2. Digital Video Input.............................................................................................................................................................45
2.2.2.1. Video TTL Input ...................................................................................................................................................................................46
2.2.2.2. EXOSD TTL Input................................................................................................................................................................................46
2.2.2.3. TTL Output ...........................................................................................................................................................................................46
2.2.2.4. Treatment o f Unused TTL Inputs .....................................................................................................................................................48
2.2.2.5. Serial Video Rx......................................................................................................................................................................................52
2.2.2.6. Primary Input Channel........................................................................................................................................................................52
2.2.2.7. Secondary Input Channel....................................................................................................................................................................57
2.2.2.8. RX Input Channel.................................................................................................................................................................................61
2.2.3. Updither Configuration .....................................................................................................................................................62
2.2.4. Clock Configuration...........................................................................................................................................................62
2.2.4.1. PVSP Output Timing ...........................................................................................................................................................................66
2.2.4.2. SVSP Output Timing............................................................................................................................................................................67
2.2.4.3. Frame Tracking .....................................................................................................................................................................................67
2.2.5. DDR2 Interface ...................................................................................................................................................................68
2.2.5.1. DDR2 Configuration............................................................................................................................................................................69
2.2.5.2. DDR2 Bandwidth and Memory Selection ........................................................................................................................................70
2.2.5.3. Single DDR2 Memory Configuration................................................................................................................................................72
2.2.5.4. DDR2 Loopback Test ...........................................................................................................................................................................72
2.2.6. I2C Auto Increment.............................................................................................................................................................73
2.2.7. SPI Loop Through ..............................................................................................................................................................74
2.2.8. VBI Data Insertion .............................................................................................................................................................74
2.2.8.1. Extraction Overview ............................................................................................................................................................................74
2.2.8.2. Ancillary Data Extraction....................................................................................................................................................................74
2.2.8.3. SPI Data Extraction ..............................................................................................................................................................................75
2.2.8.4. VBI Data Delay .....................................................................................................................................................................................75
2.2.9. Resets ....................................................................................................................................................................................76
2.2.10. Image Processing Colorimetry Breakdown ....................................................................................................................78
2.2.11. AV-Codes.............................................................................................................................................................................79
2.2.12. Color Space Conversion.....................................................................................................................................................83
2.2.12.1. Primary Input Channel CSC.........................................................................................................................................................83
2.2.12.2. Secondary Input Channel CSC.....................................................................................................................................................86
2.2.12.3. RX Input Channel CSC..................................................................................................................................................................89
2.2.12.4. TTL Output CSC ............................................................................................................................................................................92
2.2.12.5. HDMI Transmitter CSCs...............................................................................................................................................................95
2.2.13. VGA Position and Phase Information .............................................................................................................................98
2.2.14. ADV8005 Silicon Revision ................................................................................................................................................103
2.2.15. System Configuration.........................................................................................................................................................103
3. Video Signal Processing .......................................................................................................................................... 104
3.1. Introduction ....................................................................................................................................................................104
3.2. Primary VSP....................................................................................................................................................................104
3.2.1. Introduction to PVSP.........................................................................................................................................................104
3.2.1.1. Autoconfiguration ................................................................................................................................................................................105
3.2.1.2. Customized Input/Output Video Format Configuration ...............................................................................................................107
3.2.1.3. Field/Frame Buffer Number................................................................................................................................................................108
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3.2.1.4. Field/Frame Buffer Address and Size.................................................................................................................................................108
3.2.1.5. Frame Latency.......................................................................................................................................................................................110
3.2.1.6. Game Mode ...........................................................................................................................................................................................111
3.2.1.7. Low Latency Mode ...............................................................................................................................................................................112
3.2.1.8. Freezing Output Video.........................................................................................................................................................................113
3.2.1.9. Progressive Cadence Detection ..........................................................................................................................................................113
3.2.2. PVSP Video Input Module ................................................................................................................................................114
3.2.2.1. VIM Cropper.........................................................................................................................................................................................114
3.2.2.2. Horizontal Down Scaler ......................................................................................................................................................................116
3.2.2.3. Scaler Interpolation Mode...................................................................................................................................................................116
3.2.2.4. Scaler Controls ......................................................................................................................................................................................117
3.2.2.5. Pixel Packer............................................................................................................................................................................................117
3.2.3. PVSP Video Output Module .............................................................................................................................................118
3.2.3.1. Pixel Unpacker ......................................................................................................................................................................................119
3.2.3.2. VOM Cropper .......................................................................................................................................................................................119
3.2.3.3. Motion Detection..................................................................................................................................................................................120
3.2.3.4. Low Angle De-interlacing ...................................................................................................................................................................121
3.2.3.5. Cadence Detection................................................................................................................................................................................121
3.2.3.6. CUE Correction ....................................................................................................................................................................................122
3.2.3.7. Random Noise Reduction ...................................................................................................................................................................123
3.2.3.8. Mosquito Noise Reduction..................................................................................................................................................................124
3.2.3.9. Block Noise Reduction.........................................................................................................................................................................124
3.2.3.10. Sharpness Enhancement................................................................................................................................................................126
3.2.3.11. Scaler ................................................................................................................................................................................................126
3.2.3.12. Panorama Mode..............................................................................................................................................................................128
3.2.3.13. Output Port......................................................................................................................................................................................128
3.2.3.14. Demo Function...............................................................................................................................................................................131
3.2.3.15. Progressive to Interlaced Converter.............................................................................................................................................133
3.2.3.16. Automatic Contrast Enhancement ..............................................................................................................................................134
3.3. Secondary VSP................................................................................................................................................................134
3.3.1. Introduction to SVSP .........................................................................................................................................................134
3.3.1.1. Autoconfiguration ................................................................................................................................................................................136
3.3.1.2. Customized Input/Output Video Format Configuration ...............................................................................................................138
3.3.1.3. Frame Buffer Number..........................................................................................................................................................................138
3.3.1.4. Frame Buffer Address and Size...........................................................................................................................................................138
3.3.1.5. Frame Latency.......................................................................................................................................................................................140
3.3.1.6. Freezing Output Video.........................................................................................................................................................................141
3.3.2. SVSP Video Input Module (VIM) ....................................................................................................................................141
3.3.2.1. VIM Cropper.........................................................................................................................................................................................142
3.3.2.2. Scaler.......................................................................................................................................................................................................143
3.3.2.3. Scaler Interpolation Mode...................................................................................................................................................................144
3.3.2.4. VIM Miscellaneous Control................................................................................................................................................................144
3.3.2.5. Panorama Mode....................................................................................................................................................................................145
3.3.2.6. Pixel Packer............................................................................................................................................................................................145
3.3.3. SVSP Video Output Module..............................................................................................................................................146
3.3.3.1. Pixel Unpacker ......................................................................................................................................................................................147
3.3.3.2. VOM Cropper .......................................................................................................................................................................................147
3.3.3.3. Output Port............................................................................................................................................................................................148
3.3.3.4. DDR Bypass Mode................................................................................................................................................................................151
3.3.3.5. Progressive to Interlaced Converter in SVSP....................................................................................................................................152
3.4. VSP Register Access Protocols......................................................................................................................................152
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3.4.1. Bootup Protocol ..................................................................................................................................................................153
3.4.2. Reboot Protocol ..................................................................................................................................................................154
3.4.3. Gentle Reboot Protocol......................................................................................................................................................155
3.4.4. VOM Set Protocol...............................................................................................................................................................156
3.4.5. Free Access Protocol...........................................................................................................................................................156
3.5. Horizontal Pre-scaler .....................................................................................................................................................157
3.5.1. HPS Downscaling ...............................................................................................................................................................158
3.5.2. HPS Upscaling.....................................................................................................................................................................159
3.5.3. Using the HPS for converting between 3D to 2D Video formats.................................................................................160
3.5.4. 3D Side by Side Full............................................................................................................................................................161
3.5.5. 3D Side by Side Full............................................................................................................................................................162
3.6. External Sync Mode .......................................................................................................................................................162
3.6.1. Functional Description ......................................................................................................................................................163
3.7. Progressive to Interlaced Conversion ..........................................................................................................................165
4. On Screen Display ................................................................................................................................................... 166
4.1. Introduction ....................................................................................................................................................................166
4.1.1. Features ................................................................................................................................................................................166
4.1.2. OSD System Application Diagram ...................................................................................................................................166
4.1.3. Typical OSD Component Sizes .........................................................................................................................................167
4.2. Architecture Overview...................................................................................................................................................167
4.2.1. Introduction ........................................................................................................................................................................167
4.2.2. Top Level Diagram .............................................................................................................................................................167
4.2.3. OSD Blending......................................................................................................................................................................168
4.2.4. External Alpha Blending....................................................................................................................................................169
4.2.5. OSD Core .............................................................................................................................................................................169
4.2.5.1. OSD Core Region Definition ..............................................................................................................................................................170
4.2.5.2. OSD Color Space ..................................................................................................................................................................................171
4.2.6. OSD Timers .........................................................................................................................................................................171
4.2.7. OSD Scaler ...........................................................................................................................................................................174
4.2.8. OSD Master/Slave SPI Interface .......................................................................................................................................174
4.2.8.1. Overview ................................................................................................................................................................................................174
4.2.8.2. SPI Slave Interface.................................................................................................................................................................................178
4.2.8.3. SPI Master Interface .............................................................................................................................................................................180
4.2.9. OSD Initialization...............................................................................................................................................................181
5. Serial Video Receiver .............................................................................................................................................. 182
5.1. + 5 V Detect ....................................................................................................................................................................182
5.2. TMDS Clock Activity Detection ..................................................................................................................................183
5.3. Clock and Data Termination Control..........................................................................................................................183
5.4. AV Mute Status ...............................................................................................................................................................184
5.5. Deep Color Mode Support ............................................................................................................................................184
5.6. Video FIFO......................................................................................................................................................................185
5.7. Pixel Repetition...............................................................................................................................................................186
5.8. Sync Signal Polarity Readbacks ....................................................................................................................................187
5.9. InfoFrame Registers .......................................................................................................................................................188
5.9.1. InfoFrame Collection Mode..............................................................................................................................................188
5.9.2. InfoFrame Checksum Error Flags ....................................................................................................................................188
5.9.3. AVI InfoFrame Registers ...................................................................................................................................................189
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5.9.4. SPD InfoFrame Registers...................................................................................................................................................190
5.9.5. MPEG Source InfoFrame Registers..................................................................................................................................191
5.9.6. Vendor Specific InfoFrame Registers...............................................................................................................................191
5.10. Packet Registers ..............................................................................................................................................................192
5.10.1. ISRC Packet Registers.........................................................................................................................................................192
5.10.2. Gamut Metadata Packets ...................................................................................................................................................194
5.11. Customizing Packet/InfoFrame Storage Registers .....................................................................................................195
5.12. HDMI Section Reset Strategy .......................................................................................................................................196
6. HDMI Transmitter .................................................................................................................................................. 197
6.1. General Controls ............................................................................................................................................................197
6.2. Reset Strategy ..................................................................................................................................................................199
6.3. HDMI DVI Selection .....................................................................................................................................................199
6.4. AV Mute...........................................................................................................................................................................199
6.5. Source Product Description InfoFrame ......................................................................................................................200
6.6. Spare Packets and VSI Support.....................................................................................................................................201
6.7. System Monitoring .........................................................................................................................................................204
6.7.1. General Status and Interrupts ...........................................................................................................................................204
6.7.2. VSYNC Interrupt ................................................................................................................................................................205
6.8. EDID/HDCP Controller Status....................................................................................................................................205
6.9. EDID/HDCP Controller Error Codes.........................................................................................................................205
6.10. Video Setup .....................................................................................................................................................................206
6.10.1. Input Format........................................................................................................................................................................206
6.10.2. Video Mode Detection.......................................................................................................................................................206
6.10.3. Pixel Repetition ...................................................................................................................................................................207
6.10.4. Video Related Packets and InfoFrames............................................................................................................................208
6.10.5. AVI InfoFrame ....................................................................................................................................................................208
6.10.6. MPEG InfoFrame................................................................................................................................................................209
6.10.7. Gamut Metadata .................................................................................................................................................................210
6.11.Audio Setup.....................................................................................................................................................................212
6.11.1. Audio Architecture .............................................................................................................................................................212
6.11.2. Audio from Serial Video Rx ..............................................................................................................................................212
6.11.3. Audio Configuration ..........................................................................................................................................................213
6.11.3.1. I2S Audio .........................................................................................................................................................................................215
6.11.3.2. SPDIF Audio ...................................................................................................................................................................................221
6.11.3.3. DSD Audio ......................................................................................................................................................................................221
6.11.3.4. HBR Audio ......................................................................................................................................................................................222
6.11.4. N and CTS Parameters.......................................................................................................................................................223
6.11.4.1. N Parameter.....................................................................................................................................................................................223
6.11.4.2. CTS Parameter ................................................................................................................................................................................224
6.11.4.3. Recommended N and Expected CTS Values..............................................................................................................................224
6.11.5. Audio Sample Packets ........................................................................................................................................................225
6.11.6. Audio InfoFrame.................................................................................................................................................................230
6.11.7. ACP Packet ..........................................................................................................................................................................230
6.11.8. ISRC Packet .........................................................................................................................................................................231
6.12. EDID Handling...............................................................................................................................................................233
6.12.1. Reading the EDID...............................................................................................................................................................233
6.12.2. EDID Definitions................................................................................................................................................................233
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6.12.3. Additional Segments ..........................................................................................................................................................233
6.12.4. edid_tries Control...............................................................................................................................................................234
6.12.5. EDID Reread Control.........................................................................................................................................................234
6.13. HDCP Handling .............................................................................................................................................................235
6.13.1. One Sink and No Upstream Devices................................................................................................................................235
6.13.2. Multiple Sinks and No Upstream Devices.......................................................................................................................236
6.13.3. Software Implementation ..................................................................................................................................................238
6.13.4. AV Mute ...............................................................................................................................................................................239
6.14. Audio Return Channel...................................................................................................................................................239
6.15. Charge Injection Settings ..............................................................................................................................................240
6.16. Enabling and Disabling the HDMI TMDS Otuputs..................................................................................................240
6.17. HDMI TX Source Termination ....................................................................................................................................241
6.18. HDMI ACR Packet Transmission ................................................................................................................................242
7. Video Encoder Introduction to the ADV8005....................................................................................................... 243
7.1. Introduction ....................................................................................................................................................................243
7.2. Input Configuration .......................................................................................................................................................243
7.3. Output Configuration....................................................................................................................................................246
7.4. Additional Design Features...........................................................................................................................................247
7.4.1. Output Oversampling ........................................................................................................................................................248
7.4.2. Subcarrier Frequency Lock (SFL) Mode.........................................................................................................................248
7.4.3. SD VCR FF/RW Synchronization.....................................................................................................................................249
7.4.4. Vertical Blanking Interval..................................................................................................................................................249
7.4.5. SD Subcarrier Frequency Control ....................................................................................................................................249
7.4.5.1. Programming the FSC .........................................................................................................................................................................250
7.4.6. SD Non Interlaced Mode (240p/288p) ............................................................................................................................250
7.4.7. Filters ....................................................................................................................................................................................250
7.4.7.1. SD Filters................................................................................................................................................................................................250
7.4.7.2. ED/HD Filters .......................................................................................................................................................................................253
7.4.8. ED/HD Test Pattern Generator.........................................................................................................................................254
7.4.9. Color Space Conversion Matrix........................................................................................................................................255
7.4.10. ED/HD Manual CSC Matrix Adjust Feature ..................................................................................................................255
7.4.10.1. Programming the CSC Matrix......................................................................................................................................................257
7.4.11. SD Luma and Color Scale Control ...................................................................................................................................257
7.4.12. SD Hue Adjust Control ......................................................................................................................................................258
7.4.13. SD Brightness Detect..........................................................................................................................................................259
7.4.14. SD Brightness Control .......................................................................................................................................................259
7.4.15. Double Buffering.................................................................................................................................................................260
7.4.15.1. ED/HD Doubling Buffering..........................................................................................................................................................260
7.4.15.2. SD Doubling Buffering ..................................................................................................................................................................260
7.4.16. Programmable DAC Gain Control...................................................................................................................................261
7.4.17. Gamma Correction.............................................................................................................................................................262
7.4.17.1. ED/HD Gamma Correction .........................................................................................................................................................264
7.4.17.2. SD Gamma Correction..................................................................................................................................................................265
7.4.18. ED/HD Sharpness Filter and Adaptive Filter Controls .................................................................................................266
7.4.18.1. ED/HD Sharpness Filter Mode.....................................................................................................................................................266
7.4.18.2. ED/HD Adaptive Filters ................................................................................................................................................................267
7.4.18.3. ED/HD Adaptive Filter Modes.....................................................................................................................................................268
7.4.18.4. ED/HD Sharpness Filter and Adaptive Filter Application Examples .....................................................................................269
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7.4.19. SD Digital Noise Reduction ..............................................................................................................................................271
7.4.19.1. Coring Gain Border .......................................................................................................................................................................272
7.4.19.2. Coring Gain Data ...........................................................................................................................................................................272
7.4.19.3. DNR Threshold...............................................................................................................................................................................273
7.4.19.4. Border Area .....................................................................................................................................................................................273
7.4.19.5. Block Size Control..........................................................................................................................................................................273
7.4.19.6. DNR Input Select Control.............................................................................................................................................................274
7.4.19.7. DNR Mode Control........................................................................................................................................................................274
7.4.19.8. DNR Block Offset Control ............................................................................................................................................................275
7.4.19.9. SD Active Video Edge Control .....................................................................................................................................................275
7.5. Vertical Blanking Interval..............................................................................................................................................276
7.6. DAC Configurations ......................................................................................................................................................277
7.6.1. Voltage Reference................................................................................................................................................................277
7.6.2. Video Output Buffer and Optional Output Filter ..........................................................................................................277
8. Interrupts................................................................................................................................................................. 280
8.1. Interrupt Pins ..................................................................................................................................................................280
8.1.1. Interrupt Duration..............................................................................................................................................................280
8.1.2. Storing Masked Interrupts.................................................................................................................................................281
8.2. Serial Video Rx Interrupts.............................................................................................................................................281
8.2.1. Introduction ........................................................................................................................................................................281
8.2.2. Interrupt Architecture Overview......................................................................................................................................284
8.2.2.1. Multiple Interrupt Events ....................................................................................................................................................................285
8.2.3. Serial Video Interrupts Validity Checking Process ........................................................................................................285
8.3. VSP and OSD Section ....................................................................................................................................................285
8.3.1. Interrupt Architecture Overview......................................................................................................................................286
8.4. HDMI Tx core.................................................................................................................................................................286
8.4.1. Introduction ........................................................................................................................................................................286
8.4.2. Interrupt Architecture Overview......................................................................................................................................287
8.4.3. HDMI Tx Interrupt Polarity .............................................................................................................................................287
Appendix A ....................................................................................................................................................................... 288
PCB Layout Recommendations....................................................................................................................................................288
Analogue/Digital Video Interface Outputs......................................................................................................................................288
External DDR2 Memory Requirements...........................................................................................................................................288
Power Supply Bypassing .....................................................................................................................................................................289
General Digital Inputs and Outputs .................................................................................................................................................289
XTAL and Load Cap Value Selection................................................................................................................................................289
Encoder Component Placement .......................................................................................................................................................290
HDMI Transmitter Component Placement.....................................................................................................................................290
Power Supply Design and Sequencing..............................................................................................................................................290
Appendix B........................................................................................................................................................................ 292
Unused Pin List ..............................................................................................................................................................................292
Appendix C ....................................................................................................................................................................... 304
Pixel Input and Output Formats...................................................................................................................................................304
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REVISION HISTORY
1/15—Rev. 0 to Rev. A
Changes to Spare Packets and VSI Support Section ................ 201
Added VSYNC Interrupt Section and Table 53; Renumbered
Sequentially ................................................................................... 205
6/14—Revision 0: Initial Version
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UG-707 ADV8005 Hardware Reference Manual
UNDERSTANDING THE ADV8005 HARDWARE MANUAL
DESCRIPTION OF THE HARDWARE MANUAL
This manual provides a detailed description of the functionality and features supported by the ADV8005.
DISCLAIMER
The information contained in this document is proprietary of Analog Devices Inc. (ADI). This document must not be made available to anybody
other than the intended recipient without the written permission of ADI.
The content of this document is believed to be correct. If any errors are found within this document or, if clarification is needed, contact Analog
Devices.
TRADEMARK AND SERVICE MARK NOTICE
The Analog Devices logo is a registered trademark of Analog Devices, Inc. All other brand and product names are trademarks or service marks
of their respective owners.
NUMBER NOTATIONS
Notation Description
bit N Bits are numbered in little endian format, that is, the least
significant bit of a number is referred to as Bit 0
V[X:Y] Bit field representation covering bit X to Y of a value or a field V
0xNN Hexadecimal (base-16) numbers are preceded by the prefix‘0x’
0bNN Binary (base-2) numbers are preceded by the prefix ‘0b’
NN Decimal (base-10) are represented using no additional prefixes
or suffixes
REGISTER ACCESS CONVENTIONS
Mode Description
R/W Memory location has read and write access.
R Memory location has read access only. A read always returns 0
unless specified otherwise.
W Memory location has write access only.
ACRONYMS AND ABBREVIATIONS
This is a list of common acronyms and abbreviations found in Analog Devices Hardware Manuals.
Acronym/Abbreviation Description
ACP Audio Content Protection
ACR Audio Clock Regeneration
ADC Analog to Digital Converter
AFE Analog Front End
AGC
Automatic Gain Control
Ainfo HDCP register. Refer to HDCP documentation.
AKSV HDCP Transmitter Key Selection Vector. Refer to HDCP documentation.
An 64-bit pseudo-random value generated by HDCP cipher function of device A
ARC Audio Return Channel
AUD_IN Audio Input Pin
AVI Auxiliary Video Information
Aux Auxiliary
Bcaps HDCP register. Refer to HDCP documentation.
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Acronym/Abbreviation Description
BGA Ball Grid Array
BKSV HDCP Receiver Key Selection Vector. Refer to HDCP documentation.
BNR Block Noise Reduction
CEC Consumer Electronics Control
CP
Component Processor
CSC Color Space Converter/Conversion
CSync Composite Synchronization
CTS Cycle Time Stamp
CUE Color Upsampling Error
CVBS Composite Video
DCM Decimation
DDR Double Data Rate
DDFS Direct Digital Frequency Synthesizer
DE Data Enable
DID Data Identification Word
DLL Delay Locked Loop
DMA
Direct Memory Access
DNR Digital Noise Reduction
DPP Data Preprocessor
DSD Direct Stream Digital
DST Direct Stream Transfer
DUT Device Under Test (designate the ADV8005 unless stated otherwise)
DVD
Digital Video Disc
DVI Digital Visual Interface
EAV End of Active Video
ED
Enhanced Definition
ENC Encoder
EQ Equalizer
FFS Field Frame Scheduler
FRC Frame Rate Conversion/Converter
HBR High Bit Rate
HD High Definition
HDCP High Bandwidth Digital Content Protection
HDMI High Definition Multimedia Interface
HDTV High Definition Television
HEAC HDMI Ethernet and Audio Channels
HEC HDMI Ethernet Channel
HPA Hot Plug Assert
HPD Hot Plug Detect
HSync/HS Horizontal Synchronization
IC Integrated Circuit
ISRC International Standard Recording Code
I2S Inter IC Sound
I2C Inter Integrated Circuit
KSV
Key Selection Vector
LLC Line Locked Clock
LQFP Low-profile Quad Flat Package
LSB
Least Significant Bit
L-PCM Linear Pulse Code Modulation
Mbps Megabit per Second
MNR Mosquito Noise Reduction
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Acronym/Abbreviation Description
MPEG Moving Picture Expert Group
ms Millisecond
MSB Most Significant Bit
NC No Connect
NSV
Noise Shaped Video
OSD On Screen Display
OTP One Time Programmable
PtoI Progressive to Interlaced
Pj’ HDCP Enhanced Link Verification Response. Refer to HDCP documentation.
PVSP Primary VSP
Ri’ HDCP Link verification response. Refer to HDCP documentation.
RNR Random Noise Reduction
Rx Receiver
SA Slave Address
SAV Start of Active Video
SD Standard Definition
SDP
Standard Definition Processor
SDR Single Data Rate
SMPTE Society of Motion Picture and Television Engineers
SNR Signal to Noise Ratio
SOG Sync on Green
SOY Sync on Y
SPA
Source Physical Address
SPD Source Production/Product Descriptor
SPDIF Sony/Philips Digital Interface
SPI
Serial Peripheral Interface
SRM System Renewability Message
SSPD Synchronization Source Polarity Detector
STDI Standard Identification
SVSP Secondary VSP
TBC Timebase Correction
TMDS Transition Minimized Differential Signaling
Tx Transmitter
ULAI Ultra Low Angle Interpolation
US Up Sampling
VBI Video Blanking Interval
VDP VBI Data Processor
VIC Video Identification Code
VIM Video Input Module
VOM Video Output Module
VSDP Vendor Specific Data Block
VSP Video Signal Processor/Processing
VSync/VS Vertical Synchronization
XTAL Crystal Oscillator
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ADV8005 Hardware Reference Manual UG-707
FIELD FUNCTION DESCRIPTION
The function of a field is described in a table preceded by the bit name, a short function description, the I2C map, the register location within
the I2C map, and a detailed description of the field. Refer to Figure 1 for more details.
The detailed description consists of:
•For a readable field, the values the field can take
•For a writable field, the values the field can be set to
deep_color_mode[1:0], HDMI RX Map, Address 0xE20B[7:6] (Read Only)
A readback of the deep color mode information extracted from the general control packet.
Function
deep_color_mode[1:0]
Description
00 
8-bits per channel
01
10-bits per channel
10
12-bits per channel
11
16-bits per channel (not supported)
Figure 1. Field Description Format
Default value
indicated by

The name of the field. In this example the field is called
deep_color_mode and is 2 bits long.
I2C location of the field
in big endian format
(MSB first, LSB last)
Detailed
description
of the field
Values the field can be set to or
take. These values are in binary
format if not preceded by ‘0x’ and in
hexadecimal format if preceded by
‘ 0 x ’.
Read/Write
Access for field
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UG-707 ADV8005 Hardware Reference Manual
REFERENCES
HDMI Licensing and LLC, High-Definition Multimedia Interface, Revision 1.4a, March 4, 2010
Digital Content Protection (DCP) LLC, High-bandwidth Digital Content Protection System, Revision 1.3, December 21, 2006
CEA, CEA-861-E, A DTV Profile for Uncompressed High Speed Digital Interfaces, Revision E, September 11, 2007
ITU, ITU-R BT.656-4, Interface for Digital Component Video Signals in 525-Line and 625-Line Television Systems Operating at the 4:2:2 Level
of Recommendation ITU-R BT.601, February 1998
ITU, ITU-R BT.601-5 Studio encoding parameters of digital television for standard 4:3 and widescreen 16:9 aspect ratios, December 1995
ITU, ITU-R BT.709-5 Parameter values for the HDTV standards for production and international programme exchange, April 2002
CENELEC, EN 50157, Part 1, Domestic and similar electronic equipment interconnection requirements: AV.link
CENELEC, EN 50157, Part 2-1, Domestic and similar electronic equipment interconnection requirements: AV.link
CENELEC, EN 50157, Part 2-2, Domestic and similar electronic equipment interconnection requirements: AV.link
CENELEC, EN 50157, Part 2-3, Domestic and similar electronic equipment interconnection requirements: AV.link
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ADV8005 Hardware Reference Manual UG-707
1. INTRODUCTION TO THE ADV8005
1.1. OVERVIEW
The ADV8005 is a video signal processor (VSP) with TTL and Serial Video inputs that can de-interlace and scale input video, generate and blend
a bitmap based on-screen display (OSD) and output the blended video using one or more of the part’s outputs; dual HDMI transmitters and a
6-DAC encoder with SD and HD support.
The ADV8005 has three video inputs – the video TTL input, the EXOSD TTL input and the Serial Video receiver (Rx). The combined video
TTL input and EXOSD TTL input constitute the flexible 60-bit TTL input port. The 60-bit TTL input port can be arranged in a variety of
fashions to accept one input video stream (for example, a 48-bit 3 GHz input video stream from ADV7619) or two input video streams (for
example, a 36-bit input video stream from ADV7844 and a 24-bit input video stream from an external OSD generator). Once the data is received,
the video TTL and EXOSD TTL inputs can be connected to either the primary input channel or the secondary input channel. From these input
channels, the video data can be sent to the internal video processing blocks (for example, primary VSP or secondary VSP).
The Serial Video Rx is connected to the RX input channel. The Serial Video Rx accommodates inter-chip transfer of data over an HDMI
compatible interface (for example, from an HDMI (Rx) such as ADV7850 or transceiver such as ADV7623). The ADV8005 does not support
EDID or DDC activity on this port.
The motion adaptive de-interlacer in the ADV8005 provides excellent edge detection and excellent ultra-low angle performance. Per-pixel
motion-adaptive de-interlacing is used for natively interlaced input video (for example, a live sport broadcast) where still parts of the image are
reconstructed from information on both the odd and even fields, and moving parts of the image are interpolated by an advanced interpolation
algorithm. The de-interlacer can also recognize when interlaced input video originally came from progressive content (for example, 24 Hz movie
content or 30 Hz documentary content) and reconstructs the original frames.
Dual video scalers allow the ADV8005 to support two different output resolutions on its outputs, for example, 1080p60 on HDMI Tx1 and 720p
on HDMI Tx2 and the HD encoder. The primary VSP (PVSP) in the ADV8005 is capable of upscaling from 480i to 4k x 2k formats. The
secondary VSP (SVSP) in the ADV8005 is used to provide a second output resolution to accommodate dual zone systems. The ADV8005 is also
capable of downscaling a single 4Kx2K input to 1080p or lower using a combination of a Horizontal Pre-Scaler (HPS) and the SVSP. Also
available in the ADV8005 are image enhancing features such as random noise reduction (RNR), mosquito noise reduction (MNR) and block
noise reduction (BNR), detail enhancement and automatic contrast enhancement (ACE).
The ADV8005 features an internal bitmap based OSD generator capable of generating OSDs of up to 4k x 2k. External solutions can also be
implemented and fed into the ADV8005 for blending with the main video. A bitmap based OSD is an advanced form of OSD display, which can
add effects such as scrolling, animation and 3D depth to OSD displays. This allows customers to create advanced OSD designs to differentiate
their products. Once created, OSD designs are stored in an external SPI flash memory connected to the ADV8005. The control of the OSD must
be performed from the system microcontroller via SPI. OSD designs can be created using ADI’s software development tool, Blimp OSD.
The ADV8005 offers flexible configuration of its internal circuitry allowing the output of one, two or three input channels simultaneously. The
output of multiple ADV8005s can be synchronized using the master clock, horizontal sync and vertical sync inputs. This facilitates, with the
incorporation of a simple FPGA, seamless per pixel switching of multiple synchronized ADV8005 inputs. The ADV8005 can also measure the
picture position and sample quality of the video being processed; this assists in identifying the exact video format and the optimum sampling
phase of the video front end’s ADC.
Video can be output from the ADV8005 via one or both of the HDMI transmitters, the 6-DAC SD/HD video encoder or using the TTL interface.
Both HDMI transmitters support the HDMI v1.4b specifications of increased resolutions, 3D video and audio return channel (ARC). The
ADV8005 supports both S/PDIF and 8-channel I2S audio. . The audio can be sourced from either the external audio interface or using the audio
pass through feature of the Serial Video Rx.
The ADV8005 includes a high-speed digital-to-analog video encoder available with and without Rovi content protection. Six high speed, Noise
Shaped Video (NSV), 12-bit video DACs provide support for composite (CVBS), S-video (Y/C), and component (YPrPb/RGB) analog outputs
in either SD, ED, or HD video formats up to 1080p. In addition, simultaneous SD and ED/HD formats are supported. 216 MHz (SD and ED)
and 297 MHz (HD) oversampling ensures that external output filtering is not required. The final option to output video from the ADV8005 is
the TTL interface which allows up to 36 of the pins to be reconfigured as outputs. This facilitates the output of up to 1080p 12-bit deep color
from the ADV8005 to an FPGA without the requirement of an expensive FPGA-based HDMI phy.
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UG-707 ADV8005 Hardware Reference Manual
The ADV8005 supports all common consumer formats as outlined in the EIA-861 specification and many common professional output formats
as outlined in the VESA specification.
The part supports the I2C® and SPI protocols for communication with the system microcontroller.
Note: There are four options within the ADV8005 family of parts, each with different capabilities but all in the same CSPBGA-425 package.
These are described in Table 1.
Tab le 1: Available Features Within ADV8005 Family of ICs
Part Number Max Speed
Maximum
Resolution
HDMI Tx
Outputs
Analog
Outputs Rovi VSP OSD
TTL
Out
ADV8005KBCZ-
8A
3 Gbps 4k × 2k at 30 Hz (8-
bit)
2 Six 12-bit DACs Yes 2 Yes Yes
ADV8005KBCZ-
8N
3 Gbps 4k × 2k at 30 Hz (8-
bit)
2 Six 12-bit DACs No 2 Yes Yes
ADV8005KBCZ-
8B
3 Gbps 4k × 2k at 30 Hz (8-
bit)
1 No N/A 1 Yes No
ADV8005KBCZ-
8C
3 Gbps 4k × 2k at 30 Hz (8-
bit)
2 No N/A 2 Yes No
Note that ADV8005KBCZ-8A and ADV8005KBCZ-8N functionality is described throughout this manual (figures, functional blocks, and so
on). Some sections of this manual are not relevant to the ADV8005KBCZ-8B and ADV8005KBCZ-8C as they do not include those blocks. If a
section is not relevant to a particular generic, this is indicated in the introduction to that section.
1.1.1. Digital Video Input
Video data can be input into the ADV8005 in a number of ways. The flexible 60-bit TTL input port can be configured for dual video inputs
(video TTL input and EXOSD TTL input), for a single video input (interleaved TTL data from an ADV7619) or for a single video input and an
external alpha channel. The 60-bit TTL input port is extremely flexible and can be configured into a number of different arrangements; for more
information, refer to Table 88 and Table 89. Video can also be input into the ADV8005 via the Serial Video Rx which can be used for device to
device interconnect, for example, a serial video link between the ADV7850 and the ADV8005 or a serial video link between the ADV7623 and
the ADV8005. Using such front end devices located before the ADV8005 allows the audio to be extracted and processed in a DSP before being
reinserted into the ADV8005.
A mux after the TTL inputs allows the video TTL input pins and the EXOSD TTL input pins to be connected to either the primary or the
secondary input channel. The primary input channel features an input formatter, manually programmable CSC, updither function, ACE,
contrast, brightness and saturation controls. The secondary input channel features an input formatter, manually programmable CSC and
updither function. The Serial Video Rx is connected directly to the Rx input channel and features an input formatter, manually programmable
CSC and updither function.
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ADV8005 Hardware Reference Manual UG-707
Figure 2: ADV8005 Digital Video Interface
1.1.2. Flexible Digital Core
The ADV8005 has a flexible digital core, allowing multiple options for the routing of video data. This allows the user to place the OSD in front
of the video processing so the OSD will be overlaid on one or more outputs. Alternatively, video processing can be placed before the OSD
ensuring all outputs are processed to the highest quality. The digital core can also be configured so that the ADV8005 can output one or all of
the inputs in various arrangements, for example, picture in picture with one input appearing as a window within another or two inputs routed
to two outputs.
Several common modes of operation are defined to assist the user to quickly integrate the ADV8005 into a system. Refer to Section 2 for more
details.
1.1.3. Video Signal Processor
The motion adaptive de-interlacer in the ADV8005 offers excellent edge detection and ultra low angle performance. The per-pixel de-interlacing
algorithm used delivers excellent performance which can be seen with specialist test patterns, on facial features like eyebrows or on shirt collars.
This algorithm decides on whether an area of an image is moving or not and then applies the appropriate de-interlacing approach accordingly.
The de-interlacer can also determine when interlaced video originated as progressive and can reconstruct the original frames.
Figure 3: ADV8005 Video Processing
The ADV80038005 features dual scalers referred to as Primary Video Signal Processor (PVSP) and the Secondary Video Signal Processor (SVSP).
The PVSP uses a contour-based interpolation scaler which can upscale from 480i to 4k x 2k. The PVSP can arbitrarily upscale between 480p
and 4k x 2k and down scale between 1080p and 480p. The advanced scaling algorithm used in the ADV8005 eradicates many common problems
associated with scaling video such as ringing and jagged or blurred edges. Using a combination of the Horizontal Pre Scaler (HPS) and the SVSP,
Low Angle
Processing
Cadence
Detection Dual Scaler and
OSD Blend
De-interlacer Enhance
Detail
Enhance
Motion
Detection
CUE
Correction
Colour
Enhance
Noise
Reduction
Low Angle
Processing
Cadence
Detection
Dual Scaler
and FRC
De-interlacer Enhance
Detail
Enhance
Motion
Detection
CUE
Correction
Colour
Enhance
Noise
Reduction
I
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148.5MHz to
300MHz
Conversion
Secondary
Input
Channel
Primary
Input
Channel
RX
Input
Channel
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UG-707 ADV8005 Hardware Reference Manual
the ADV8005 can downscale from 4k x 2k to 1080p. The PVSP can be employed to further scale the downscaled 4k x 2k content. When using
the PVSP as the primary scaler, the SVSP can also be used to provide a second lower resolution output format. The PVSP and SVSP can be
connected in parallel or in series.
The ADV8005 features a number of video enhancement controls such as detail enhancement, block noise reduction, mosquito noise reduction
and random noise reduction. Block and mosquito noise are related to the compression of video for transmission or encoding onto a DVD or BD
disc. Random noise is related to noise picked up during the transmission of video. The automatic contrast enhancement feature offered by the
ADV8005 intelligently stretches the brightness of an image to enhance the dark areas without saturating the dark areas.
Note that the dual scaler variants of the ADV8005 are the following:
•ADV8005KBCZ-8A/8N
•ADV8005KBCZ-8C
The single scaler variants of the ADV8005 are the following:
•ADV8005KBCZ-8B
1.1.4. Bitmap On Screen Display
The ADV8005 incorporates an OSD core capable of generating an internal bitmap based OSD. Customers can generate elaborate OSD designs
that can include bitmap images, 3D overlay and animation. Up to 256 regions in total can be created and displayed. These 256 regions are bitmap
images defined during the design stage and can be characters, pictures, buttons, and so on. Individual regions can be alpha blended and
prioritized versus other regions.
Figure 4: ADV8005 Bitmap OSD
The OSD is controlled by the host microcontroller via the ADV8005 SPI slave (serial port 1). In response to commands, the ADV8005 loads the
data from the external SPI flash memory via the SPI master (serial port 2). The ADV8005 uses DDR2 memory when rendering and blending
the OSD. In order to lower the load of the DDR2 memory, there is a block in the ADV8005 OSD hardware called the OSD co-processor. The
OSD co-processor is responsible for handling upper level commands from the microcontroller and translating them into lower level operations
for the OSD and DMA which retrieves data from the external DDR2 memories.
The OSD blend can be switched between either of the two video streams routed through the OSD blend block without disturbing the output
video. This enables seamless OSD blending in dual zone systems.
Bitmap OSDs can be created and compiled using ADI’s software development tool, Blimp OSD. This allows users to create their custom OSDs
and emulate them before integrating them into their system, abstracting the design task from the underlying OSD hardware. For more details
on the operation of the external OSD, design and system techniques, refer to the Blimp OSD documentation.
OSD Build OSD Scaler
OSD Blend
Video
External OSD
DDR2
OSD Build OSD Scaler
OSD Blend
Video 1
External OSD
DDR2
VideoVideo 2
Internal
OSD Generator
SPI
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ADV8005 Hardware Reference Manual UG-707
1.1.5. External DDR2 Memory
Figure 5: External DDR2 Memory Interface
External DDR2 memory is required for motion adaptive de-interlacing, Frame Rate Conversion (FRC), and OSD bitmap overlay. ADV8005
supports various memory options using one or two DDR2 memories of various sizes (1 Gb maximum). For full processing capabilities, two
DDR2 memories are required which use data transfers up to 250 MHz. Refer to Section 3 for more details on the operations using the external
DDR2 memory.
1.1.6. HDMI Transmitter
The ADV8005 features two HDMI v1.4b transmitters. The transmitters feature an audio return channel (ARC), which allows a Sony/Philips
Digital Interface (SPDIF) audio connection between the source and sink. Each transmitter features an on-chip MPU with an I2C master to
perform HDCP operations and EDID operations.
Note: The dual transmitter variants of the ADV8005 are ADV8005KBCZ-8A, ADV8005KBCZ-8N and ADV8005KBCZ-8C. The single
transmitter variant of the ADV8005 is the ADV8005KBCZ-8B.
1.1.7. Video Encoder
The ADV8005 features a high speed digital to analog video encoder. Six high speed, NSV, 3.3 V, 1 2-bit video DACs provide support for worldwide
composite (CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog outputs in standard definition (SD), enhanced definition (ED), or high
definition (HD) video formats. It is also possible to enable the ADV8005 video encoder to work in simultaneous mode where both an SD and
ED/HD format are being output.
Note: The video encoder variants of the ADV8005 are the ADV8005KBCZ-8A and the ADV8005KBCZ-8N. The variants of ADV8005 with no
encoder are the ADV8005KBCZ-8B and the ADV8005KBCZ-8B.
1.1.8. Digital Video Output
Video can be output from the ADV8005 via the flexible TTL port. Reusing up to 36 of the flexible TTL port pins means that video can be routed
in and out of the ADV8005 without using HDMI, a useful cost reduction in systems which utilize FPGA interconnects (e.g. 30-bit TTL input
and 30-bit TTL output allowing 1080p 10-bit input and output). The possible configurations of the TTL output port are captured in Table 91
and Table 92. The video TTL output port has a manually programmable CSC.
DDR2Interface
Motion
Adaptive
De-interlacer
FrameRate
Conversion Bitmap OSD
Data
DDR2Interface
Motion
Adaptive
De-interlacer
FrameRate
Conversion Bitmap OSD
Data
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UG-707 ADV8005 Hardware Reference Manual
1.2. MAIN FEATURES OF THE ADV8005
1.2.1. Video Signal Processor
1.2.1.1. Primary VSP
•12-bit internal processing
•Fixed frame latency capability
•Input timing up to 1080p
•Output timing up to 4k x 2k
•Input/output format YCbCr at 4:4:4
•Motion adaptive de-interlacing with motion detection
•Ultra low angle interpolation on edge regions of interlaced video
•Cadence detection (any cadence detection possible)
•Progressive cadence supported
•Super resolution video scaler
•Aspect ratio conversion/panorama scaling
•Arbitrary upscaling and downscaling for both horizontal and vertical direction
•Sharpness detail and edge enhancement
•Noise reduction for random, mosquito, and block noise
•Frame Rate Conversion
•Color Upsampling Error (CUE) correction
•Progressive to interlaced (PtoI) converter
•Game mode supported
•Album mode supported
•Demo window
1.2.1.2. Horizontal Pre-Scaler
•8-bit internal processing
•Downscales video standards of greater than 162MHz and/or more than 2048 pixels/line
1.2.1.3. Secondary VSP
•8-bit internal processing
•Input and output timing up to 1080p
•Input and output format YCbCr at 4:4:4
•Up-scaling and down-scaling for both horizontal and vertical direction
•Aspect ratio conversion and panorama scaling
•Frame Rate Conversion
•Progressive to interlaced (PtoI) converter
1.2.2. OSD
•Internally generated bitmap based OSD allowing overlay of bitmap images on one or more video outputs
•Dual video paths through the OSD blend block to support dual zone OSD
•Dedicated OSD scaler – allows OSDs to be rendered at a single resolution reducing external memory bandwidth
•Blending onto 3 GHz video formats
•Pixel-by-pixel alpha blending of OSD data on video data
•Option of externally generated OSD
•OSD can be overlaid in the main 3D video format timings
•Blimp OSD software tool and provided ANSI-C libraries cover the full design flow of any OSD
Rev. A | Page 20 of 317