Annapolis Micro Systems WILDSTAR A5/PCIe Quick user guide

WILDSTAR A5 /PCIe
Hardware Reference
Manual
Document No:15199-0000, Revision 1.2

© Copyright 2014 by Annapolis Micro Systems, Inc. All rights reserved. Printed and published in the United States of America. WILDFIRE,
WILDFIRE-XL, WILDCHILD, WILDFORCE, WILDFORCE-XL, WILD-ONE, WILD-ONE-XL, WILDTIME, WILDCARD,
STARFIRE, WILDSTAR, WILDSTAR-II, WILDSTAR-II PRO, WILDSTAR 4/5/6/7, WILDSTAR A, WILDSTAR-E, WSDP,
WILDWARE, WILD, C2WILD, CoreFire, CoreFire Next and FIREBIRD are trademarks of Annapolis Micro Systems, Inc. All other
trademarks and registered trademarks are owned by their respective owners. Patents Pending.

This is the standard Annapolis Micro Systems, Inc. Shrink Wrap license which covers all Annapolis Hardware, VHDL
Drivers, APIs, Examples, and Reference Designs. CoreFire Next is covered by a different shrinkwrap license.
If this license is included in a purchase order, it supersedes any and all other Terms and Conditions regarding licensing
and technical rights that are found in the Purchase Order.
ANNAPOLIS MICRO SYSTEMS, INC. - LICENSE AGREEMENT
WILDSTAR, WILDSTAR-II, WILDSTAR-II PRO, WILDSTAR 4, WILDSTAR 5, WILDSTAR 6, WILDSTAR 7, WILDSTAR 5B, and
WILDSTAR A5 Host Software, Device Drivers, Models, VHDL, Examples, Tools and PCI and FPGA-based Ethernet Controllers
are supplied with a License Agreement. This License Agreement also covers the PLD designs, Reference designs, and Flash
contents supplied with the board. Do not install or use this product and/or break the seal on the CD-ROM until you have read and
agreed to the following terms and conditions. Should you choose not to be bound by the terms and conditions of this agreement,
you should promptly return this product.
YOU ARE BOUND TO THE TERMS OF THIS AGREEMENT BY BREAKING THE SEAL ON THE CD-ROM
Under the terms of this License, you:
• may make copies of the Licensed Product
• may not transfer the Licensed Product to an unlicensed party
• may modify the VHDL and the Examples
• may not modify any other parts of the Licensed Product
• may not decompile, reverse assemble or otherwise reverse engineer the Licensed Product
• may run this product ONLY on an Annapolis Micro Systems, Inc. board
• may run the FPGA vendor specific parts of this product ONLY on an Annapolis Micro Systems, Inc. board with FPGAs from that
vendor
The Licensed Product is owned and copyrighted by Annapolis Micro Systems, Inc. You may not remove the copyright notice from
the Licensed Product. You must use your best efforts to prevent any unauthorized copying of the Licensed Product.
The Licensed Product is provided “as is” without warranty of any kind including warranties for merchantability or fitness for a
particular purpose. Annapolis Micro Systems, Inc. shall not be liable for any loss of profits, loss of use, interruption of business,
nor for indirect, special, incidental or consequential damages of any kind whether under this agreement or otherwise.
Although Annapolis Micro Systems, Inc. does not warrant the functions contained in the Licensed Product, the medium on which
the Licensed Product is furnished is warranted to be free from defects in materials and workmanship under normal use for a
period of 90 days from date of delivery to you as evidenced by a copy of your receipt. Annapolis Micro Systems’ entire liability to
you and your exclusive remedy shall be replacement of the Licensed Product if the medium on which the Licensed Product is
furnished proves to be defective.
You understand that the Licensed Product may require a license from the US Department of Commerce or other government
agency before it may be taken or sent outside of the United States. You agree to obtain any required licenses before taking or
sending the Licensed Product out of the United States. You will not permit the re-export of the Licensed Product without obtaining
required licenses or letter of further assurance.

Contents
Chapter 1: About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Key Words and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chapter 2: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 WILDSTAR A5 /PCIe Board Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 About the WILDSTAR A5 /PCIe Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.1 WILDSTAR A5 /PCIe Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 WILDSTAR Mezzanine I/O Daughter Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Chapter 3: Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Unpacking and Inspecting the WILDSTAR Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Board Illustrations and LED Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 4: Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1 WILDSTAR A5 /PCIe Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1.1 Power Up System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1.2 WILDSTAR A5 /PCIe DIP Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2 WILDSTAR A5 /PCIe Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2.1 WILDSTAR A5 /PCIe Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Chapter 5: Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1 Board Identification Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Chapter 6: Hardware Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1 WILDSTAR A5 /PCIe Board Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2 Thermal and Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2.1 WILDSTAR A5 /PCIe Heatsinks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2.2 Temperature Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.2.3 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.3 Power Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.4 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Appendix A: CoreFire Next Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Appendix B: WILDSTAR Mezzanine Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Appendix C: WILDSTAR A5 /PCIe Statement of Volatility . . . . . . . . . . . . . . . . . . . 59
Appendix D: WILDSTAR A5 /PCIe Generic I/O Connector Specification . . . . . . . 63

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WILDSTAR A5 /PCIe Hardware Reference Manual
Chapter 1: About This Manual
Chapter 1: About This Manual

2 WILDSTAR A5 /PCIe Hardware Reference Manual
Chapter 1: About This Manual
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Chapter 1: About This Manual
All WILDSTAR A5 /PCIe boards operate with WD Host Software. Detailed software information can be found in the
WD Software Reference Manual, included in hardcopy and as a PDF file on the WD Host Software CD-ROM.
Installation instructions for VHDL and host software are located in the accompanying release notes.
This WILDSTAR A5 /PCIe Hardware Reference Manual is intended to help the user install, program, and maintain
a high performance WILDSTAR A5 /PCIe motherboard from Annapolis Micro Systems, Inc.
Note: References throughout this manual to “WILDSTAR A5 /PCIe” typically pertain to all memories types,
unless specifically indicated otherwise.
1.1 Overview
A brief description of each chapter appears below.
• Chapter 2: Introduction, discusses board architecture and performance features of WILDSTAR A5 /PCIe
boards.
• Chapter 3: Getting Started, describes unpacking and inspection procedures for your WILDSTAR A5 /
PCIe, as well as board LED definitions and locations.
• Chapter 4: Installation describes host system requirements, installation instructions, reset options, and
switch descriptions.
• Chapter 5: Technical Support provides information for contacting Annapolis Micro Systems, Inc.
Technical Support.
• Chapter 6: Hardware Reference describes hardware specifications, along with voltage and clocking.
• Appendix A: CoreFire Next Support contains information regarding CoreFire Next.
• Appendix B: WILDSTAR Mezzanine Cards contains WILDSTAR Mezzanine Card information.
• Appendix C: WILDSTAR A5 /PCIe Statement of Volatility contains the WILDSTAR A5 /PCIe Statement of
Volatility.
• Appendix D: WILDSTAR A5 /PCIe Generic I/O Connector Specification contains the I/O connector
specification for WILDSTAR A5 /PCIe boards.

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Chapter 1: About This Manual
1.2 Conventions
Different text styles are used throughout the manual to call attention to specific items:
Convention Description
Text represented as
screen display This typeface is used to represent displays appearing
on the screen, such as at the “A:\” prompt.
Keys When specific keys are referenced, they are
designated by their labels, such as “the Enter key” or
“the Escape key,” or they may be shown as [Enter] or
[Esc].
When two or more keys are to be pressed
simultaneously, the keys are linked with a plus sign
(+). For example: [Ctrl] + [Alt] + [Del].
Clickable Links Text that references another area in the document.
The user can click on the blue text and the document
will jump directly to the section referenced.

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Chapter 1: About This Manual
1.3 Key Words and Definitions
Terms used throughout the manual are defined below.
API Application Programming Interface
Application Programming Interface
A set of functions coded in the C language allowing communication between an application and the board.
Block RAM
An architectural feature of the Stratix V FPGA in which blocks are reserved specifically for Random Access
Memory.
CLB Configurable Logic Block (CLB). CLBs provide the functional elements for constructing logic within the PE.
CoreFire Next Design Suite
An FPGA design and debug application tool developed by Annapolis Micro Systems, Inc.
CPE Computational Processing Element. A Stratix V Field Programmable Gate Array (FPGA) comprises the
basic processing unit on the WILDSTAR A5 /PCIe board. The Stratix V FPGA is used on WILDSTAR A5 /
PCIe boards. CPEs are contained within Processing Modules (see definition below).
CPE0 Computational Processing Element 0
CPE1 Computational Processing Element 1
DDR3 DRAM
Double Data Rate DRAM. A high-performance, synchronous burst DRAM capable of single- and double-
data operational modes.
Deprogram
To pulse the PROGRAM input to an FPGA causing its configuration to be cleared and placing it in a pre-
configuration state.
Differential Signal Pair
Two lines, one negative and one positive.
Differential Signaling
Two-wire signaling, in which the difference in voltage between two wires is used to signal data.
DLL Dynamic Linkage Library
DMA Direct Memory Access. In this document, DMA refers to data transfers initiated in the PEs which target
host memory or other devices on the system bus.

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DMA Bus
Direct Memory Access Bus. A high-bandwidth point-to-point bus between a PE and the PCI Controller
which is dedicated to DMA transfers initiated by the PE.
DRAM Dynamic Random Access Memory
Driver Software used to handle communication with one to four WILDSTAR A5 /PCIe boards.
External I/O
External Input/Output
FPGA Field Programmable Gate Array
HHS High Speed Serial
ICLK Fixed, single-ended bus clock used for Local Address Data Bus transactions.
IOPE Input/Output Processing Element. A Stratix V Field Programmable Gate Array (FPGA) located on the
WILDSTAR motherboard, responsible for the interface to mezzanine cards.
IRIG-B The IRIG-B Adapter Card allows the sampling of IRIG-B Serial Time Code Data
LAD Bus
Local Address Data Bus. Point-to-point bus from the PCI Controller to each PE. This bus is dedicated to
Programmed Input/Output accesses from the host CPU to the PE.
Lane A set of differential signal pairs, one pair for transmission and one pair for reception. A PCI Express by-N
Link is composed of N Lanes.
MCLK Reprogrammable differential memory clock, synchronous to PCLK.
Mezzanine I/O Card
I/O daughter card designed for compatibility with WILDSTAR 4/5/6/7 families. Mezzanine
I/O cards are classified using Class A and Class B.
ModelTech®
An application used to simulate VHDL.
N/C No Connection
PAR Place and Route

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PCI Peripheral Component Interconnect
PCI Controller
Device on the WILDSTAR A5 board which acts as a bridge between the PEs and the system bus. This
device also provides a variety of board management functions.
PCI Express (PCIe)
General performance I/O interconnect which maintains the fundamental attributes of PCI, but replaces the
parallel bus implementation with a serial interface that offers new features and new levels of performance.
PCLK Reprogrammable Differential Processing Element Clock asynchronous to MCLK.
PE Processing Element. A Field Programmable Gate Array (FPGA) which comprises the basic processing unit
on the WILDSTAR A5 /PCIe board. The Stratix V FPGA is used on WILDSTAR A5 /PCIe boards.
Processing Elements can be subdivided into two categories; Computational Processing Elements (CPEs)
and I/O Processing Elements (IOPEs).
Processing Module
A basic unit in the WILDSTAR A5 /PCIe architecture consisting of a computational processing element
(CPE) and its associated ports, buses, clocks, and Flash.
QDR II SRAM
Quadruple-Data Rate II. A high-performance, synchronous burst SRAM capable of quadruple-data
operational modes.
Rx Abbreviation of “Receive”.
Single-ended Signaling
Uses one wire per signal, in which a single voltage is generated that the receiver compares with a fixed
reference voltage.
SRAM Synchronous Random Access Memory
Slice A slice contains two look-up tables and two flip-flops for implementing logic within a CLB (Configurable
Logic Block). On Stratix V FPGAs, there are four slices per CLB.
Synplicity®
Manufacturer of Synplify ASIC®, an application used for synthesizing ASIC designs.
Tx Abbreviation of “Transfer”.
WD Host Software
Application Programming Interface, Device Driver, and utilities.
WILDSTAR A5 /PCIe VHDL Models
Hardware models used for board-level VHDL simulation of application.

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Chapter 1: About This Manual
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WILDSTAR A5 /PCIe Hardware Reference Manual
Chapter 2: Introduction
Chapter 2: Introduction

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Chapter 2: Introduction
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Chapter 2: Introduction
WILDSTAR A5 /PCIe computing is a revolutionary technology combining user-programmable, reconfigurable
system gates with very high memory and I/O bandwidth capacities, which allow for high-density and high-
performance system designs. The Stratix V family of products is an evolution of WILDSTAR family of products with
enhancements that allow for more simplistic, but accelerated design development. Stratix V products allow for low
power consumption, which enables higher clock frequency and better noise margins. This significant power
savings greatly reduces cost.
The above FPGA platforms can be used on WILDSTAR A5 /PCIe mainboards for a variety of applications,
dependent upon customer needs. WILDSTAR A5 /PCIe mainboards allow for one IOPE and two CPEs. CPEs are
populated with QDRII+ SRAM or, optionally, DDR3 DRAM memories (see Figure 2-1).
To ensure safe and reliable processing, WILDSTAR A5 /PCIe boards come equipped with a proactive thermal
management system. Integrated thermal solutions are available, depending on configuration, application
requirements, and environmental requirements. Please refer to the thermal management section for more
information. Sensors across the board monitor power and temperature, with automatic shutdown capability to
prevent excessive heat buildup. WILDSTAR A5 /PCIe boards are built with a rugged, durable design.
WILDSTAR A5 /PCIe boards support both VHDL design flow tools and the CoreFire Next Design Suite.
• The VHDL flow consists of four steps: 1) creation of VHDL design using supplied VHDL model; 2)
simulation using the ModelTech® application; 3) synthesis using Synplicity®, and 4) place-and-routing
using Stratix V tools.
• CoreFire Next can be used to create FPGA designs for the WILDSTAR A5 /PCIe board. The CoreFire
Next Design Suite, a design application tool developed by Annapolis Micro Systems, Inc., makes it
possible to create designs in a fraction of the time required for a conventional VHDL-based control flow
approach.
Caution
To prevent system damage, board damage, fire, and personal injury, never use the WILDSTAR
A5 /PCIe board without an appropriate thermal solution. In addition, the operational PCI chassis
should have adequate cooling and airflow to ensure a Tj < 85°C temperature for a commercial
board option, and Tj < 100°C for an industrial board option. Temperatures above this range can
result in performance degradation and component damage. Please refer to the thermal
management section for more information.

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Chapter 2: Introduction
2.1 WILDSTAR A5 /PCIe Board Architecture
The WILDSTAR A5 /PCIe architecture is best illustrated in terms of Computational Processing Elements (CPEs)
and I/O Processing Elements (IOPEs). WILDSTAR A5 /PCIe boards are populated with CPE0, CPE1, and IOPE0.
Both DRAM and SRAM memories can be built into the board. This manufacturing build option is specified when a
board is purchased.
2.2 About the WILDSTAR A5 /PCIe Board
The WILDSTAR A5 /PCIe architecture (see Figure 2-1) has a number of processing configuration options, with the
full architecture containing three processing elements.
The host computer can communicate with the WILDSTAR A5/PCIe board using the Gen 3 16x PCIe bus. Full DMA
is supported to and from the board for a theoretical bidirectional bandwidth of 16 GBytes per second. Each FPGA
has an 8x PCIe Gen 3 bus connection.
The CPEs are connected by a 8 pin differential data bus, and 20 lanes of HSS. There are also an 8 pin differential
data bus and seven lanes of HSS connecting each CPE to the IOPE.
The WILDSTAR A5 /PCIe card can support three QSFPs for rear panel high speed I/O.
The WILDSTAR A5 /PCIe board also supports stackable mezzanine cards, offering a variety of high-fidelity analog
and high speed digital I/O solutions.
The external power connector allows for additional power input to the board. Please refer to Thermal and Power
Management for more information.
The WILDSTAR A5 /PCIe is well-equipped for power monitoring and thermal management. For additional
information, see Thermal and Power Management.

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Chapter 2: Introduction
Figure 2-1: WILDSTAR A5 /PCIe Block Diagram
A host computer can communicate with the WILDSTAR A5 /PCIe board via the PCI Express interface. The PCIe switch
has a Non Transparent Port facing the host system which allows PCIe traffic to reach the FPGAs through the switch and
looks like a single endpoint to the host system.
CPE0
Altera Stratix® V
5SGSD4, 5SGSD5,
5SGSD6, 5SGSD8,
5SGXA3, 5SGXA4,
5SGXA5, 5SGXA7,
5SGXA9, 5SGXAB
36
CPE1
Altera Stratix® V
5SGSD4, 5SGSD5,
5SGSD6, 5SGSD8,
5SGXA3, 5SGXA4,
5SGXA5, 5SGXA7,
5SGXA9, 5SGXAB
8X/16X PCI Express (Gen 1, 2, 3)
96
Copyright 2012-14
Annapolis Micro Systems, Inc.
QDRII+ SRAM
2, 4, 8, 16 MB
IOPE0
Altera Stratix® V
5SGSD4, 5SGSD5,
5SGSD6, 5SGSD8,
5SGXA3, 5SGXA4,
5SGXA5, 5SGXA7,
5SGXA9, 5SGXAB
Gen 3 PCIe
Switch
+12V
Ext PWR
Conn
IRIG-B Option
GPIO
12
QDRII+ SRAM
2, 4, 8, 16 MB
DDR3 DRAM
0GB, 2GB DDR3 DRAM 0GB, 2GB
QDRII+ SRAM
2, 4, 8, 16 MB
QDRII+ SRAM
2, 4, 8, 16 MB
QDRII+ SRAM
2, 4, 8, 16 MB
QDRII+ SRAM
2, 4, 8, 16 MB
36
36
36
36
36
36
36
36
36
36
36
QDRII+ SRAM
2, 4, 8, 16 MB
QDRII+ SRAM
2, 4, 8, 16 MB
QDRII+ SRAM
2, 4, 8, 16 MB
QDRII+ SRAM
2, 4, 8, 16 MB
QDRII+ SRAM
2, 4, 8, 16 MB
QDRII+ SRAM
2, 4, 8, 16 MB
36
36
36
36
36
36
36
36
36
36
36
36
QSFP+
QSFP+
QSFP+
Mezz 0
2nd Slot
Mezz 0
Mfg Options
OR
SignalTap
IRIG-B Data
6464
Trig/1PPS
8 Bits Data
8
8
8
8
7
4
4
7
4
4
2044
JTAG
8
16
96
DDR3 DRAM
0GB, 1GB
Alternate CPE Memory Option 32
Legend
Pluggable
Module
Manufacturing
Option
PCI Express
Up to Gen3
(7 Gbytes/s per 8x connection)
Differential Pairs
Single Ended
HiSpeed Serial IO
XCVR Speed 1 up to 14.1 Gbits/s
(1.71 Gbytes/s per Lane)
XCVR Speed 2 up to 12.5 Gbits/s
(1.52 Gbytes/s per Lane)

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Chapter 2: Introduction
2.2.1 WILDSTAR A5 /PCIe Features
WILDSTAR A5 /PCIe has the following system support features:
•Uses three Stratix V FPGAs with up to 952,000 logic blocks and 550 MHz performance. Both the IOPE and
the CPEs can be populated with Stratix V 5SGSD4, 5SGSD5, 5SGSD6, 5SGSD8, 5SGXA3, 5SGXA4,
5SGXA5, 5SGXA7, 5SGXA9 5SGXAB FPGAs.
• 8X/16X PCIe Gen1, Gen 2, or Gen 3 to Host
• Gen 3 PCIe Between FPGAs On Board with PCIe Switch
• Up to 3926 18x18 Variable Precision Multipliers
• 28-nm copper CMOS process
• 36 high speed serial (HSS) transceivers per FPGA operating at up to 14.1Gbps
• Two Memory Banks of DDR3 DRAM at up to 800 MHz (1600 MT/s) per IOPE
• Up to approximately 25 GB/s of DRAM bandwidth per IOPE
• Up to 4GBbyes of IOPE DDR3 DRAM per board
• Option of either Six Memory Banks of QDRII+ SRAM at up to 550 MHz or Six Memory Banks of DDR3
DRAM at up to 800 MHz per CPE
• Up to approximately 38 GB/s (DRAM option) or 39 GB/s (SRAM option) of memory bandwidth per
CPE
• Up to 192 MBytes of CPE QDRII+ SRAM or 12 GBytes of DDR3 DRAM per board
• Three Optional QSFP+ Connectors Provide:
• Twelve 10 Gbps Ethernet or Three 40Gbps Ethernet or Three 14Gbps FDR Infiniband
• Multi-Thread Safe Software Support
• Supports PCI Express Standard External Power Connector
• Multicolor status LED for each PE
• Supports up to two standard I/O mezzanine cards. Two mezzanine cards requires stacking and two
slots.
• Clocks
• PCLK: Processor Clock, independently programmable per FPGA and differential
• HSS Reference Clocks: Six High Speed Reference clocks per IOPE, two per CPE