Apex Instrument Discovery-III XC3S200F User manual

FPGA Discovery-III XC3S200 Board Manual V1 0 (REV5, 9/3/2007)
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FPGA Discovery-III XC3S200F
FPGA Discovery-III XC3S200F4
Board Manual
    APEX I STRUME T CO., LTD.
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FPGA Discovery-III XC3S200 Board Manual V1 0 (REV5, 9/3/2007)
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FPGA Discovery-III XC3S200
 FPGA Discovery-III XC3S200  1  200,000 -
400,000  Platform Flash PROM   Platform Flash PROM 
 JTAG 
  LAB  
 1  FPGA Discovery-III XC3S200
1) 
 FPGA Discovery-III XC3S200  2 
•FPGA Discovery-III XC3S200F ( 200,000 )
•FPGA Discovery-III XC3S200F4 ( 400,000 )
 FPGA Discovery-III XC3S200F  FPGA Discovery-III XC3S200F4  
 FPGA Discovery-III XC3S200F  FPGA  Spartan-3  Xilinx  XC3S200-4TQ144C (
XC3S200-4TQG144C)  FPGA  200,000 , Package  TQ144, Speed Grade:4  Platform Flash
PROM  XCF01SVO20C ( XCF01SVOG20C)  FPGA Discovery-III XC3S200F4  FPGA 
XC3S400-4TQ144C ( XC3S400-4TQG144C)  FPGA  400,000  Package  TQ144, Speed Grade:4 
Platform Flash PROM  XCF02SVO20C ( XCF02SVOG20C)   20,000 


FPGA Discovery-III XC3S200 Board Manual V1 0 (REV5, 9/3/2007)
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•7-Segment  4  ( Expansion ports )
•LED  8  ( Expansion ports  I/O  RNET3  RNET4 )
•Buzzer  1  ( Expansion ports)
• DIP Switch 8 
•Push Botton Switch  5 
•Expansion ports ( 80 Bits 3 3V I/O )
•RS-232C Port 1 Port ( Expansion ports)
•I2C Socket  EEPROM ( Expansion ports)
•25 Mhz Oscillator (  Digital Frequency Synthesizer  FPGA)
2)  FPGA  Spartan-3  XC3S200
• 200,000 
•18Kb block RAMs  12  ( 216Kb)
•18x18 hardware multiplier  12 
•Digital Clock Manager (DCM)  4 
3)  FPGA  Spartan-3  XC3S400
• 200,000 
•18Kb block RAMs  16  ( 288Kb)
•18x18 hardware multiplier  16 
•Digital Clock Manager (DCM)  4 

1. 18Kb block RAM
18Kb block RAM  ( ) 200 Mhz 
RAM  ROM   FIFO   2  RAM  Single Port  3
 RAM  Single Port   Block RAM 
 2  RAM  Single Port
 3 RAM  Single Port   Block RAM 

FPGA Discovery-III XC3S200 Board Manual V1 0 (REV5, 9/3/2007)
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2. 18x18 Hardware multiplier
18x18 hardware multiplier  18x18  
 4 
 4  18x18 hardware multiplier
3. Digital Clock Manager
Digital Clock Manager (DCM)   4  

 DCM  5  DCM
 5  DCM
• (Clock Divider)   1 5,
2, 2 5, 3, 3 5, 4, 4 5, 5, 5 5, 6, 6 5, 7, 7 5, 8, 9, 10, 11,12, 13, 14, 15,  16 
• (Clock Doubler )  2 
•Digital Frequency Synthesizer (DFS) 
 M/D  M = 2  32  D = 1  32   66 66666 Mhz 
 25 Mhz  DFS  M=8 D=3 Delay-Locked Loop (DLL)

•Quadrant Phase Shift  90 , 180  270  
•Fine Phase Shift   1/ 255 
4) 
 FPGA Discovery-III XC3S200  6  7
 I/O () 8  FPGA (I/O List)  1

FPGA Discovery-III XC3S200 Board Manual V1 0 (REV5, 9/3/2007)
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 6 
 7  FPGA Discovery-III XC3S200

FPGA Discovery-III XC3S200 Board Manual V1 0 (REV5, 9/3/2007)
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 8  I/O  FPGA Discovery-III XC3S200()
 1  FPGA (I/O List)

FPGA Discovery-III XC3S200 Board Manual V1 0 (REV5, 9/3/2007)
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 1  FPGA (I/O List) ()
 1  FPGA (I/O List) ()

FPGA Discovery-III XC3S200 Board Manual V1 0 (REV5, 9/3/2007)
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 1  FPGA (I/O List) ()
 1  FPGA (I/O List) ()

FPGA Discovery-III XC3S200 Board Manual V1 0 (REV5, 9/3/2007)
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4.1) 
a) LED 
 LED  8  LED0LED7  (Cathode) 
 I/O  FPGA  R=470  RNET3  RNET4 
 9  FPGA  1  LED   I/O  LED  I/O 
 K3  K4  ( 1 )  I/O  K3  K4 
 LED 
 9  LED  CPLD
b) 
 (7-Segment)  4  DIGIT4 - DIGIT1 
 (Common Common)  10  4 
  2530  
 30 x4  = 120 
 1
 0  COM   R1R8  100  
DIGIT2  DIGIT1 (dp) : (Colon) 
 
 10  (7-Segment)  4 

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 I/O  I/O  K1  K/  ( 1 ) 
 I/O  K1  K2 
c) 
 (Buzzer)  1  I/O  FPGA  11  FPGA  1
Buzzer   Buzzer  0  I/O  Buzzer  I/O  40  K3
 I/O  K3  Buzzer  Jumper J3 
 11  Buzzer  FPGA
4.2) 
 K1- K4  I/O 1  K1- K4 
 (Cross talk)  (Flat
Cable)
 I/O  K1  K4 
()  
  LED    I/O  3 3V
 
 40   1520  (
- CD ) 
  I/O  FPGA  Slow Slew Rate 
  Transmission Line
effect  PCB    < (2/nS) x (Rise time) 
 O/P  FPGA  Fastslew rate  < 1 nS  Slow slew rate 
 < 3 nS  (2/nS) x 3 nS = 6 = 15  ( 20 ) 
  Terminate 
 Vcc  0 1 uF  10 nF
 (Chip capacitor)  Vcc   (
)  Vcc  AC 
 Vcco  3 3V  I/O  3 3V  I/O 2  
LVCMOS33  LVTTL  2  FPGA  LVTTL (IOSTANDARD = LVTTL)
 Slow slew Rate (SLEW = SLOW)  Edit Constraints(Text)12  PACE  13
 FPGA  3 3V 5V ( 74LS00, 74HCT00)  FPGA 
 3 3V   FPGA  5 V 14(a) 
CPLD  XC9500XL  3 3V  5V  14(b)  (Pulled up)
 Jumper J2   J2 