Applistar DNPCIe 10G K7 LL QSFP User manual

DINI GROUP
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UserManual
DNPCIe_10G_K7_LL(_QSFP)

L O G I C E M U L A T I O N S O UR CE
DNPCIe_10G_K7_LL (_QSFP) User Manual Version
1.9
DateofPrintDecember12,2017
Dini Group 2012-2017
7469 Draper Ave.
La Jolla, CA92037
Phone [phone] • Fax [phone]
[e-mail]
www.dinigroup.com

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Dini Group has made reasonable efforts to ensure that the information in this document is accurate and
complete. However, the Dini Group assumes no liability for errors, or for any incidental, consequential,
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lost profits or savings, arising from the use of this document or the product which it accompanies.

Table of Contents
INTRODUCTION ............................................................................................................................................................................................................................1
1DNPCIE_10G_K7_LL (_QSFP) ETHERNET PACKET ANALYSIS ENGINE .........................................................................................................1
1.1 Overview.........................................................................................................................................................................................................................1
1.2 FPGA –Xilinx, Kintex-7 ...............................................................................................................................................................................................1
1.3 Two Channels of 10 GbE or Four Channels of 10 GbE for the _QSFP version.......................................................................................................2
1.4 QDR II+ SSRAM - Memory with the Lowest Latency.................................................................................................................................................2
1.5 DDR3 DRAM - Bulk Memory .......................................................................................................................................................................................2
1.6 PCI Express –Customizable 4-lane, GEN2 PCI Express...........................................................................................................................................3
1.7 Time Synchronization ....................................................................................................................................................................................................3
1.8 How Everything Works … .............................................................................................................................................................................................3
2DNPCIE_10G_K7_LL (_QSFP) ETHERNET PACKET ANALYSIS ENGINE FEATURES.......................................................................................4
3PACKAGE CONTENTS:............................................................................................................................................................................................6
4INSPECT THE BOARD..............................................................................................................................................................................................6
5ADDITIONAL INFORMATION..................................................................................................................................................................................7
GETTING STARTED .....................................................................................................................................................................................................................8
1BEFORE YOU BEGIN ..............................................................................................................................................................................................8
1.1 Configuring the Programmable Components..............................................................................................................................................................8
1.2 Warnings ........................................................................................................................................................................................................................8
2INSTALLING THE SOFTWARE .................................................................................................................................................................................8
2.1 Exploring the Customer Support Package...................................................................................................................................................................9
3BOARD SETUP ........................................................................................................................................................................................................9
3.1 Before Powering Up the Board ....................................................................................................................................................................................9
3.2 Cooling Requirements –IMPORTANT!! ...................................................................................................................................................................10
3.3 Powering Up the Board...............................................................................................................................................................................................10
4USING THE REFERENCE DESIGN (MAIN) ............................................................................................................................................................11
PROGRAMMING/CONFIGURING THE HARDWARE......................................................................................................................................................14
1INTRODUCTION ....................................................................................................................................................................................................14
2CONFIGURING THE FPGA USING JTAG .............................................................................................................................................................15
2.1 Setup - Configuring the FPGA using JTAG ...............................................................................................................................................................15
2.2 Powering Up the Board...............................................................................................................................................................................................15
2.3 Installing Digilent cable driver...................................................................................................................................................................................15
2.3.1 Windows ..............................................................................................................................................................................................................15
2.3.2 Linux ....................................................................................................................................................................................................................16
2.4 Configuring the FPGA ................................................................................................................................................................................................17
3CONFIGURING THE FPGA USING MASTER BPI..................................................................................................................................................18
3.1 Setup - Configuring the FPGA using Master BPI .....................................................................................................................................................19
3.2 Powering Up the Board...............................................................................................................................................................................................19
3.3 Configuring the FPGA ................................................................................................................................................................................................19
3.4 Using multiple FPGA “boot” images for configuration fallback ............................................................................................................................21
4USING CHIPSCOPE PRO (VIA JTAG)...................................................................................................................................................................22
4.1 Setup –Using ChipScope Pro (via JTAG) .................................................................................................................................................................23
4.2 Powering Up the Board...............................................................................................................................................................................................23
4.3 Configuring the FPGA ................................................................................................................................................................................................23
HARDWARE DESCRIPTION ....................................................................................................................................................................................................25

1DESCRIPTION........................................................................................................................................................................................................25
1.1 Overview.......................................................................................................................................................................................................................25
1.2 FPGA –Xilinx, Kintex-7 .............................................................................................................................................................................................26
1.3 Two Channels of 10 GbE or Four Channels of 10 GbE for the _QSFP version.....................................................................................................26
1.4 QDR II+ SSRAM - Memory with the Lowest Latency...............................................................................................................................................27
1.5 DDR3 DRAM - Bulk Memory .....................................................................................................................................................................................27
1.6 PCI Express –Customizable 4-lane, GEN2 PCI Express.........................................................................................................................................27
1.7 Time Synchronization ..................................................................................................................................................................................................28
2FPGA (KINTEX-7) ...............................................................................................................................................................................................28
2.1 FPGA Configuration ...................................................................................................................................................................................................28
2.2 USB Port (RS232/JTAG) .............................................................................................................................................................................................28
2.2.1 RS232/JTAG Circuit Diagram ...........................................................................................................................................................................28
2.2.2 Connections between FPGA and the RS232 Port .............................................................................................................................................29
2.3 QDR II+ SRAM Memory.............................................................................................................................................................................................29
2.3.1 QDRII+ SRAM Memory Architecture ..............................................................................................................................................................30
2.3.2 Design Guidelines –QDR II+ SRAM IO Standards.........................................................................................................................................30
2.3.3 Connections between FPGA and QDR II+ SRAM Devices (4M x 18)...........................................................................................................31
2.4 DDR3 Memory (VLP MINIUDIMM) .........................................................................................................................................................................33
2.4.1 DDR3 SDRAM Memory Interface Solution .....................................................................................................................................................33
2.4.2 Design Guidelines - DDR3 Termination ...........................................................................................................................................................34
2.4.3 Design Guidelines –DDR3 IO Standards .........................................................................................................................................................35
2.4.4 Serial Presence-Detect EEPROM Operation.....................................................................................................................................................35
2.4.5 Clocking Connections between FPGA and MINIUDIMM ..............................................................................................................................36
2.4.6 Connections between FPGA and MINIUDIMM ..............................................................................................................................................36
2.5 EEPROM ......................................................................................................................................................................................................................41
2.5.1 EEPROM Circuit Diagram .................................................................................................................................................................................41
2.5.2 Connections between FPGA and the EEPROM................................................................................................................................................41
2.6 PCI Express Interface (x4)..........................................................................................................................................................................................41
2.6.1 System Requirements..........................................................................................................................................................................................42
2.6.2 Clocking - Jitter Attenuator ................................................................................................................................................................................42
2.6.3 PCI Express Circuit .............................................................................................................................................................................................42
2.6.4 Connections between FPGA and PCI Express Edge Connector ......................................................................................................................42
2.7 SFP+ Interface (only for DNPCIe_10G_K7_LL) .....................................................................................................................................................43
2.7.1 SFP+ Circuit Diagram.........................................................................................................................................................................................43
2.7.2 LED indicators.....................................................................................................................................................................................................44
2.7.3 SFP+ Pin Assignments........................................................................................................................................................................................45
2.7.4 Connections between FPGA and the SFP+ Connectors ...................................................................................................................................45
2.8 QSFP+ Interface (only for the DNPCIe_10G_K7_LL_QSFP) ................................................................................................................................47
2.8.1 QSFP+ Circuit Diagram......................................................................................................................................................................................47
2.8.2 LED indicators.....................................................................................................................................................................................................48
2.8.3 QSFP+ Pin Assignments.....................................................................................................................................................................................48
2.8.4 Connections between FPGA and the QSFP+ Connectors ................................................................................................................................49
2.9 Time Synchronization ..................................................................................................................................................................................................51
2.9.1 Time Synchronization Circuit Diagram .............................................................................................................................................................51
2.9.2 Connections between the FPGA and Time Synchronization Circuitry ...........................................................................................................51
3CLOCK GENERATION ...........................................................................................................................................................................................52
3.1 System Clock –IDELAYCTRL ....................................................................................................................................................................................52
3.1.1 Connection between FPGA and the System Clock Oscillator..........................................................................................................................52
3.2 High-Speed (GTX) Clocks...........................................................................................................................................................................................52
4LED INDICATORS ................................................................................................................................................................................................52
4.1 FPGA Status LEDs ......................................................................................................................................................................................................52
4.2 Configuration DONE LEDs ........................................................................................................................................................................................53
5POWER DISTRIBUTION.........................................................................................................................................................................................53
5.1 In-System Operation ....................................................................................................................................................................................................53
6MECHANICAL .......................................................................................................................................................................................................53
6.1 Board Dimensions .......................................................................................................................................................................................................53
APPENDIX 55
1APPENDIX A: UCF FILE......................................................................................................................................................................................55
2ORDERING INFORMATION ...................................................................................................................................................................................55

List of Figures
Figure 1 - DNPCIe_10G_K7_LL (_QSFP) Ethernet Packet Analysis Engine. (upper picture is the DNPCIe_10G_K7_LL and lower picture is the
DNPCIe_10G_K7_LL_QSFP) ..................................................................................................................................................................................................................4
Figure 2 - USB Flash Drive Directory Structure...........................................................................................................................................................................................................9
Figure 3 - DNPCIe_10G_K7_LL (_QSFP) Block Diagram –Note the two SFP+ modules are replaced with one QSFP+ module in the _QSFP version ....... 26
Figure 4 –FPGA Serial Port............................................................................................................................................................................................................................................ 29
Figure 5 - QDR II+ Memory Architecture................................................................................................................................................................................................................. 30
Figure 6 –FPGA Serial Port............................................................................................................................................................................................................................................ 41
Figure 7 - SFP+ Channel 0 Interface ........................................................................................................................................................................................................................... 44
Figure 8 –SFP+ GTX Oscillator.................................................................................................................................................................................................................................. 44
Figure 9 - QSFP+ Channel 0 Interface........................................................................................................................................................................................................................ 47
Figure 10 –QSFP+ GTX Oscillator............................................................................................................................................................................................................................ 48

List of Tables
Table 1 –USB Flash Drive Directory Contents ...........................................................................................................................................................................................................9
Table 2 –Kintex-7 Uncompressed Bitstream Length .............................................................................................................................................................................................. 18
Table 3 - Connections between RS232 Port and the FPGA................................................................................................................................................................................... 29
Table 4 –QDR II+ SRAM IO Standards................................................................................................................................................................................................................... 30
Table 5 - Connections between FPGA and the QDR II+ SRAM Devices ........................................................................................................................................................ 31
Table 6 - Serial Presence-Detect EEPROM Connections....................................................................................................................................................................................... 35
Table 7 –Clocking Connections between FPGA and the UDIMM Connector ................................................................................................................................................ 36
Table 8 - Connections between FPGA and the UDIMM Connector .................................................................................................................................................................. 36
Table 9 - Connections between FPGA and the EEPROM .................................................................................................................................................................................... 41
Table 10 - Connections between FPGA and the PCI Express Edge Connector............................................................................................................................................... 43
Table 11 –SFP+ Pin Assignments ............................................................................................................................................................................................................................... 45
Table 12 - Connections between FPGA and the SFP+ Connectors .................................................................................................................................................................... 46
Table 13 –QSFP+ Pin Assignments............................................................................................................................................................................................................................ 48
Table 14 - Connections between FPGA and the QSFP+ Connectors................................................................................................................................................................. 49
Table 15 - Connection between the FPGA and the System Clock Oscillator .................................................................................................................................................... 52
Table 16 –FPGA Status LEDs ..................................................................................................................................................................................................................................... 52
Table 17 –FPGA DONE LED.................................................................................................................................................................................................................................... 53

I N T R O D U C T I O N
DNPCIe_10G_K7_LL (_QSFP) User Manual www.dinigroup.com 1
Introduction
This User Manual accompanies the DNPCIe_10G_K7_LL (_QSFP)
Ethernet Packet Analysis Engine. For specific information regarding the Xilinx
Kintex-7 parts, please referencethedatasheet onthe Xilinxwebsite.
1DNPCIe_10G_K7_LL (_QSFP) Ethernet Packet
Analysis Engine
1.1 Overview
The DNPCIe_10G_K7_LL (_QSFP) is a PCI Express based FPGA board designed
to minimize input to output processing latency on 10Gb Ethernet packets. The primary
application is for ultra-low latency, high throughput trading without CPU intervention.
Every possible variable that affects input to output latency has been analyzed and
minimized. Raw 10 GbE packets can be analyzed and acted upon without interrupts or
an operating system adding delay to the process. This configurable hardware computing
platform has the ability to achieve the theoretical minimum Ethernet packet processing
latency. This board also has a time code input to allow for precise message time
stamping and tracking.
1.2 FPGA –Xilinx, Kintex-7
The Xilinx, Kintex-7, in the FFG676 package is utilized for this product. This package
supports 400 IOs with the majority utilized. Most are dedicated to a variety of off chip
memory peripherals including QDR II+ for low-latency, high speed look-up, and
DDR3 for performance oriented bulk storage. The Kintex-7 FPGAs contain high-speed
transceiver PHYs. The GTX transceivers are capable of handling data rates of 500 Mb/s
to 12.5 Gb/s, making these applicable to 10 Gigabit Ethernet (10 GbE) and
GEN1/GEN2 PCI Express applications. Four of the GTX transceivers are used for
GEN2-capable PCIe. For the DNPCIe_10G_K7_LL version, two of the GTX
transceivers are connected to 10 GbE SFP+ sockets. For the
DNPCIe_10G_K7_LL_QSFP version, four of the GTX transceivers are connected to
the 40 GbE QSFP+ socket.
Chapter
1

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Either the XC7K325T or the XC7K410T FPGAs can be populated. Both come in three
speeds grades, with -3 being the fastest.
1.3 Two Channels of 10 GbE or Four Channels of 10 GbE for
the _QSFP version
The Kintex-7 FPGAs have transceivers capable of 10 GbE. The physical interface is
handled using SFP+ modules or a single QSFP+ module for the _QSFP verison. This
allows you to bypass a MAC if necessary and process raw Ethernet packets. The
DNPCIe_10G_K7_LL has two 10 GbE channels and the
DNPCIe_10G_K7_LL_QSFP has four 10 GbE channel, and can support
10GBASET-ER, 10GBASET-SR, 10GBASET-KR.
1.4 QDR II+ SSRAM - Memory with the Lowest Latency
One, quad data rate, static RAMs (QDR II+ SSRAM) is used in the 4M x 18 size. This
style of memory has separate input and output data paths, enabling maximum
read/write data bandwidth with minimum latency. Using -3 speed grade FPGA, this
interface is capable of running at the maximum I/O frequency of 500MHz. To
minimize processing latency, we suspect it will be best to clock these QDRII+ SSRAMs
at 312.50 MHz, exactly twice the internal Ethernet controller frequency of 156.25MHz.
The Kintex-7 FPGAs are capable of generating internal 2x clocks that are phase
synchronous, eliminating the latencies associated with the tricky re-synchronization of
data moving between different clock frequencies. The internal controller can be
optimized in any way you choose. Dini Group provides several Verilog examples. All
functions of the QDR II+ SSRAM can be exploited, including concurrent read and
write operations and four-tick bursts. The only real limitation is the amount of time and
effort spent in customizing the individual memory controllers.
1.5 DDR3 DRAM - Bulk Memory
A single 244-pin PC3-10600 DDR3 VLP MINIUDIMM socket enables up to 4GB of
memory for bulk storage and lookup. Using a -2 or -3 speed grade FPGA, this interface
is tested at the maximum FPGA I/O frequency: 666.5Hz (1333Mb/s with DDR). The
user can use this memory as 64-bits with 8 bits of error correction (ECC), or as a 72-bit
byte-memory without correction.
To minimize data synchronization across clock boundaries, it probably makes sense to
clock the DDR3 interface at a 3x multiple of the base Ethernet frequency of 156.25
MHz, which is 468.75MHz. A 3x phase synchronous clock can be easily generated
internal to the FPGA, allowing zero latency synchronous data transfers between the
Ethernet packet receiving logic and the DDR3 memory controller. The DDR3
controller can be optimized in any way you choose. We, of course, provide several
Verilog examples. All functions of the DDR3 DRAM can be exploited and optimized.
Timing variables such as CAS latency and precharge can be tailored to the minimum
given your operating frequency and the timing specification of the exact DDR3 memory

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DNPCIe_10G_K7_LL (_QSFP) User Manual www.dinigroup.com 3
utilized. As with the QDRII+ SRAM, the only real limitation is the amount of time and
effort spent customizing the DDR3 memory controller to your needs.
1.6 PCI Express –Customizable 4-lane, GEN2 PCI Express
PCI Express is connected directly to the FPGA via 4-lanes of GTX transceivers. The
interfaces are GEN2 capable, and the board is shipped with PCIe IP that is a full
function, fixed, 4-lane master/target. To gain access to the PCIe interface, this IP must
be integrated with the user application. Dini Group provides support with the IP,
including BAR sizes. Additionally we can optionally add or subtract DMA engines,
scratchpad memories, interrupts, and other host-related functions to maximize the
performance, while utilizing the minimum FPGA resources. 'C' source for drivers for
several operating systems are included no charge. Partial reconfiguration of the FPGA is
supported via the PCIe interface.
1.7 Time Synchronization
The time code input allows for precise message time stamping and tracking. This input
can receiver PPS, or IRIG-B000 (RS232, RS485, RS422, TLL).
1.8 How Everything Works …
With direct data feeds such as NASDAQ (ITCH/OUCH) or Financial Information
Exchange (FIX), the DNPCIe_10G_K7_LL (_QSFP) contains all of the basic
functions required to minimize the amount of time it takes to receive Ethernet packets,
process them, and respond deterministically. The MAC, operating system et al, can be
bypassed. There are no interrupts. No operating system. Not a single clock cycle is
wasted here, enabling a near theoretical minimum in-to-out response time. For
algorithms requiring processing, FPGA resources can be hard coded to perform the
task. This includes real-time Monte Carlo analysis and floating point, all operating 1000's
of times faster than possible in a processor-based approach.

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2DNPCIe_10G_K7_LL (_QSFP) Ethernet Packet
Analysis Engine Features
Figure 1 - DNPCIe_10G_K7_LL (_QSFP) Ethernet Packet Analysis Engine. (upper picture is the DNPCIe_10G_K7_LL and lower
picture is the DNPCIe_10G_K7_LL_QSFP)
DNPCIe_10G_K7_LL (_QSFP) Kintex-7 Board features the following:
Hosted in a 4-lane (16-lane mechanical, with notches to allow to be plugged into
x4/x8/x16) PCI Express Slot (GEN2) or Stand-alone
Xilinx Kintex-7 FPGA (FFG676)
oXC7K325T (-3, -2, -1 fastest to slowest)
oXC7K410T (-3, -2, -1 fastest to slowest)
GTX Transceivers (10Gb/s)
oPCI Express (x4)
oTwo SFP+ modules (x1 each)
oQSFP+ module (x4), only with _QSFP version

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DNPCIe_10G_K7_LL (_QSFP) User Manual www.dinigroup.com 5
Flexible Clock Resources
oPCI Express Clock Jitter Attenuator –250MHz
oOscillators for GTX Transceivers
Memory
oBulk Memory: DDR3 VLP MINIUDIMM (244-pin)
72-bit data width (64-bit with 8-bit ECC)
PC3-10600 (666.5MHz)
Addressing/power to support 4GB (+ ECC)
DDR3 Verilog/VHDL reference design provided.
oQDRII + SSRAM
1 channels: 4M x 18 (72Mb)
500 MHz bus operation, DDR (double data rate)
Fast enough to be clocked at 312.50 MHz
Eliminates clock synchronization delays between memory and
Ethernet clock.
User LED’s
Time Synchronization
o2.5mm jack that accepts PPS and IRIG-B000
(RS232/RS485/RS422/TTL) time code.
Onboard Distributed Power Supplies
Full support for Embedded Logic Analyzers and Debug
oChipScope Logic Analyzer
oInPA, Veridae, SpringSoft
USB-B 2.0 Port
oRS232
oJTAG
The FIX board support package (DN_FBSP) for the DNPCIe_10G_K7_LL
(_QSFP) is a functioning reference design with the following components:
o10-Gigabit Ethernet MAC
oTCP/IP Offload Engine (TOE)
oFIX protocol parser

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oPCIe Interface (4-lane, GEN2)
oMemory
oQDRII+ Controller
oDDR3 Controller
3Package Contents:
Before using the kit or installing the software, be sure to check the contents of the kit
and inspect the board to verify that you received all of the items. If any of these items
are missing, contact Dini Group before you proceed. The DNPCIe_10G_K7_LL
(_QSFP) Ethernet Packet Analysis Engine includes the following:
USB Flash Drive (4GB) –USB007, P/N UFDCR-4096
USB 2.0 Cable –NewEgg, P/N N82E16812119030
VLP MINIUDIMM DDR3 2GB (PC3-10600), 244 Pin, Micron, P/N
MT9JBG25672AKZ-1G4
DB9 to 2.5mm cable. P/N BC20223-6
Customer Support Package (on USB Flash Drive)
oDocumentation (Datasheets, User Manual and Schematics)
oFPGA Reference Designs (Verilog)
oHost Software (AETest)
Cooling Requirements for DNPCIE_10G_K7_LL.pdf
Optional Items
SFP+ Direct Cable 10GbE Copper, 1.6ft –Amphenol, P/N SF-SFPP2EPASS-
000.5
4Inspect the Board
Place the board on an anti-static surface and inspect it to ensure that it has not been
damaged during shipment. Verify that all components are on the board and appear
intact.

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5Additional Information
For additional information, please visit http://www.dinigroup.com/. The following
table lists some of the resources you can access from this website. You can also directly
access these resources using the provided URLs.
Resource
Description/URL
User Manual
This is the main source of technical information. The manual
should contain most of the answers to your questions
Demonstration
Videos
MEG-Array Daughter Card header insertion and removal video
Dini Group
Web Site
The web page will contain the latest user manual, application notes,
FAQ, articles, and any device errata and manual addenda. Please
visit and bookmark: http://www.dinigroup.com
Data Book
Pages from 7-Series Databook, which contains device-specific
information on Xilinx device characteristics
E-Mail
You may direct questions and feedback to Dini Group using this e-
mail address: [e-mail]
Phone Support
Call us at 858.454.3419 during the hours of 8:00am to 5:00pm
Pacific Time.
FAQ
The download section of the web page may contain a document
called DNPCIe_10G_K7_LL (_QSFP) Frequently Asked
Questions (FAQ). This document is periodically updated with
information that may not be in the User’s Manual.

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DNPCIe_10G_K7_LL (_QSFP) User Manual www.dinigroup.com 8
Getting Started
Congratulations on your purchase of the DNPCIe_10G_K7_LL
(_QSFP) EthernetPacket Analysis Engine. The remainder of this
chapter describes how to start using the DNPCIe_10G_K7_LL
(_QSFP) EthernetPacket Analysis Engine.
1Before You Begin
1.1 Configuring the Programmable Components
The DNPCIe_10G_K7_LL (_QSFP) has been factory tested and pre-programmed to
ensure correct operation. The user does not need to alter any jumpers or program
anything to see the board work.
1.2 Warnings
Mechanical Stress –Inserting and removing VLP MINIUDIMM and the
board from the motherboard can add additional stress that may cause board
failures.
ESD Warning - The board is sensitive to static electricity, so treat the PCB
accordingly. The target markets for this product are engineers that are familiar
with FPGAs and circuit boards. However, if needed, the following web page
has an excellent tutorial on the “Fundamentals of ESD” for those of you who
are new to ESD sensitive products:
http://en.wikipedia.org/wiki/Electrostatic_discharge
2Installing the Software
No Software installation required.
Chapter
2

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2.1 Exploring the Customer Support Package
The USB Flash Drive contains the following items, see Figure 2:
Documentation
FPGA Reference Designs
Host Software
Figure 2 - USB Flash Drive Directory Structure
A description of the USB Flash Drive directory contents is listed in Table 1. Please visit
the Dini Group website for the most recent revision of these documents.
Table 1 –USB Flash Drive Directory Contents
USB Flash Drive Directory Contents
Directory Name
Description of Contents
Documentation
Contains the Datasheets, Schematics and
User Manual for the board.
FPGA Reference Designs
Contains the source and compiled
programming files for the
DNPCIe_10G_K7_LL (_QSFP) reference
designs.
Host Software
Provides the Host Software for the Windows
and Linux platforms.
3Board Setup
The instructions in this section explain how to install the DNPCIe_10G_K7_LL
(_QSFP) Ethernet Packet Analysis Engine. For the purpose of this demonstration, the
DNPCIe_10G_K7_LL (_QSFP) will be configured using a motherboard’s PCIE
connectors for power and the USB interface.
3.1 Before Powering Up the Board
Before powering up the board, prepare the board as follows:
1. If the kit contains a Memory VLP MINIUDIMM module, populate the VLP
MINIUDIMM socket J7.

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2. Plug board into x4, x8, or x16 PCIE slot.
3. Connect the “USB 2.0 Cable” to the USB-B connector on the bracket.
3.2 Cooling Requirements –IMPORTANT!!
This board is shipped with a passive heatsink that requires external
airflow in order to prevent the FPGA from exceeding the upper limit of its
recommended operating temperature (85C).
When using the mainref bit file that is loaded on the board when shipped,
the FPGA will power down if the die temperature exceeds 85C and will
power back up as previously configured once the die temperature goes
down to 70C. Unless there is enough cooling directed at the board, the
FPGA will repeatedly go from the power down state back to the normal
state every ~1-2minutes depending on the environment.
Requirements for user design to use the internal XADC temperature
monitoring to ensure that the FPGA does not exceed its recommended
operating temperature:
1. Enable bitgen option “OverTempPowerDown”, or alternatively, the
automatic power down can be enabled by using a configuration
option in the ISE design tools. To generate a programming file, the
user checks the “Power Down Device if Over Safe Temperature”
option under “Configuration Options” on the Process Properties GUI.
Either of these options default to 125C being the Over Temperature
threshold.
2. Set user defined thresholds in the control registers of the XADC.
More information about calculating the temperature and setting the
registers can be found in the UG480 “7 Series FPGAs XADC User
Guide” under “Temperature Sensor” and “Thermal Management”.
3.3 Powering Up the Board
1. Power up the board by turning ON the power to the motherboard verify the
“+12V” LED (DS16) is ON indicating the presence of +12V (located on the
back-side of the board near the top-left.)
2. USB drivers should automatically install when the board turns on. If this doesn’t
happen then install the USB driver from the FTDI website (for driver
Note: The DNPCIe_10G_K7_LL (_QSFP) Ethernet Packet Analysis Engine is
shipped with a passive heat sink for operation in a server or PC with forced cooling. If
the board is used in standalone mode, please provide an external fan to prevent the
FPGA from overheating!

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installation, please refer to
http://www.ftdichip.com/Support/Documents/InstallGuides.htm).
3. Once drivers are finished installing, open a Terminal Emulator and configure
the session as follows:
4Using the Reference Design (Main)
This section lists detailed instructions for executing the reference design. Ensure the
DNPCIe_10G_K7_LL (_QSFP) Ethernet Packet Analysis Engine is powered ON and
a Terminal Window is open to exercise the reference design options;
1. Select test option (6), “Clock Frequencies Check” in the Terminal window and
verify that the test displays VALID frequencies.

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2. Select test option (0), “DDR3 Test (requires ECC module)” in the Terminal
window and verify that the test PASS (periods will be displayed as the memory
locations are being tested, if no DDR3 Module is present, the test will display
read/write errors).
3. Select test option (3), “QDR2 Test” in the Terminal window and verify that the
test PASS (periods will be displayed as the memory locations are being tested, if
no QDR2 Memory fails, the test will display read/write errors).

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The remainder of the reference design functional tests requires various loop-back test
boards/modules to make them PASS, and is not covered in this User Manual. Please
reference the Customer Support Package (on USB Flash Drive) for code examples. The
next section describes configuring and programming the hardware in detail.