APPOTECH AX2228D User manual

AX2228D
Audio Player Microcontroller
User Manual
[AX2228D -UM-EN]
Versions: 1.0.0
Release Date: 2015-9-2

II Table of content
AX2228D Audio Player Microcontroller Version 1.0.0
Copyright © 2015, www.appotech.com. All Rights Reserved.
Table of content
Table of content ........................................................................................................................................ II
Figure........................................................................................................................................................ VI
Table ......................................................................................................................................................... VI
Register.................................................................................................................................................... VII
1Product Overview.............................................................................................................................. 1
1.1 Outline........................................................................................................................................ 1
1.2 Features...................................................................................................................................... 1
1.3 System Architecture................................................................................................................... 2
2Pin Definitions ................................................................................................................................... 3
2.1 AX2228D..................................................................................................................................... 3
2.1.1 Packages ............................................................................................................................. 3
2.1.2 Pin Assignment ................................................................................................................... 3
2.1.3 Pin Descriptions .................................................................................................................. 3
3CPU Core Information ....................................................................................................................... 8
3.1 Architecture ............................................................................................................................... 8
3.2 Instruction Set ............................................................................................................................ 8
3.3 Memory Mapping .................................................................................................................... 11
3.3.1 Program Memory Mapping .............................................................................................. 11
3.3.2 External Data Memory Mapping ...................................................................................... 12
3.3.3 Internal Data Memory Mapping....................................................................................... 12
3.4 Interrupt Processing................................................................................................................. 13
3.4.1 Interrupt sources .............................................................................................................. 13
3.4.2 Interrupt Priority............................................................................................................... 15
3.5 CPU and Memory related SFR Description .............................................................................. 15
4Reset Generation............................................................................................................................. 23
4.1 Power-on Reset (POR).............................................................................................................. 23
4.2 System Reset ............................................................................................................................ 23

Table of content III
AX2228D Audio Player Microcontroller Version 1.0.0
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4.2.1 LVD.................................................................................................................................... 24
4.2.2 RTCC Reset........................................................................................................................ 26
4.2.3 Watchdog Reset ............................................................................................................... 26
4.2.4 Port Wakeup Reset........................................................................................................... 26
4.3 Clock System ............................................................................................................................ 26
4.3.1 Clock Control .................................................................................................................... 26
4.3.2 Phase Lock Loop (PLL)....................................................................................................... 32
5Low Power Management ................................................................................................................ 36
5.1 Power Saving Mode ................................................................................................................. 36
5.1.1 Sleep Mode....................................................................................................................... 36
5.1.2 Hold Mode........................................................................................................................ 36
5.1.3 Idle Mode.......................................................................................................................... 36
5.1.4 Deep Sleep Mode ............................................................................................................. 37
5.1.5 Power Down Mode........................................................................................................... 37
5.2 Power Supply............................................................................................................................ 38
6General Purpose Input/Output (GPIO)............................................................................................ 40
6.1 Overview .................................................................................................................................. 40
6.2 Features.................................................................................................................................... 40
6.3 Function multiplexing............................................................................................................... 40
6.4 GPIO Special Function Registers .............................................................................................. 42
6.5 Port interrupt and wakeup....................................................................................................... 55
6.5.1 Wakeup registers.............................................................................................................. 55
6.6 Operation Guide....................................................................................................................... 57
7Timers.............................................................................................................................................. 58
7.1 Timer0 ...................................................................................................................................... 58
7.1.1 Timer0 Features................................................................................................................ 58
7.1.2 Timer0 Special Function Registers.................................................................................... 58
7.2 Timer1 ...................................................................................................................................... 59
7.2.1 Timer1 Features................................................................................................................ 60
7.2.2 Timer1 Special Function Registers.................................................................................... 60

IV Table of content
AX2228D Audio Player Microcontroller Version 1.0.0
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7.3 Timer2 ...................................................................................................................................... 62
7.3.1 Timer2 Features................................................................................................................ 62
7.3.2 Timer2 Special Function Registers.................................................................................... 62
7.4 Timer3 ...................................................................................................................................... 64
7.4.1 Timer3 Features................................................................................................................ 64
7.4.2 Timer3 Special Function Registers.................................................................................... 64
7.5 Watchdog Timer (WDT) ........................................................................................................... 66
7.5.1 Watchdog Wake up .......................................................................................................... 66
7.5.2 Watchdog SFR................................................................................................................... 66
7.6 Independent Power Real Time Clock Counter (IRTCC) ............................................................ 67
7.6.1 IRTCC Controller ............................................................................................................... 67
7.6.2 IRTCC Timer ...................................................................................................................... 67
7.6.3 Communication with IRTCC Timer.................................................................................... 68
7.6.4 IRTCC components description ........................................................................................ 70
7.6.5 IRTCC Special Function Registers...................................................................................... 75
7.6.6 IRTCC Operating Guide ..................................................................................................... 77
8Universal Asynchronous Receiver/Transmitter (UART) .................................................................. 79
8.1 UART0....................................................................................................................................... 79
8.1.1 Overview........................................................................................................................... 79
8.1.2 UART0 Special Function Registers .................................................................................... 79
8.2 UART1....................................................................................................................................... 81
8.2.1 Overview........................................................................................................................... 81
8.2.2 UART1 Special Function Registers .................................................................................... 81
8.2.3 UART1 Operation Guide ................................................................................................... 84
8.3 UART2....................................................................................................................................... 84
8.3.1 Overview........................................................................................................................... 84
8.3.2 UART2 Special Function Registers .................................................................................... 84
8.4 Operation Guide....................................................................................................................... 88
9SPI .................................................................................................................................................... 90
9.1 SPI0........................................................................................................................................... 90

Table of content V
AX2228D Audio Player Microcontroller Version 1.0.0
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9.1.1 SPI0 Special Function Registers ........................................................................................ 91
9.1.2 SPI0 Operation Guide ....................................................................................................... 92
9.2 SPI1........................................................................................................................................... 93
9.2.1 SPI1 Special Function Registers ........................................................................................ 94
9.2.2 SPI1 Operation Guide ....................................................................................................... 96
10 External Memory Interface (EMI).................................................................................................... 97
10.1 EMI Control Registers............................................................................................................... 97
11 Audio Terminal (DAC).................................................................................................................... 101
11.1 Features.................................................................................................................................. 101
11.2 DAC Special Function Registers.............................................................................................. 101
11.2.1 DAC Register Mapping.................................................................................................... 101
11.2.2 Function of DAC Control Registers ................................................................................. 102
11.3 Operation Guide..................................................................................................................... 106
12 SARADC.......................................................................................................................................... 107
12.1 Features.................................................................................................................................. 107
12.2 ADC Pin Mapping.................................................................................................................... 107
12.3 SARADC Special Function Registers........................................................................................ 107
13 Integrated Interchip Sound (IIS) .................................................................................................... 110
13.1 Features.................................................................................................................................. 110
13.2 IIS Special Function Register .................................................................................................. 111
13.3 Operation Guide..................................................................................................................... 114
13.3.1 Master mode .................................................................................................................. 114
13.3.2 Slave mode 1 .................................................................................................................. 114
13.3.3 Slave mode 2 .................................................................................................................. 114
13.3.4 Slave mode 3 .................................................................................................................. 114
13.3.5 IIS Operation Flow .......................................................................................................... 115
14 LCD driver ...................................................................................................................................... 116
14.1 Features.................................................................................................................................. 116
14.2 LCD Function Control Registers.............................................................................................. 118
15 Characteristics ............................................................................................................................... 123

VI Table of content
AX2228D Audio Player Microcontroller Version 1.0.0
Copyright © 2015, www.appotech.com. All Rights Reserved.
15.1 LDO Parameters ..................................................................................................................... 123
15.2 PLL Parameters....................................................................................................................... 123
15.3 I/O Parameters....................................................................................................................... 123
15.4 OSC Parameters ..................................................................................................................... 124
15.5 Audio DAC Parameters........................................................................................................... 124
16 Package Dimensions...................................................................................................................... 125
16.1 AX2228D LQFP48.................................................................................................................... 125
Appendix I Revision History........................................................................................................................ i
Figure
Figure 1-1 AX2228D system architecture............................................................................................................2
Figure 2-1 shows the pin assignments of LQFP48 package. ..............................................................................3
Figure 2-2 Pin assignment for LQFP48...............................................................................................................3
Figure 3-1 Program Memory Organization ........................................................................................................11
Figure 3-2 External Data Memory Mapping.......................................................................................................12
Figure 3-3 Internal data memory mapping.........................................................................................................13
Figure 3-4 Lowest 32 bytes in Internal data memory Lower 128.......................................................................13
Figure 4-1 Power on reset.................................................................................................................................23
Figure 4-2 Reset Sources..................................................................................................................................24
Figure 4-3 Source of XCK12V...........................................................................................................................30
Figure 5-1 Frequency compensation through external component....................................................................38
Figure 7-1 Timer1 Block Diagram......................................................................................................................60
Figure 9-1 SPI timing.........................................................................................................................................90
Figure 10-1 EMI timing......................................................................................................................................97
Figure 22-1 Timing of IIS in different mode......................................................................................................111
Figure 16-1 AX2228D LQFP48 package dimensions......................................................................................125
Table
Table 2-1 LQFP48 pin description .......................................................................................................................3
Table 3-1 AXC51-CORE Instruction Set Summary..............................................................................................8
Table 3-2 Interrupt Summary.............................................................................................................................13

Table of content VII
AX2228D Audio Player Microcontroller Version 1.0.0
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Table 4-1 LVD level setting................................................................................................................................24
Table 6-1 Pad types...........................................................................................................................................40
Table 6-2 Ports multiplexed mapping.................................................................................................................41
Table 7-1 IRTCC components communication commands................................................................................68
Table 17-1 DAC registers address mapping....................................................................................................101
Table 19-1 pin used.........................................................................................................................................107
Table 22-1 IIS pin mapping..............................................................................................................................110
Table 23-1 LCD PAD groups............................................................................................................................116
Table 23-2 Support panel in auto display mode...............................................................................................116
Table 15-1 LDO Parameters............................................................................................................................123
Table 15-2 PLL Parameters.............................................................................................................................123
Table 15-3 I/O Parameters ..............................................................................................................................123
Table 15-4 OSC Parameters............................................................................................................................124
Table 15-5 Audio DAC Parameters..................................................................................................................124
Register
Register 3-1 DPCON –Data Pointer Configure Register ..................................................................................15
Register 3-2 DPL0 –Data Pointer Low Byte .....................................................................................................16
Register 3-3 DPL1 –Data Pointer Low Byte .....................................................................................................16
Register 3-4 DPH0 –Data Pointer High Byte....................................................................................................16
Register 3-5 DPH1 –Data Pointer High Byte....................................................................................................16
Register 3-6 SP –Stack Pointer Low Byte ........................................................................................................17
Register 3-7 SPH –Stack Pointer High Byte.....................................................................................................17
Register 3-8 PSW –Processor Status Word.....................................................................................................17
Register 3-9 SPMODE –Special mode.............................................................................................................18
Register 3-10 IE0 –Interrupt Enable 0 ..............................................................................................................18
Register 3-11 IE1 –Interrupt Enable 1 ..............................................................................................................19
Register 3-12 IPH0 –Interrupt Priority high 0....................................................................................................19
Register 3-13 IP0 –Interrupt Priority 0 ..............................................................................................................20
Register 3-14 IPH1 –Interrupt Priority high 1....................................................................................................21
Register 3-15 IP1 –Interrupt Priority 1 ..............................................................................................................21
Register 4-1 LVDCON–LVD control..................................................................................................................25
Register 4-2 PCON0 –Power control 0.............................................................................................................26
Register 4-3 PCON1 –Power control 1.............................................................................................................27

VIII Table of content
AX2228D Audio Player Microcontroller Version 1.0.0
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Register 4-4 PCON2 –Power control 2.............................................................................................................28
Register 4-5 PCON3 –Power control 3.............................................................................................................28
Register 4-6 CLKCON –Clock control ..............................................................................................................29
Register 4-7 CLKCON1 –Clock control 1 .........................................................................................................30
Register 4-8 CLKCON2 –Clock control 2 .........................................................................................................31
Register 4-8 CLKCON3–Clock control 3 ..........................................................................................................32
Register 4-9 PLLCON –PLL Configuration.......................................................................................................32
Register 4-10 PLLCON2 –PLL Configuration2.................................................................................................33
Register 4-11 PLLINTH –PLL integer high........................................................................................................33
Register 4-12 PLLINTL –PLL integer low..........................................................................................................34
Register 4-13 PLLFRACH –PLL fraction high...................................................................................................34
Register 4-14 PLLFRACL –PLL fraction low.....................................................................................................34
Register 5-1 PWRCON1 –Power control 1.......................................................................................................38
Register 5-2 PWRCON2 –Power control 2.......................................................................................................39
Register 6-1 P0DIR-P0 direction Register.........................................................................................................42
Register 6-2 P1DIR-P1 direction Register.........................................................................................................42
Register 6-3 P2DIR-P2 direction Register.........................................................................................................42
Register 6-4 P3DIR-P3 direction Register.........................................................................................................42
Register 6-4 P4DIR-P4 direction Register.........................................................................................................43
Register 6-1 SRCCON-Slew Rate control Register...........................................................................................43
Register 6-5 P0 –P0 data register ....................................................................................................................43
Register 6-6 P1 –P1 data register ....................................................................................................................44
Register 6-7 P2 –P2 data register ....................................................................................................................44
Register 6-8 P3 –P3 data register ....................................................................................................................44
Register 6-8 P4 –P4 data register ....................................................................................................................44
Register 6-9 P0PU0 –P0 pull-up resistor control..............................................................................................44
Register 6-10 P1PU0 –P1 pull-up resistor control............................................................................................45
Register 6-11 P2PU0 –P2 pull-up resistor control low byte ..............................................................................45
Register 6-12 P2PU1 –P2 pull-up resistor control high byte.............................................................................45
Register 6-13 P3PU0 –P3 pull-up resistor control............................................................................................45
Register 6-9 P4PU0 –P4 pull-up resistor control..............................................................................................46
Register 6-10 PU200–pull-up 200Ωresistor control..........................................................................................46
Register 6-14 P0PD0 –P0 pull-down resistor control........................................................................................47
Register 6-15 P1PD0 –P1 10KΩ pull-down resistor control..............................................................................47
Register 6-16 P2PD0 –P2 3.3KΩpull-down resistor control.............................................................................47

Table of content IX
AX2228D Audio Player Microcontroller Version 1.0.0
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Register 6-17 P2PD1 –P2 0.5KΩpull-down resistor control.............................................................................47
Register 6-18 P3PD0 –P3 10KΩpull-down resistor control..............................................................................48
Register 6-19 P3PUD1 –P3 10KΩpull-down resistor control...........................................................................48
Register 6-14 P4PD0 –P4 pull-down resistor control........................................................................................48
Register 6-20 PIE0 –Port digital input enable control.......................................................................................49
Register 6-21 PIE1 –Port digital input enable control1.....................................................................................49
Register 6-21 PIE2 –Port digital input enable control2.....................................................................................50
Register 6-22 P0DRV0 –Port 0 Driving control.................................................................................................50
Register 6-23 P1DRV0 –Port 1 Driving control 0..............................................................................................51
Register 6-24 P1DRV1 –Port 1 Driving control 1..............................................................................................51
Register 6-25 P2DRV0 –Port 2 Driving control.................................................................................................52
Register 6-26 P3DRV0 –Port 3 Driving control.................................................................................................53
Register 6-27 P3DRV1 –Port 3 Driving control.................................................................................................54
Register 6-28 PMUXCON0 –Port Function MUX control 0...............................................................................54
Register 6-29 PWKEN –Port wakeup enable ...................................................................................................55
Register 6-30 PWKEDGE –Port wakeup Event select .....................................................................................56
Register 7-1 TMR0CON –Timer0 control..........................................................................................................58
Register 7-2 TMR0CNT –Timer0 Counter ........................................................................................................59
Register 7-3 TMR0PR –Timer0 Period.............................................................................................................59
Register 7-4 TMR0PWM –Timer0 PWM duty...................................................................................................59
Register 7-5 TMR1CON0 –Timer1 control 0.....................................................................................................60
Register 7-6 TMR1CON1 –Timer1 control 1.....................................................................................................61
Register 7-7 TMR1CNTH/TMR1CNTL –Timer1 Counter..................................................................................62
Register 7-8 TMR1PRH/TMR1PRL –Timer1 Period.........................................................................................62
Register 7-9 TMR1PWMH/TMR1PWML –Timer1 PWM duty ...........................................................................62
Register 7-10 TMR2CON0 –Timer2 control 0...................................................................................................62
Register 7-11 TMR2CON1 –Timer2 control 1...................................................................................................63
Register 7-12 TMR2CNTH/TMR2CNTL –Timer2 Counter................................................................................64
Register 7-13 TMR2PRH/TMR2PRL –Timer2 Period.......................................................................................64
Register 7-14 TMR2PWMH/TMR2PWML –Timer2 PWM duty .........................................................................64
Register 7-15 TMR3CON –Timer3 control........................................................................................................64
Register 7-16 TMR3CNT –Timer3 Counter ......................................................................................................65
Register 7-17 TMR3PR –Timer3 Period...........................................................................................................65
Register 7-18 TMR3PWM –Timer3 PWM duty.................................................................................................66
Register 7-19 WDTCON –Watchdog control....................................................................................................66

XTable of content
AX2228D Audio Player Microcontroller Version 1.0.0
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Register 7-20 RTCON –RTCC control..............................................................................................................75
Register 7-21 RTCDAT –RTCC communication data.......................................................................................76
Register 7-22 SECCNT –IRTCC second counter.............................................................................................76
Register 7-23 RTCON1 –IRTCC control1.........................................................................................................76
Register 10-1 UARTCON –UART0 control.......................................................................................................79
Register 10-2 UARTSTA –UART0 status..........................................................................................................80
Register 10-3 UARTBAUDL –UART0 Baud Rate Low Byte .............................................................................80
Register 10-4 UARTBAUDH –UART0 Baud Rate High Byte............................................................................80
Register 10-5 UARTDATA –UART0 Data .........................................................................................................81
Register 10-6 UART1CON –UART1 control.....................................................................................................81
Register 10-7 UART1STA –UART1 status........................................................................................................82
Register 10-8 UARTDIV –UART1 baud rate high.............................................................................................82
Register 10-9 UART1BAUD –UART1 baud rate low ........................................................................................83
Register 10-10 UART1DATA –UART1 Data buffer...........................................................................................83
Register 10-11 UARTDMATXCNT –UART DMA Transmit counter....................................................................83
Register 10-12 UARTDMATXPTR–UART DMA Transmit Start Pointer byte .....................................................83
Register 10-13 UARTDMARXPTR–UART DMA receive Start Pointer byte.......................................................83
Register 8-14 UART2CON –UART2 control.....................................................................................................84
Register 8-15 UART2STA –UART2 status........................................................................................................85
Register 8-16 UART2DIV –UART2 divide register............................................................................................86
Register 8-17 UART2BAUD –UART2 Baud Rate register................................................................................86
Register 8-18 UART2DATA –UART2 Data .......................................................................................................86
Register 8-19 UART2DMATXCNT –UART2 DMA Transmit counter..................................................................86
Register 8-20 UART2DMATXPTR–UART2 DMATransmit Start Pointer byte.................................................87
Register 8-21 UART2DMARXPTR–UART2 DMA receive Start Pointer byte.....................................................87
Register 8-22 UART2MINUS–UART2 DMA receive data minus byte count by CPU.........................................87
Register 8-23 UART2POINTL–UART2 DMApoint by CPU read.......................................................................87
Register 8-24 UART2POINTH–UART2 DMApoint by CPU read high byte.......................................................87
Register 8-25 UART2LOOPCNT–UART2 DMAloop count...............................................................................87
Register 8-26 UART2CNTH–UART2 DMAreceive count high byte ..................................................................88
Register 8-27 UART2CNTL–UART2 DMA receive count low byte ....................................................................88
Register 14-1 SPI0CON –SPI0 control.............................................................................................................91
Register 14-2 SPI0BAUD –SPI0 Baud Rate.....................................................................................................91
Register 14-3 SPI0BUF –SPI0 Data Buffer ......................................................................................................92
Register 14-4 SPI0DMACNT –SPI0 DMA counter............................................................................................92

Table of content XI
AX2228D Audio Player Microcontroller Version 1.0.0
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Register 14-5 SPI0DMAPTRH–SPI0 DMA Start Pointer high byte...................................................................92
Register 14-6 SPI0DMAPTRL–SPI0 DMA Start Pointer low byte.....................................................................92
Register 14-7 SPI1CON –SPI1 Configure Register..........................................................................................94
Register 14-8 SPI1CON1 –SPI1 Configure Register1......................................................................................94
Register 14-7 SPI1CON2 –SPI1 Configure Register 2.....................................................................................95
Register 14-9 SPI1BUF –SPI1 Data Buffer ......................................................................................................95
Register 14-10 SPI1DMASPH–SPI1 DMA Pointer...........................................................................................95
Register 14-11 SPI1DMASPL–SPI1 DMA Pointer............................................................................................95
Register 14-12 SPI1DMACNT –SPI1 DMA Counter.........................................................................................95
Register 15-1 EMICON0 –EMI control0............................................................................................................97
Register 15-2 EMICON1 –EMI control1............................................................................................................98
Register 15-2 EMICON2 –EMI control2............................................................................................................98
Register 15-2 EMICON3 –EMI control3............................................................................................................99
Register 15-2 EMICON4 –EMI contro4 ............................................................................................................99
Register 15-3 PWMBUF0/1/2/3/4/5/6/7 –PWMbuffer0/1/2/3/4/5/6/7................................................................100
Register 15-3 EMIBUF –EMI output buffer.....................................................................................................100
Register 17-1 ATADR - audio terminal address ...............................................................................................101
Register 17-2 ATDAT - audio terminal data .....................................................................................................101
Register 17-3 DACCFG - DAC configuration register......................................................................................102
Register 17-4 DACSM - DAC soft mute configuration register........................................................................103
Register 17-5 DACSPR - DAC sample rate register........................................................................................103
Register 17-6 DACVOLL - DAC volume setting low byte register....................................................................103
Register 17-7 DACVOLH–DAC volume setting high byte register..................................................................104
Register 17-8 DACVCON–DAC volume control register ................................................................................104
Register 17-9 TRIMCON1 - DAC trim control register1...................................................................................104
Register 17-10 TRIMCON2 - DAC trim control register2.................................................................................105
Register 17-11 TRREGLL - DAC left channel trim data reg law byte...............................................................105
Register 17-12 TRREGLH - DAC left channel trim data reg high byte ............................................................106
Register 17-13 TRREGRL- DAC right channel trim data reg law byte.............................................................106
Register 17-14 TRREGRH - DAC right channel trim data reg high byte..........................................................106
Register 19-1 ADCCON–SARADC control.....................................................................................................107
Register 19-2 ADCMODE–SARADC mode control ........................................................................................108
Register 19-3 ADCBAUD–SARADC baud rate control...................................................................................108
Register 19-4 ADCDATAL–SARADC Buffer low byte control .........................................................................109
Register 19-5 Register 21-4 ADCDATAH–SARADC Buffer high byte control.................................................109

XII Table of content
AX2228D Audio Player Microcontroller Version 1.0.0
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Register 22-1 IISCON0:...................................................................................................................................111
Register 22-2 IISCON1:...................................................................................................................................112
Register 22-3 IISBAUD:...................................................................................................................................112
Register 22-4 IISCKCON:................................................................................................................................112
Register 22-5 IISCH0: first group of IIS buffer.................................................................................................113
Register 22-6 IISCH1: second group of IIS buffer ...........................................................................................113
Register 22-7 IISADR:.....................................................................................................................................113
Register 22-8 IISCNT:......................................................................................................................................114
Register 23-1 LCD_CFG0 - LCD configuration control 0.................................................................................118
Register 23-2 LCD_CFG1 - LCD configuration control 1.................................................................................119
Register 23-3 LCD_MAP LCD mapping ..........................................................................................................119
Register 23-4 LCD_COM0L –Segment data low byte for LCDCOM0.............................................................120
Register 23-5 LCD_COM0H - Segment data high byte for LCDCOM0 ...........................................................120
Register 23-6 LCD_COM1L - Segment data low byte for LCDCOM1..............................................................120
Register 23-7 LCD_COM1H - Segment data high byte for LCDCOM1 ...........................................................121
Register 23-8 LCD_COM2L - Segment data low byte for LCDCOM2..............................................................121
Register 23-9 LCD_COM2H - Segment data high byte for LCDCOM2 ...........................................................121
Register 23-10 LCD_COM3L - Segment data low byte for LCDCOM3............................................................121
Register 23-11 LCD_COM3H - Segment data high byte for LCDCOM3..........................................................121
Register 23-12 LCD_COM4L - Segment data low byte for LCDCOM4............................................................121
Register 23-13 LCD_COM4H - Segment data high byte for LCDCOM4 .........................................................121

1 Product Overview 1
AX2228D Audio Player Microcontroller Version 1.0.0
Copyright © 2015, www.appotech.com. All Rights Reserved.
1Product Overview
1.1 Outline
AX2228D is an MCS-51TM Compatible high performance mixed signal microcontroller. It integrates advanced digital
and analog peripherals to suit for audio record and playback applications.
1.2 Features
Compatible with MCS-51TM instruction set;
Maximum 48MHz operating frequency;
Supports MP3 decoder;
Supports WMA decoder;
Supports WAV decoder;
Supports MP3 encoder;
Supports SPDIF;
Keypad tone mixer;
Two multi-function 8-bit timers, support Capture and PWM mode;
Two multi-function 16-bit timers, support Capture and PWM mode;
Watchdog Timer with on-chip RC oscillator;
one full-duplex UART;
Two SPI;
Full-speed USB 2.0 Device/Host controller;
Independent powered RTCC;
48MHz PLL-based clock generator;
Nine Channels 10-bit SARADC;
Power on Reset.
Operating temperature: -25℃to +85℃;
Storage temperature: -65℃to +150℃.

2 1.3 System Architecture
AX2228D Audio Player Microcontroller Version 1.0.0
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1.3 System Architecture
AX2228D
CORE DMA arbiter
MP3 decoder
SDC
Huffman
EMI
DAC
USB
(Host/Device)
RTCC driver
WatchdogInternal RCPLL
Clock managment
External OSC
Timer0,1,2,3
UART0,1
ADC
IIS
LVD
MP3 encoder
SPI0,1
Port0,1,2,3
WMA decoder
Memory
Figure 1-1 AX2228D system architecture

2 Pin Definitions 3
AX2228D Audio Player Microcontroller Version 1.0.0
Copyright © 2015, www.appotech.com. All Rights Reserved.
2Pin Definitions
2.1 AX2228D
2.1.1 Packages
LQFP48
2.1.2 Pin Assignment
Figure 2-1 shows the pin assignments of LQFP48 package.
AX2228D
LQFP48
1
2
3
4
5
6
7
8
9
13 14
47
48
P35
P03
P27
10
11
12
P21
P20
P36
VDDLDO
VDDIO
VDDHP
VDDDAC
DACR
VCM
DACL
VSSDAC
15 16
17 18 19 20
21 22 23 24
P02
P01
P00
P14
P33
P04
P05
P06
P07
P16
P17
26
25
28
27
30
29
32
31
34
33
36
35
DVSS
VDDCORE
P37
P13
P12
P11
P10
VDDIRT
IRTOSCI
IRTOSCO
IRTCWKO
P15
45
46
43
44
41
42
39
40
37
38
USBDP
USBDM
P22
P23
P24
P25
P26
P34
P30 P31
P32
Figure 2-2 Pin assignment for LQFP48
2.1.3 Pin Descriptions
Table 2-1 shows the pin descriptions of LQFP48 package.
Table 2-1 LQFP48 pin description

4 2.1 AX2228D
AX2228D Audio Player Microcontroller Version 1.0.0
Copyright © 2015, www.appotech.com. All Rights Reserved.
Pin No.LQFP48
Name
Type
Function
1
P27
I/O
EMID7
SDDAT00
SPI0DODI0
SPI0DO0
GPIO
2
P21
I/O
EMID1
IISDI0
SDCLK0
GPIO
3
P20
I/O
EMID0
IISBCLK
SDCMD0
GPIO
4
P36
I/O
VPG33
AUXR1
GPIO
5
VDDLDO
PWP
LDO 5V Power
6
VDDIO
PWR
IO 3.3V Power
7
VDDHP
PWR
HeadPhone 3.3V Power
8
VDDDAC
PWR
DAC 3.3V Power
9
DACR
AO
DAC Right Channel
10
VCM
AO
DAC Bandgap voltage reference
11
DACL
AO
DAC Left Channel
12
VSSDAC
GND
DAC Ground
13
P03
AI
MICIN1
VCMBUF
AUXL2
14
P02
AI
MICIN0
AUXR2
15
P01
I/O
AUXR0
SDDAT2
UART0TX1
GPIO
16
P00
I/O
AUXL0
SPI0DI2
SDDAT1
UART0RX1
GPIO
17
P14
I/O
PWM3
CAP3
SDDAT3
SPI0DODI2

2 Pin Definitions 5
AX2228D Audio Player Microcontroller Version 1.0.0
Copyright © 2015, www.appotech.com. All Rights Reserved.
Pin No.LQFP48
Name
Type
Function
SPI0DO2
GPIO
18
P33
I/O
ADC0
PWRWKUP
LVDDET
CLKO
GPIO
19
P04
I/O
ADC2
INT0
SPI1DO1
SPI1DODI1
PWM1
SPI0DODI1
SPI0DO1
GPIO
20
P05
I/O
ADC3
INT1
SPI1CLK1
CAP0
SPI0CLK1
GPIO
21
P06
I/O
ADC1
SPI1DI1
TMR1
TMR0
SPI0DI1
GPIO
22
P07
I/O
INT3
CAP1
GPIO
23
P16
I/O
ADC6
PWM2
IISREFCLK
AMIN
CAP2
UART0TX0
GPIO
24
P17
I/O
TMR2
IISWS
GPIO
25
DVSS
GND
Digital Ground
26
VDDCORE
PWR
Digital 1.8V Power

6 2.1 AX2228D
AX2228D Audio Player Microcontroller Version 1.0.0
Copyright © 2015, www.appotech.com. All Rights Reserved.
Pin No.LQFP48
Name
Type
Function
27
P37
I/O
AUXL1
GPIO
28
P13
I/O
ADC5
GPIO
29
P12
I/O
GPIO
30
P11
I/O
GPIO
31
P10
I/O
EMIWR
GPIO
32
VDDIRT
PWR
IRT 5V Power
33
IRTOSCI
AI
IRTC Oscillator Input
34
IRTOSCO
AO
IRTC Oscillator Output
35
IRTWKO
I/O
IRTC Wake up
36
P15
I/O
TMR3
GPIO
37
P32
I/O
SPI1DO0
SPI1DODI0
SDDAT01
GPIO
38
P31
I/O
SPI1DI0
SDCMD1
GPIO
39
P30
I/O
ADC4
SPI1CLK0
SDCLK1
GPIO
40
P34
I/O
INT2
PWM0
SPI0CLK2
UART0RX0
GPIO
41
P26
I/O
EMID6
SPI0CLK0
GPIO
42
P25
I/O
EMID5
SPI0DO3
SPI0DI0
GPIO
43
P24
I/O
EMID4
IISDO1
GPIO
44
P23
I/O
EMID3
IISDI1

2 Pin Definitions 7
AX2228D Audio Player Microcontroller Version 1.0.0
Copyright © 2015, www.appotech.com. All Rights Reserved.
Pin No.LQFP48
Name
Type
Function
GPIO
45
P22
I/O
EMID2
IISDO0
GPIO
46
USBDM
I/O
USB Negative Input/output
47
USBDP
I/O
USB Positive Input/output
48
P35
I/O
UDSW
GPIO
I: input; O: output; PWR: power; GND: ground; AO: Analog Output; AI：Analog Input；NC: not connect

8 3.1 Architecture
AX2228D Audio Player Microcontroller Version 1.0.0
Copyright © 2015, www.appotech.com. All Rights Reserved.
3CPU Core Information
3.1 Architecture
The AXC51-CORE of AX2228D is fully compatible with the MCS-51TM instruction set.
The AXC51-CORE employs a pipelined architecture that greatly increases its instruction throughput over the
standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock
cycles to execute, and usually have a maximum system clock of 12MHz. By contrast, the AXC51-CORE executes
most of its instructions in 1 system clock cycle. With system clock running at 48 MHz, it has a peak throughput of 48
MIPS running in on-chip SRAM area.
3.2 Instruction Set
The instruction set of the AXC51-CORE is fully compatible with the standard MCS-51TM instruction set; standard
8051 development tools can be used to develop software for the AXC51-CORE. All instructions of AXC51-CORE
are the binary and functional equivalent of their MCS-51TM counterparts, including op-codes, addressing modes and
effect on PSW flags. However, instruction timing is different than that of the standard 8051. Table 3-1 shows
AXC51-CORE Instruction Set Summary
Table 3-1 AXC51-CORE Instruction Set Summary
Number of Bytes
Mnemonic
Operands
Clock Cycles (running in SRAM)
1
NOP
1
2
AJMP
code addr
3
3
LJMP
code addr
3
1
RR
A
1
1
INC
A
1
1
INC
data addr
1
1
INC
@Ri
1
1
INC
Rn
1
3
JBC
bit addr, code addr
1 or 3
2
ACALL
code addr
3
3
LCALL
code addr
3
1
RRC
A
1
1
DEC
A
1
2
DEC
data addr
1
1
DEC
@Ri
1
1
DEC
Rn
1
3
JB
bit addr, code addr
1 or 3
1
RET
4
1
RL
A
1
2
ADD
A, #data
1