NXP Semiconductors LPC43 Series User manual

UM10503
LPC43xx ARM Cortex-M4/M0 dual-core microcontroller
Rev. 1.3 — 6 July 2012 User manual
Document information
Info Content
Keywords LPC4350FET256; LPC4350FET180; LPC4350FBD208; LPC4330FET256;
LPC4330FET180; LPC4330FET100; LPC4330FBD144; LPC4320FET100;
LPC4320FBD144; LPC4310FET100; LPC4310FBD144; LPC4357FET256;
LPC4357FET180; LPC4357FBD208; LPC4353FET256; LPC4353FET180;
LPC4353FBD208; LPC43xx, LPC4350, LPC4330, LPC4320, LPC4310,
LPC4357, LPC4353, LPC4337, LPC4333, LPC43Sxx, ARM Cortex-M4, ARM
Cortex-M0, SPIFI, SCT, USB, Ethernet
Abstract LPC4300 user manual

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LPC43xx user manual
Revision history
Rev Date Description
1.3 20120706 LPC43xx user manual.
Modifications: •Description of USB CDC device class updated in Section 25.5.26 “USBD_API_INIT_PARAM”and
Section 25.5.27 “USBD_CDC_API”.
•Section 24.7.1 “Susp_CTRL module”added for USB1.
•Section 23.11 “USB power optimization”updated.
•Table 20 “Boot image header use”added.
•AES only available for LPC43Sxx parts.
•Bank, Row, Column addressing for SDRAM devices added in Table 373.
•Parts LPC4337 and LPC4333 added.
1.2 20120608 LPC43xx user manual.
Modifications: •Syncflash removed from Chapter 21.
•Parameter tbupdated in Section 5.3.6.
•Parameters for ISP/IAP command “Copy RAM to flash” updated (Table 1031 and Table 1044).
•Part IDs updated in Table 1036; also see Errata note ES_LPC43X0_A.
•Description of CTRL_DISABLE register updated (see Table 230).
•Table 215 “SGPIO multiplexer” corrected.
•Flash accelerator register waitstate values added (see Table 46 and Table 47).
•Programming procedure for the SDRAM mode register added in Section 21.8.5.
•Clock ramp-up procedures for core clock added in Section 11.2.1.
•Description of the event router updated (see Section 8.3).

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Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
NXP Semiconductors UM10503
LPC43xx user manual
1.1 20120510
Modifications: •Reset value of the ETB bit in the ETBCFG register changed to one (see Table 48).
•UART1 FIFOLVL register removed.
•Chapter 46 “LPC43xx flash programming/ISP and IAP” added.
•OTP memory bank 0 changed to reserved.
•Hardware IP checksum feature removed from ethernet block.
•USB frame length adjust register added (see Table 54 and Table 55; for parts with on-chip flash only).
•Flash accelerator control registers added (see Table 46 and Table 47; for parts with on-chip flash
only).
•Support for SAMPLE pin added to the CREG0 register (Table 42).
•Chapter 47 “LPC43xx EEPROM memory” added (for parts with on-chip flash only).
•SDRAM low-power mode removed in Chapter 21.
•Motor control PWM hardware noise filtering removed.
•Description of the QEI register VEL corrected.
•Chapter 41 “LPC43xx I2S interface” updated.
•Remove condition RTC_ALARM = LOW on reset for entering debug mode.
•Ethernet chapter updated: PPS and auxiliary timestamp features removed.
•Chapter 36 “LPC43xx Event monitor/recorder” added (for parts with on-chip flash only).
•Connection of USB0_VBUS/USB1_VBUS signals added (Section 23.5.1).
•Description of ADC GDR register updated (Section 44.6.2).
•Pin reset states updated in Table 128 and Table 129.
•SCT register map updated in Table 645.
•Changed maximum clock frequency for SWD and ETB access to 120 MHz in Chapter 48.
•Reduced and normal power modes removed in Chapter 10.
•AES encryption option added in Table 22 (parts LPC43Sxx only).
•SGPIO register names and descriptions updated.
•Update description of bit 0 in the USBSTS_D and bit 5:0 in ENDPTCOMPLETE registers of USB0/1.
•Update procedure Section 23.10.8.1.2 “Setup packet handling using the trip wire mechanism”.
•Polarity of bit OUTSEL in the SCT EVCTRL register swapped (see Table 670).
•Bit 9 (JTAG enable for the M0 co-processor) added to the CREG5 register (Table 44).
•Description of CCU Auto mode updated (see Section 12.5.3).
•LQFP100 package removed.
•Maximum power consumption in the USB Suspended state corrected according to USB 2.0 ECN
specification (see Section 23.11.2).
1 20111212 Preliminary LPC43xx user manual.
Revision history …continued
Rev Date Description

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1.1 Introduction
The LPC43xx are ARM Cortex-M4 based microcontrollers for embedded applications
which include an ARM Cortex-M0 coprocessor, up to 1 MB of flash, up to 264 kB of
SRAM, advanced configurable peripherals such as the State Configurable Timer (SCT)
and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,
Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals.
The LPC43xx operate at CPU frequencies of up to 204 MHz.
The ARM Cortex-M4 is a next generation 32-bit core that offers system enhancements
such as low power consumption, enhanced debug features, and a high level of support
block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a
Harvard architecture with separate local instruction and data buses as well as a third bus
for peripherals, and includes an internal prefetch unit that supports speculative branching.
The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD
instructions. A hardware floating-point processor is integrated in the core.
The ARM Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core which
is code- and tool-compatible with the Cortex-M4 core. The Cortex-M0 coprocessor,
designed as a replacement for existing 8/16-bit microcontrollers, offers up to 204 MHz
performance with a simple instruction set and reduced code size.
1.2 Features
•Cortex-M4 Processor core
–ARM Cortex-M4 processor, running at frequencies of up to 204 MHz.
–ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions.
–ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
–Hardware floating-point unit.
–Non-maskable Interrupt (NMI) input.
–JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four
watch points.
–Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
–System tick timer.
•Cortex-M0 Processor core
–ARM Cortex-M0 co-processor capable of off-loading the main ARM Cortex-M4
application processor.
–Running at frequencies of up to 204 MHz.
–JTAG, Serial Wire Debug, and built-in NVIC.
•On-chip memory (flashless parts)
–Up to 264 kB SRAM for code and data use.
UM10503
Chapter 1: Introductory information
Rev. 1.3 — 6 July 2012 User manual

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Chapter 1: Introductory information
–Multiple SRAM blocks with separate bus access. Two SRAM blocks can be
powered down individually.
–64 kB ROM containing boot code and on-chip software drivers.
–32 bit general-purpose One-Time Programmable (OTP) memory.
•On-chip memory (parts with on-chip flash)
–Up to 1 MB on-chip dual bank flash memory with flash accelerator.
–16 kB on-chip EEPROM data memory.
–136 kB SRAM for code and data use.
–Multiple SRAM blocks with separate bus access. Two SRAM blocks can be
powered down individually.
–64 kB ROM containing boot code and on-chip software drivers.
–128 bit general-purpose One-Time Programmable (OTP) memory.
•Configurable digital peripherals
–Serial GPIO (SGPIO) interface.
–State Configurable Timer (SCT) subsystem on AHB.
–Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and
outputs to event driven peripherals like the timers, SCT, and ADC0/1.
•Serial interfaces
–Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 60 MB
per second.
–10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high
throughput at low CPU load. Support for IEEE 1588 time stamping and advanced
time stamping (IEEE 1588-2008 v2).
–One High-speed USB 2.0 Host/Device/OTG interface with DMA support and
on-chip high-speed PHY.
–One High-speed USB 2.0 Host/Device interface with DMA support, on-chip
full-speed PHY and ULPI interface to external high-speed PHY.
–USB interface electrical test software included in ROM USB stack.
–One 550 UART with DMA support and full modem interface.
–Three 550 USARTs with DMA and synchronous mode support and a smart card
interface conforming to ISO7816 specification. One USART with IrDA interface.
–Two C_CAN 2.0B controllers with one channel each.
–Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA
support.
–One SPI controller.
–One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O
pins conforming to the full I2C-bus specification. Supports data rates of up to
1 Mbit/s.
–One standard I2C-bus interface with monitor mode and with standard I/O pins.
–Two I2S interfaces, each with DMA support and with one input and one output.

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Chapter 1: Introductory information
•Digital peripherals
–External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,
and SDRAM devices.
–LCD controller with DMA support and a programmable display resolution of up to
1024H 768V. Supports monochrome and color STN panels and TFT color
panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel
mapping.
–Secure Digital Input Output (SD/MMC) card interface.
–Eight-channel General-Purpose DMA (GPDMA) controller can access all
memories on the AHB and all DMA-capable AHB slaves.
–Up to 164 General-Purpose Input/Output (GPIO) pins with configurable
pull-up/pull-down resistors.
–GPIO registers are located on the AHB for fast access. GPIO ports have DMA
support.
–Up to eight GPIO pins can be selected from all GPIO pins as edge and level
sensitive interrupt sources.
–Two GPIO group interrupt modules enable an interrupt based on a programmable
pattern of input states of a group of GPIO pins.
–Four general-purpose timer/counters with capture and match capabilities.
–One motor control Pulse Width Modulator (PWM) for three-phase motor control.
–One Quadrature Encoder Interface (QEI).
–Repetitive Interrupt timer (RI timer).
–Windowed watchdog timer (WWDT).
–Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes
of battery powered backup registers.
–(Parts with on-chip flash only): Event recorder with three inputs to record event
identification and event time; can be battery powered.
–Alarm timer; can be battery powered.
•Analog peripherals
–One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
–Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.
Up to eight input channels per ADC.
•Security (LPC43Sxx only)
–AES decryption programmable through an on-chip API.
–Two 128-bit secure OTP memories for AES key storage and customer use.
–Random number generator (RNG) accessible through AES API.
–Unique ID for each device.
•Clock generation unit
–Crystal oscillator with an operating range of 1 MHz to 25 MHz.
–12 MHz Internal RC (IRC) oscillator trimmed to 1 % accuracy over temperature
and voltage.

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Chapter 1: Introductory information
–Ultra-low power Real-Time Clock (RTC) crystal oscillator.
–Three PLLs allow CPU operationup to the maximum CPU rate without the need for
a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the
third PLL can be used as audio PLL.
–Clock output.
•Power
–Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip DC-to-DC converter for the
core supply and the RTC power domain.
–RTC power domain can be powered separately by a 3 V battery supply.
–Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
–Processor wake-up from Sleep mode via wake-up interrupts from various
peripherals.
–Wake-up from Deep-sleep, Power-down, and Deep power-down modes via
external interrupts and interrupts generated by battery powered blocks in the RTC
power domain.
–Brownout detect with four separate thresholds for interrupt and forced reset.
–Power-On Reset (POR).
–Available as LBGA256, TFBGA180, and TFBGA100 packages and as LQFP208
and LQFP144 packages.
1.3 Ordering information (flashless parts LPC4350/30/20/10)
Table 1. Ordering information
Type number Package
Name Description Version
LPC4350FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC4350FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls SOT570-3
LPC4350FBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC4330FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC4330FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls SOT570-3
LPC4330FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC4330FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC4320FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC4320FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC4310FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC4310FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1

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Chapter 1: Introductory information
1.4 Ordering information (parts with on-chip flash)
Table 2. Ordering options
Type number Total
SRAM LCD Ethernet USB0 (Host,
Device,
OTG)
USB1
(Host,
Device)/
ULPI
interface
ADC
channels PWM QEI GPIO Package
LPC4350FET256 264 kB yes yes yes yes/yes 8 yes yes 164 LBGA256
LPC4350FET180 264 kB yes yes yes yes/yes 8 yes yes 118 TFBGA180
LPC4350FBD208 264 kB yes yes yes yes/yes 8 yes yes 142 LQFP208
LPC4330FET256 264 kB no yes yes yes/yes 8 yes yes 164 LBGA256
LPC4330FET180 264 kB no yes yes yes/yes 8 yes yes 118 TFBGA180
LPC4330FET100 264 kB no yes yes yes/no 4 no no 49 TFBGA100
LPC4330FBD144 264 kB no yes yes yes/no 8 yes no 83 LQFP144
LPC4320FET100 200 kB no no yes no 4 no no 49 TFBGA100
LPC4320FBD144 200 kB no no yes no 8 yes no 83 LQFP144
LPC4310FET100 168 kB no no no no 4 no no 49 TFBGA100
LPC4310FBD144 168 kB no no no no 8 yes no 83 LQFP144
Table 3. Ordering information
Type number Package
Name Description Version
LPC4357FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC4357FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls SOT570-3
LPC4357FBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC4353FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC4353FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls SOT570-3
LPC4353FBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC4337FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC4337FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls SOT570-3
LPC4337FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC4337FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC4333FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC4333FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls SOT570-3
LPC4333FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC4333FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1

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Chapter 1: Introductory information
Table 4. Ordering options
Type number Flash Flash
bank A Flash bank B Total SRAM LCD Ethernet USB0 (Host,
Device,
OTG)
USB1
(Host,
Device)/
ULPI
interface
ADC
channels GPIO
LPC4357FET256 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes 8 164
LPC4357FET180 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes 8 118
LPC4357FBD208 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes 8 142
LPC4353FET256 512 kB 256 kB 256 kB 136 kB yes yes yes yes/yes 8 164
LPC4353FET180 512 kB 256 kB 256 kB 136 kB yes yes yes yes/yes 8 118
LPC4353FBD208 512 kB 256 kB 256 kB 136 kB yes yes yes yes/yes 8 142
LPC4337FET256 1 MB 512 kB 512 kB 136 kB no yes yes yes/yes 8 164
LPC4337FET180 1 MB 512 kB 512 kB 136 kB no yes yes yes/yes 8 118
LPC4337FET100 1 MB 512 kB 512 kB 136 kB no yes yes yes/yes 4 49
LPC4337FBD144 1 MB 512 kB 512 kB 136 kB no yes yes yes/yes 8 83
LPC4333FET256 512 kB 256 kB 256 kB 136 kB no yes yes yes/yes 8 164
LPC4333FET180 512 kB 256 kB 256 kB 136 kB no yes yes yes/yes 8 118
LPC4333FET100 512 kB 256 kB 256 kB 136 kB no yes yes yes/yes 4 49
LPC4333FBD144 512 kB 256 kB 256 kB 136 kB no yes yes yes/yes 8 83

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Chapter 1: Introductory information
1.5 Block diagram (flashless parts)
AES is supported for LPC43Sxx parts only.
Fig 1. LPC43xx Block diagram (flashless parts)
ARM
CORTEX-M4
TEST/DEBUG
INTERFACE
I-code bus D-code bus system bus
GPDMA LCD(1) SD/
MMC
ETHERNET(1)
10/100
MAC
IEEE 1588
HIGH-SPEED
USB0(1)
HOST/
DEVICE/OTG
HIGH-SPEED
USB1(1)
HOST/DEVICE
EMC
HIGH-SPEED PHY
32 kB AHB SRAM
16 +16 kB AHB SRAM
SPIFI
AES
HS GPIO
SPI
SGPIO
SCT
64 kB ROM
I2C0
I2S0
I2S1
C_CAN1
MOTOR
CONTROL
PWM(1)
TIMER3
TIMER2
USART2
USART3
SSP1
RI TIMER
QEI(1)
GIMA
BRIDGE 0 BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE
AHB MULTILAYER MATRIX
LPC4350/30/20/10
128 kB LOCAL SRAM
72 kB LOCAL SRAM
10-bit ADC0
10-bit ADC1
C_CAN0
I2C1
10-bit DAC
BRIDGE
RGU
CCU2
CGU
CCU1
ALARM TIMER
CONFIGURATION
REGISTERS
OTP MEMORY
EVENT ROUTER
POWER MODE CONTROL
12 MHz IRC
RTC POWER DOMAIN
BACKUP REGISTERS
RTC OSC
RTC
002aaf772
slaves
slaves
masters
ARM
CORTEX-M0
TEST/DEBUG
INTERFACE
= connected to GPDMA
GPIO
INTERRUPTS
GPIO GROUP0
INTERRUPT
GPIO GROUP1
INTERRUPT
WWDT
USART0
UART1
SSP0
TIMER0
TIMER1
SCU

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Chapter 1: Introductory information
1.6 Block diagram (parts with on-chip flash)
AES is supported for parts LPC43Sxx only. LCD on parts LPC4357/53 only.
Fig 2. LPC4357/53/37/33 block diagram (parts with on-chip flash)
ARM
CORTEX-M4
TEST/DEBUG
INTERFACE
I-code bus D-code bus system bus
GPDMA LCD(1) SD/
MMC
ETHERNET
10/100
MAC
IEEE 1588
HIGH-SPEED
USB0
HOST/
DEVICE/OTG
HIGH-SPEED
USB1
HOST/DEVICE
EMC
HIGH-SPEED PHY
SPIFI
HS GPIO
SPI
SGPIO
SCT
I2C0
I2S0
I2S1
C_CAN1
MOTOR
CONTROL
PWM
TIMER3
TIMER2
USART2
USART3
SSP1
RI TIMER
QEI
GIMA
BRIDGE 0 BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE
AHB MULTILAYER MATRIX
LPC4357/53/37/33
10-bit ADC0
10-bit ADC1
C_CAN0
I2C1
10-bit DAC
BRIDGE
RGU
CCU2
CGU
CCU1
ALARM TIMER
CONFIGURATION
REGISTERS
OTP MEMORY
EVENT ROUTER
POWER MODE CONTROL
12 MHz IRC
RTC POWER DOMAIN
BACKUP REGISTERS
RTC OSC
RTC
002aah234
slaves
slaves
masters
ARM
CORTEX-M0
TEST/DEBUG
INTERFACE
= connected to GPDMA
GPIO
INTERRUPTS
GPIO GROUP0
INTERRUPT
GPIO GROUP1
INTERRUPT
WWDT
USART0
UART1
SSP0
TIMER0
TIMER1
SCU
32 kB AHB SRAM
16 kB +
16 kB AHB SRAM
64 kB ROM
32 kB LOCAL SRAM
40 kB LOCAL SRAM
512/256 kB FLASH A
512/256 kB FLASH B
16 kB EEPROM

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2.1 How to read this chapter
The ARM Cortex-M0 co-processor is available on all LPC43xx parts.
2.2 Basic configuration
The ARM Cortex-M0 co-processor is configured as follows:
•See Table 5 for clocking and power control.
•The ARM Cortex-M0 is reset by the M0APP_RST (reset # 56) or by a general Reset.
•After power-up, the ARM Cortex-M0 reset must be released by clearing the
corresponding RESET_CTRL1 bit (see Table 115).
•The ARM Cortex-M0 interrupt is connected to interrupt slot # 1 in the ARM Cortex-M4
NVIC. See Table 26 for peripheral interrupts connected to the ARM Cortex-M0.
•To clear the ARM-Cortex-M0 interrupt, use the M0TXEVENT register (Table 53). See
Section 2.4.2.
2.3 Introduction
The LPC43xx is a dual-core microcontroller implementing an ARM Cortex-M4 and an
ARM Cortex-M0 core. The ARM Cortex-M4 is used as application processor. The second
core, the ARM Cortex-M0, can be used as co-processor to off-load the ARM Cortex-M4
and to perform serial I/O tasks. A communication protocol between the two processors is
needed. This chapter describes the Inter Process Communication (IPC) protocol for the
LPC43xx.
2.4 General description
On the LPC43xx, the ARM Cortex-M4 host CPU is used as the top-level system controller.
The LPC43xx also includes a second CPU, an ARM Cortex-M0. The ARM Cortex-M0
CPU is controlled by the host CPU. The communication between both CPUs makes use
of shared memory space and interrupts.
UM10503
Chapter 2: LPC43xx ARM Cortex-M0 co-processor and Inter-
Process Communication (IPC)
Rev. 1.3 — 6 July 2012 User manual
Table 5. ARM Cortex-M0 clocking and power control
Base clock Branch clock Operating frequency
ARM Cortex-M0 clock BASE_M4_CLK CLK_M4_M0 up to 204 MHz

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Chapter 2: LPC43xx ARM Cortex-M0 co-processor and Inter- Process
2.4.1 Hardware
Instead of using dedicated hardware, the IPC uses existing hardware components. The
buffers in shared memory can use any of the available SRAM. The buffer pointers are
maintained in software. The interrupts are captured in the processor’s NVIC and cleared
in the CREG block (see Table 51 and Table 53).
2.4.2 Interrupt handling
The ARM Cortex-M4 and ARM Cortex-M0 trigger interrupts to each other via CREG
registers M4TXEVENT and M0TXEVENT (see Table 51 and Table 53). The M4-to-M0 and
M0-to-M4 interrupts use the SendEvent instruction (SEV) to raise the signal TXEV. This
signal is captured by CREG. It should be cleared by the interrupt handler of the receiving
core.
2.5 IPC Protocol description
The IPC supports low-level interfaces, e.g. a register level interface, but also higher levels
like an API.
The ARM Cortex-M4 host CPU is always master. It initiates commands to the ARM
Cortex-M0 that mimic a hardware register level interface. The commands can be issued
either synchronously (wait for the reply message) or asynchronously (not wait for the reply
message) depending on the host application.
The ARM Cortex-M0 responds to commands given by the ARM Cortex-M4 by issuing
messages.
Since the ARM Cortex-M4 and ARM Cortex-M0 cannot at the same time write to the same
location, there is no need for a synchronization object (e.g. a semaphore) in this IPC.
Fig 3. Dual-core block diagram
= M0 subsystem
= M4 subsystem
= shared
RAM
HOST_MSG_BUFFER
Cortex M4
(Master)
Cortex M0
(Slave)
Read
Pointer
Write
Pointer
Write
Pointer
Read
Pointer
RAM
HOST_CMD_BUFFER
Interrupt
Interrupt
AHB

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Chapter 2: LPC43xx ARM Cortex-M0 co-processor and Inter- Process
The basic IPC features are:
•The ARM Cortex-M4 initializes the ARM Cortex-M0 system.
•The ARM Cortex-M4 communicates with the ARM Cortex-M0 system via a command
queue.
•The message queues are located in the ARM Cortex-M4 address space because the
ARM Cortex-M4 can be blocked from access to the ARM Cortex-M0 hardware
subsystem.
2.5.1 IPC queues
The ARM Cortex-M4 has an output command queue and an input message queue. A
queue is defined by four registers:
1. queue start address
2. queue end address
3. write pointer
4. read pointer
The ARM Cortex-M4 initializes these four registers. These registers reside in the same
shared SRAM as the queues to ensure that data and registers changes are synchronous.
Their location is static and known up front by the ARM Cortex-M0.
Messages are passed through queues using cyclic buffers. A queue is filled with
commands or messages from start to end address. When a buffer pointer points beyond
the end address it wraps around to the start address. When the read pointer is equal to
the write pointer, the queue can be either empty or completely full. To avoid this ambiguity
the queue shall never be filled completely. The minimum queue size is thus 3 words (the
longest command/message +1 word). An equal write and read pointer will indicate an
empty queue.
The command queue is filled by the ARM Cortex-M4 and emptied by the ARM Cortex-M0;
the write pointer is advanced by the ARM Cortex-M4 every time it adds a new command
to the queue. The read pointer is advanced by the ARM Cortex-M0 every time it removes
a command from the queue.
The message queue is filled by the ARM Cortex-M0 and emptied by the ARM Cortex-M4;
the write pointer is advanced by the ARM Cortex-M0 every time it adds a new message to
the queue. The read pointer is advanced by the ARM Cortex-M4 every time it removes a
message from the queue.
When a new command or message has been added to the queue and the write pointer
had been updated, an interrupt is raised to the other processor. The commands are
acknowledged by a return message (accept or fail).
The ARM Cortex-M4 and ARM Cortex-M0 only have one IPC write and one IPC read task.
If multiple instances exist then a local arbiter shall ensure that all write and read
operations are atomic; after data has been written (read) the write (read) pointer is
updated before another write (read) operation can start.

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Chapter 2: LPC43xx ARM Cortex-M0 co-processor and Inter- Process
It is the responsibility of the process writing to a queue making sure that the queue is not
filled completely; before loading a new item the process should confirm that the write
pointer will not be equal to, or overtake the read pointer and will leave at least one free
space. On the other hand the receiving side shall promptly process and remove items
from the queue.
No explicit error handling is performed. It is assumed that the ARM Cortex-M0 will always
respond to a ARM Cortex-M4 command.
2.5.2 Protocol
The ARM Cortex-M0 is used a co-processor to off-load the ARM Cortex-M4 and to
perform serial IO tasks. The ARM Cortex-M4 should be able to initialize tasks executed on
the ARM Cortex-M0. The ARM Cortex-M0 should be able to signal to the ARM Cortex-M4
when these tasks have completed or failed. This is done by issuing commands from ARM
Cortex-M4 to ARM Cortex-M0, where the ARM Cortex-M0 responds with messages. This
command and message interface resembles a hardware register level interface with
command and status registers.
The ARM Cortex-M4 issues 32-bit commands to the ARM Cortex-M0. Each command
starts with a 16-bit ID that defines which task is referred to. The LSBit indicates the
command type. A Write command is followed by a 32-bit operand. When a new command
is available, the ARM Cortex-M4 signals this to the ARM Cortex-M0 by raising an
interrupt.
The ARM Cortex-M0 return 32-bit messages to the ARM Cortex-M4. A messages starts
with a 16-bit ID that indicates which tasks the message refers to. The LSByte indicates the
message type. A Read response message is followed by the 32-bit read operand. When a
new message is available, the ARM Cortex-M0 signals this to the ARM Cortex-M4 by
raising an interrupt.
Small data transfers can be performed by the single 32-bit data read, CMD_RD_ID, and
write, CMD_WR_ID, commands. These commands use a 3-Byte addressing scheme to
support an argument space of 212 = 4096 32-bit words. Large data transfers can be more
efficiently handled using pointers.
Also higher level interfaces using API calls will typically use indirect, pointer based, reads
and writes.
When multiple tasks are running concurrently the ID is used to distinguish commands and
messages belonging to a certain task. A global command parser should be used to the
kick off commands to the tasks running on the ARM Cortex-M0.
The same holds true for the ARM Cortex-M4 side, a global message parser channels
back messages to the task dispatchers running on the ARM Cortex-M4 side.
Table 6. Command list
Command Bit mask Description
CMD_RD_ID 0xTTTT.PPP0 read 32 bit WORD with argument ID=0xPPP
from the task with ID = 0xTTTT
CMD_WR_ID 0xTTTT.PPP1, WORD write 32 bit WORD with argument ID=0xPPP to
the task with ID = 0xTTTT

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Chapter 2: LPC43xx ARM Cortex-M0 co-processor and Inter- Process
2.5.3 Example
Assume a certain task with ID 0x1234 should be executed by the ARM Cortex-M0. For
example, read data from a register level interface controlled by the ARM Cortex-M0. Text
in bold indicates a register.
The registers can either be located in the ARM Cortex-M0 SRAM, for more deterministic
access times, or in shared SRAM. If the ARM Cortex-M0 SRAM is used, then the register
data needs to be copied at initialization time. This copying takes time. The ARM
Cortex-M4 can poll a status register to determine when the transfer has finished.
The ARM Cortex-M4 initializes the command and message queues by loading the start-
and end addresses and write and read pointers.
Then the ARM Cortex-M4 loads the register values in a reserved area in common SRAM
memory. An alternative approach is that the ARM Cortex-M4 writes register per register,
however this requires more communication overhead than loading all data in one go.
Once all data has been set up, the ARM Cortex-M0 task can be started.
Table 7. Message list
Message Bit mask Description
MSG_SRV_ID 0xTTTT.SS00 ARM Cortex-M0 request servicing for the task
with ID = 0xTTTT. The service type is coded in
bytes SS. The meaning of SS is proprietary per
task. SS=0x00 means the task has finished.
MSG_RD_ID 0xTTTT.PPP1, VALUE ARM Cortex-M0 responds with VALUE to a read
of WORD with argument ID=0xPPP* from the
task with ID = 0xTTTT.
MSG_RD_STS_ID 0xTTTT.PPPR ARM Cortex-M0 response to a read of WORD
with argument ID=0xPPP* from the task with ID
= 0xTTTT fails. Cause of the failure is coded in
R; R = 2...4
2 = invalid argument
3 = reserved
4 = reserved
MSG_WR_STS_ID 0xTTTT.PPPW ARM Cortex-M0 response to a write with
argument ID=0xPPP* from the task with ID =
0xTTTT. Response is coded in W; W = 5...7
5 = write was successful
6 = write failed
7 = reserved
Table 8. Command responses
Command Possible responses Description
CMD_RD_ID MSG_RD_ID, VALUE read acknowledged
MSG_RD_STS_ID read failed
CMD_WR, WORD MSG_WR_STS_ID write is acknowledged as a success or failure

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Chapter 2: LPC43xx ARM Cortex-M0 co-processor and Inter- Process
Table 9. IPC example
Command Message Byte values Description
1 CMD_WR 0x1234<rst>1, pointer Command to initialise
the task, the pointer
informs the ARM
Cortex-M0 the location
of the register values.
The ARM Cortex-M0 processes the registers
2 MSG_WR_STS 0x1234<rst>2 ARM Cortex-M0 signals
write data has been
processed
3 MSR_SRV 0x1234<serve>00 ARM Cortex-M0
requests service, e.g.
because data has been
captured and is
available
4 CMD_RD 0x1234<status>1 ARM Cortex-M4 read
status
5 MSG_RD,VALUE 0x1234<status>1, VALUE ARM Cortex-M0
responds with status
Depending on the status the ARM Cortex-M4 may decide to read more data
6 CMD_RD 0x1234<result>,1 ARM Cortex-M4 reads
result
7 MSG_RD,VALUE 0x1234<result>1, pointer ARM Cortex-M0
responds with pointer to
results.
:: : : :
n CMD_WR 0x1234<stop>1, value Command to stop the
task
n+1 MSG_WR_STS 0x1234<stop>2 ARM Cortex-M0 signals
stop has been
processed

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3.1 How to read this chapter
The available peripherals and their memories vary for different parts.
•Ethernet: available only on LPC435x/3x.
•USB0: available only on LPC435x/3x/2x.
•USB1: available only on LPC435x/3x.
•SRAM: see Table 10.
•Flash: see Table 11.
The registers and memory regions corresponding to unavailable peripheral and memory
blocks are reserved.
3.2 Basic configuration
In the CREG block (see Table 49), select the interface to access the 16 kB block of RAM
located at address 0x2000 C000. This RAM memory block can be accessed either by the
Embedded Trace Buffer (ETB) or be used as normal SRAM on the AHB bus.
Remark: When the ETB is used , the 16 kB memory space at 0x2000 C000 must not be
used by any other process.
3.3 Memory configuration
3.3.1 On-chip static RAM
The LPC43xx support up to 264 kB SRAM on flashless parts or up to 136 kB on parts with
on-chip flash with separate bus master access for higher throughput and individual power
control for low power operation (see Figure 8).
When the Embedded Trace Buffer is used (see ETBCFG register, Table 49), the 16 kB
memory space at 0x2000 C000 must not be used by any other process.
UM10503
Chapter 3: LPC43xx Memory mapping
Rev. 1.3 — 6 July 2012 User manual
Table 10. LPC43xx SRAM configuration
Part Local SRAM LocalSRAM AHB SRAM AHBSRAM AHB
SRAM/
ETB
SRAM[1]
0x1000 0000 0x1008 0000 0x2000 0000 0x2000 8000 0x2000 C000
LPC4350 128 kB 72 kB 32 kB 16 kB 16 kB Figure 4
LPC4330 128 kB 72 kB 32 kB 16 kB 16 kB Figure 4
LPC4320 96 kB 40 kB 32 kB 16 kB 16 kB Figure 4

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Chapter 3: LPC43xx Memory mapping
[1] To configure SRAM memory use for AHB or ETB, see Table 49.
3.3.2 Bit banding
Bit-banding offers efficient bit accesses. Bits in the bit-band region (0x2000 0000 to
0x2010 0000 and 0x4000 0000 to 0x4010 0000) can be accessed in the so-called alias
region at 0x2200 0000 and 0x4200 0000. Reads return the respective bit from the
bit-band region. Writes perform an atomic read-modify-write on the respective bit of the
bit-band region. For details, see the ARM Cortex-M4 technical reference manual.
Remark: Bit banding can not be used with the MAC_RWAKE_FRFLT register (see
Section 26.6.10).
Remark: Although the EEPROM is mapped in a bit-banding capable region, attempts to
write access the EEPROM in the bit-banding aliased memory space will not result in a bit
write
3.3.3 On-chip flash
The available flash configuration for the LPC435x/3x/2x/1x is shown in Table 11. An
integrated flash accelerator maximizes performance for use with the two fast AHB buses.
The flash memory interface includes an intelligent buffering scheme. It can be beneficial
to locate code and static data over the two flash memories to enable parallel code and
data access or to avoid that interrupts corrupt buffer content. The buffers are aligned on
32-byte boundaries.
LPC4310 96 kB 40 kB 16 kB - 16 kB Figure 4
LPC4357 32 kB 40 kB 32 kB 16 kB 16 kB Figure 6
LPC4353 32 kB 40 kB 32 kB 16 kB 16 kB Figure 6
LPC4337 32 kB 40 kB 32 kB 16 kB 16 kB Figure 6
LPC4333 32 kB 40 kB 32 kB 16 kB 16 kB Figure 6
Table 10. LPC43xx SRAM configuration
Part Local SRAM LocalSRAM AHB SRAM AHBSRAM AHB
SRAM/
ETB
SRAM[1]
0x1000 0000 0x1008 0000 0x2000 0000 0x2000 8000 0x2000 C000
Table 11. LPC435x/3x/2x/1x Flash configuration
Part Flash bank A
256 kB Flash bank A 128 kB Flash bank A 128 kB Flash bank B 256 kB Flash bank B 128 kB Flash bank B 128 kB
0x1A00 0000 0x1A04 000 0x1A0 6000 0x1B00 0000 0x1B04 000 0x1B0 6000
LPC4357 yes yes yes yes yes yes

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Chapter 3: LPC43xx Memory mapping
3.3.4 On-chip EEPROM
The LPC435x/3x/2x/1x parts with flash also include a 16 kB EEPROM. The EEPROM is
divided into 128 pages. The last EEPROM page is protected.
3.3.5 Memory retention in the Power-down modes
In Deep-sleep mode, all SRAM content is retained. At wake-up the system can restart
immediately.
In Power-down mode, only the top 8 kB of the SRAM block starting at 0x1008 0000 is
retained - that is 8 kB of SRAM located at 0x1009 0000. All other SRAM content is lost.
Common practice is to store the stack and other variables that need to be retained in this
8 kB memory space as well as code to restart the rest of the system.
In Deep power-down mode, no SRAM content is retained. Variables that need to be
retained in deep power down can be stored in the 256-byte register file located in the RTC
domain at 0x4004 1000.
3.3.6 Memory Protection Unit (MPU)
The MPU is a integral part of the ARM Cortex-M4 for memory protection and supported by
all LPC43xx parts. The processor supports the standard ARMv7 Protected Memory
System Architecture model. The MPU provides full support for:
•protection regions
•overlapping protection regions, with ascending region priority (7 = highest priority, 0 =
lowest priority)
•access permissions
•exporting memory attributes to the system
MPU mismatches and permission violations invoke the programmable-priority
MemManage fault handler. See the ARMv7-M Architecture Reference Manual for more
information.
The access permission bits, TEX, C, B, AP, and XN, of the Region Access Control
Register control access to the corresponding memory region. If an access is made to an
area of memory without the required permissions, a permission fault is raised. For more
information, see the ARMv7-M Architecture Reference Manual.
The MPU is used to enforce privilege rules, to separate processes, and to enforce access
rules. For details on how to use the MPU and for the register description refer to the ARM
Cortex-M4 Technical Reference Manual.
LPC4353 yes no no yes no no
LPC4337 yes yes yes yes yes yes
LPC4333 yes no no yes no no
Table 11. LPC435x/3x/2x/1x Flash configuration
Part Flash bank A
256 kB Flash bank A 128 kB Flash bank A 128 kB Flash bank B 256 kB Flash bank B 128 kB Flash bank B 128 kB
0x1A00 0000 0x1A04 000 0x1A0 6000 0x1B00 0000 0x1B04 000 0x1B0 6000