Epson S1C31W74 User manual

Rev. 1.1
CMOS 32-BIT SINGLE CHIP MICROCONTROLLER
S1C31W74
Technical Manual

©
SEIKO EPSON CORPORATION 2021 , All rights reserved.
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(Rev. e1.0, 2021.9)

PREFACE
S1C31W74 TECHNICAL MANUAL Seiko Epson Corporation i
(Rev. 1.1)
Preface
This is a technical manual for designers and programmers who develop a product using the S1C31W74. This
document describes the functions of the IC, embedded peripheral circuit operations, and their control methods.
Notational conventions and symbols in this manual
Register address
Peripheral circuit chapters do not provide control register addresses. Refer to “Peripheral Circuit Area” in
the “Memory and Bus” chapter or “List of Peripheral Circuit Control Registers” in the Appendix.
Register and control bit names
In this manual, the register and control bit names are described as shown below to distinguish from signal
and pin names.
XXX register: Represents a register including its all bits.
XXX.YYY bit: Represents the one control bit YYY in the XXX register.
XXX.ZZZ[1:0] bits: Represents the two control bits ZZZ1 and ZZZ0 in the XXX register.
Register table contents and symbols
Initial: Value set at initialization
Reset: Initialization condition. The initialization condition depends on the reset group (H0, H1, or S0).
For more information on the reset groups, refer to “Initialization Conditions (Reset Groups)” in the
“Power Supply, Reset, and Clocks” chapter.
R/W: R = Read only bit
W = Write only bit
WP = Write only bit with a write protection using the SYSPROT.PROT[15:0] bits
R/W = Read/write bit
R/WP = Read/write bit with a write protection using the SYSPROT.PROT[15:0] bits
Control bit read/write values
This manual describes control bit values in a hexadecimal notation except for one-bit values (and except
when decimal or binary notation is required in terms of explanation). The values are described as shown
below according to the control bit width.
1 bit: 0 or 1
2 to 4 bits: 0x0 to 0xf
5 to 8 bits: 0x00 to 0xff
9 to 12 bits: 0x000 to 0xfff
13 to 16 bits: 0x0000 to 0xffff
Decimal: 0 to 9999...
Binary: 0b0000... to 0b1111...
Channel number
Multiple channels may be implemented in some peripheral circuits (e.g., 16-bit timer, etc.). The peripheral
circuit chapters use ‘n’ as the value that represents the channel number in the register and pin names regard-
less of the number of channel actually implemented. Normally, the descriptions are applied to all channels.
If there is a channel that has different functions from others, the channel number is specified clearly.
Example) T16_nCTL register of the 16-bit timer
If one channel is implemented (Ch.0 only): T16_nCTL = T16_0CTL only
If two channels are implemented (Ch.0 and Ch.1): T16_nCTL = T16_0CTL and T16_1CTL
For the number of channels implemented in the peripheral circuits of this IC, refer to “Features” in the
“Overview” chapter.
Low power mode
This manual describes the low power modes as HALT mode and SLEEP mode. These terms refer to sleep
mode and deep sleep mode in the Cortex®-M0+ processor, respectively.

CONTENTS
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– Contents –
Preface......................................................................................................................................i
Notational conventions and symbols in this manual ................................................................i
1 Overview........................................................................................................................1-1
1.1 Features .......................................................................................................................... 1-1
1.2 Block Diagram................................................................................................................. 1-3
1.3 Pins ................................................................................................................................. 1-4
1.3.1 Pin Configuration Diagram................................................................................ 1-4
1.3.2 Pad Configuration Diagram .............................................................................. 1-5
1.3.3 Pin Descriptions................................................................................................ 1-7
2 Power Supply, Reset, and Clocks ...............................................................................2-1
2.1 Power Generator (PWGA) ............................................................................................... 2-1
2.1.1 Overview ........................................................................................................... 2-1
2.1.2 Pins................................................................................................................... 2-1
2.1.3 VD1 Regulator Operation Mode......................................................................... 2-2
2.1.4 VD1 Regulator Voltage Mode............................................................................. 2-2
2.2 System Reset Controller (SRC)....................................................................................... 2-3
2.2.1 Overview ........................................................................................................... 2-3
2.2.2 Input Pin............................................................................................................ 2-3
2.2.3 Reset Sources .................................................................................................. 2-4
2.2.4 Initialization Conditions (Reset Groups)............................................................ 2-4
2.3 Clock Generator (CLG).................................................................................................... 2-5
2.3.1 Overview ........................................................................................................... 2-5
2.3.2 Input/Output Pins ............................................................................................. 2-6
2.3.3 Clock Sources .................................................................................................. 2-7
2.3.4 Operations ........................................................................................................ 2-8
2.4 Operating Mode ............................................................................................................. 2-13
2.4.1 Initial Boot Sequence....................................................................................... 2-13
2.4.2 Transition between Operating Modes.............................................................. 2-13
2.5 Interrupts........................................................................................................................ 2-15
2.6 Control Registers ........................................................................................................... 2-15
PWGA Control Register............................................................................................................ 2-15
CLG System Clock Control Register........................................................................................ 2-16
CLG Oscillation Control Register ............................................................................................. 2-17
CLG IOSC Control Register ..................................................................................................... 2-18
CLG OSC1 Control Register .................................................................................................... 2-18
CLG OSC3 Control Register .................................................................................................... 2-20
CLG Interrupt Flag Register ..................................................................................................... 2-20
CLG Interrupt Enable Register ................................................................................................. 2-21
CLG FOUT Control Register..................................................................................................... 2-22
3 CPU and Debugger ......................................................................................................3-1
3.1 Overview ......................................................................................................................... 3-1
3.2 CPU................................................................................................................................. 3-1
3.3 Debugger ........................................................................................................................ 3-1
3.3.1 List of Debugger Input/Output Pins.................................................................. 3-1
3.3.2 External Connection ......................................................................................... 3-1
3.4 Reference Documents .................................................................................................... 3-2
4 Memory and Bus ..........................................................................................................4-1
4.1 Overview ......................................................................................................................... 4-1

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4.2 Bus Access Cycle ........................................................................................................... 4-2
4.3 Flash Memory ................................................................................................................. 4-2
4.3.1 Flash Memory Pin ............................................................................................. 4-2
4.3.2 Flash Bus Access Cycle Setting....................................................................... 4-2
4.3.3 Flash Programming........................................................................................... 4-3
4.4 RAM ................................................................................................................................ 4-3
4.5 Display Data RAM ........................................................................................................... 4-3
4.6 Peripheral Circuit Control Registers................................................................................ 4-3
4.6.1 System-Protect Function.................................................................................. 4-9
4.7 Instruction Cache............................................................................................................ 4-9
4.8 Memory Mapped Access Area For External Flash Memory ........................................... 4-9
4.9 Control Registers ........................................................................................................... 4-10
System Protect Register .......................................................................................................... 4-10
CACHE Control Register .......................................................................................................... 4-10
FLASHC Flash Read Cycle Register ........................................................................................ 4-10
5 Interrupt.........................................................................................................................5-1
5.1 Overview ......................................................................................................................... 5-1
5.2 Vector Table .................................................................................................................... 5-1
5.2.1 Vector Table Offset Address (VTOR)................................................................. 5-3
5.2.2 Priority of Interrupts .......................................................................................... 5-3
5.3 Peripheral Circuit Interrupt Control ................................................................................. 5-3
5.4 NMI.................................................................................................................................. 5-4
6 DMA Controller (DMAC)...............................................................................................6-1
6.1 Overview ......................................................................................................................... 6-1
6.2 Operations ...................................................................................................................... 6-2
6.2.1 Initialization ....................................................................................................... 6-2
6.3 Priority............................................................................................................................. 6-2
6.4 Data Structure................................................................................................................. 6-2
6.4.1 Transfer Source End Pointer............................................................................. 6-3
6.4.2 Transfer Destination End Pointer ...................................................................... 6-3
6.4.3 Control Data...................................................................................................... 6-4
6.5 DMA Transfer Mode ........................................................................................................ 6-5
6.5.1 Basic Transfer ................................................................................................... 6-5
6.5.2 Auto-Request Transfer...................................................................................... 6-5
6.5.3 Ping-Pong Transfer ........................................................................................... 6-6
6.5.4 Memory Scatter-Gather Transfer ...................................................................... 6-7
6.5.5 Peripheral Scatter-Gather Transfer ................................................................... 6-8
6.6 DMA Transfer Cycle ........................................................................................................ 6-9
6.7 Interrupts......................................................................................................................... 6-9
6.8 Control Registers ........................................................................................................... 6-10
DMAC Status Register ............................................................................................................. 6-10
DMAC Configuration Register.................................................................................................. 6-10
DMAC Control Data Base Pointer Register.............................................................................. 6-11
DMAC Alternate Control Data Base Pointer Register .............................................................. 6-11
DMAC Software Request Register........................................................................................... 6-11
DMAC Request Mask Set Register .......................................................................................... 6-11
DMAC Request Mask Clear Register ....................................................................................... 6-12
DMAC Enable Set Register ...................................................................................................... 6-12
DMAC Enable Clear Register ................................................................................................... 6-12
DMAC Primary-Alternate Set Register ..................................................................................... 6-12
DMAC Primary-Alternate Clear Register .................................................................................. 6-13
DMAC Priority Set Register...................................................................................................... 6-13

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DMAC Priority Clear Register................................................................................................... 6-13
DMAC Error Interrupt Flag Register ......................................................................................... 6-13
DMAC Transfer Completion Interrupt Flag Register................................................................. 6-14
DMAC Transfer Completion Interrupt Enable Set Register ...................................................... 6-14
DMAC Transfer Completion Interrupt Enable Clear Register ................................................... 6-14
DMAC Error Interrupt Enable Set Register............................................................................... 6-14
DMAC Error Interrupt Enable Clear Register............................................................................ 6-15
7 I/O Ports (PPORT).........................................................................................................7-1
7.1 Overview ......................................................................................................................... 7-1
7.2 I/O Cell Structure and Functions..................................................................................... 7-2
7.2.1 Schmitt Input .................................................................................................... 7-2
7.2.2 Over Voltage Tolerant Fail-Safe Type I/O Cell................................................... 7-2
7.2.3 Pull-Up/Pull-Down ............................................................................................ 7-2
7.2.4 CMOS Output and High Impedance State ....................................................... 7-3
7.3 Clock Settings................................................................................................................. 7-3
7.3.1 PPORT Operating Clock................................................................................... 7-3
7.3.2 Clock Supply in SLEEP Mode .......................................................................... 7-3
7.3.3 Clock Supply During Debugging ...................................................................... 7-3
7.4 Operations ...................................................................................................................... 7-3
7.4.1 Initialization ....................................................................................................... 7-3
7.4.2 Port Input/Output Control................................................................................. 7-5
7.5 Interrupts......................................................................................................................... 7-6
7.6 Control Registers ............................................................................................................ 7-6
PxPort Data Register................................................................................................................ 7-6
PxPort Enable Register ............................................................................................................ 7-7
PxPort Pull-up/down Control Register..................................................................................... 7-7
PxPort Interrupt Flag Register.................................................................................................. 7-8
PxPort Interrupt Control Register............................................................................................. 7-8
PxPort Chattering Filter Enable Register.................................................................................. 7-8
PxPort Mode Select Register ................................................................................................... 7-8
PxPort Function Select Register .............................................................................................. 7-9
P Port Clock Control Register ................................................................................................... 7-9
P Port Interrupt Flag Group Register........................................................................................ 7-10
7.7 Control Register and Port Function Configuration of this IC ......................................... 7-11
7.7.1 P0 Port Group.................................................................................................. 7-11
7.7.2 P1 Port Group.................................................................................................. 7-12
7.7.3 P2 Port Group.................................................................................................. 7-13
7.7.4 P3 Port Group.................................................................................................. 7-14
7.7.5 P4 Port Group.................................................................................................. 7-15
7.7.6 P5 Port Group.................................................................................................. 7-16
7.7.7 P6 Port Group.................................................................................................. 7-17
7.7.8 P7 Port Group.................................................................................................. 7-18
7.7.9 P8 Port Group.................................................................................................. 7-19
7.7.10 P9 Port Group................................................................................................ 7-20
7.7.11 Pd Port Group................................................................................................ 7-21
7.7.12 Common Registers between Port Groups..................................................... 7-22
8 Universal Port Multiplexer (UPMUX)...........................................................................8-1
8.1 Overview ......................................................................................................................... 8-1
8.2 Peripheral Circuit I/O Function Assignment.................................................................... 8-1
8.3 Control Registers ............................................................................................................ 8-2
Pxy–xz Universal Port Multiplexer Setting Register................................................................... 8-2
9 Watchdog Timer (WDT2)..............................................................................................9-1
9.1 Overview ......................................................................................................................... 9-1

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9.2 Clock Settings................................................................................................................. 9-1
9.2.1 WDT2 Operating Clock..................................................................................... 9-1
9.2.2 Clock Supply in DEBUG Mode......................................................................... 9-1
9.3 Operations ...................................................................................................................... 9-2
9.3.1 WDT2 Control ................................................................................................... 9-2
9.3.2 Operations in HALT and SLEEP Modes............................................................ 9-3
9.4 Control Registers ............................................................................................................ 9-3
WDT2 Clock Control Register ................................................................................................... 9-3
WDT2 Control Register ............................................................................................................. 9-4
WDT2 Counter Compare Match Register ................................................................................. 9-5
10 Real-Time Clock (RTCA) ...........................................................................................10-1
10.1 Overview ...................................................................................................................... 10-1
10.2 Output Pin and External Connection ........................................................................... 10-1
10.2.1 Output Pin...................................................................................................... 10-1
10.3 Clock Settings.............................................................................................................. 10-2
10.3.1 RTCA Operating Clock .................................................................................. 10-2
10.3.2 Theoretical Regulation Function.................................................................... 10-2
10.4 Operations ................................................................................................................... 10-3
10.4.1 RTCA Control ................................................................................................ 10-3
10.4.2 Real-Time Clock Counter Operations............................................................ 10-4
10.4.3 Stopwatch Control......................................................................................... 10-4
10.4.4 Stopwatch Count-up Pattern ........................................................................ 10-4
10.5 Interrupts...................................................................................................................... 10-5
10.6 Control Registers ......................................................................................................... 10-6
RTCA Control Register (Low Byte) ........................................................................................... 10-6
RTCA Control Register (High Byte) .......................................................................................... 10-7
RTCA Second Alarm Register .................................................................................................. 10-7
RTCA Hour/Minute Alarm Register .......................................................................................... 10-8
RTCA Stopwatch Control Register........................................................................................... 10-8
RTCA Second/1Hz Register..................................................................................................... 10-9
RTCA Hour/Minute Register.................................................................................................... 10-10
RTCA Month/Day Register...................................................................................................... 10-11
RTCA Year/Week Register....................................................................................................... 10-11
RTCA Interrupt Flag Register .................................................................................................. 10-12
RTCA Interrupt Enable Register .............................................................................................. 10-13
11 Supply Voltage Detector (SVD2)...............................................................................11-1
11.1 Overview ...................................................................................................................... 11-1
11.2 Input Pin and External Connection .............................................................................. 11-2
11.2.1 Input Pin......................................................................................................... 11-2
11.2.2 External Connection ...................................................................................... 11-2
11.3 Clock Settings.............................................................................................................. 11-2
11.3.1 SVD2 Operating Clock................................................................................... 11-2
11.3.2 Clock Supply in SLEEP Mode ....................................................................... 11-2
11.3.3 Clock Supply During Debugging ................................................................... 11-3
11.4 Operations ................................................................................................................... 11-3
11.4.1 SVD2 Control ................................................................................................. 11-3
11.4.2 SVD2 Operations ........................................................................................... 11-4
11.5 SVD2 Interrupt and Reset ............................................................................................ 11-5
11.5.1 SVD2 Interrupt ............................................................................................... 11-5
11.5.2 SVD2 Reset.................................................................................................... 11-5
11.6 Control Registers ......................................................................................................... 11-6
SVD2 Ch.nClock Control Register .......................................................................................... 11-6

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SVD2 Ch.nControl Register..................................................................................................... 11-6
SVD2 Ch.nStatus and Interrupt Flag Register......................................................................... 11-8
SVD2 Ch.nInterrupt Enable Register....................................................................................... 11-8
12 16-bit Timers (T16).....................................................................................................12-1
12.1 Overview ...................................................................................................................... 12-1
12.2 Input Pin....................................................................................................................... 12-1
12.3 Clock Settings.............................................................................................................. 12-2
12.3.1 T16 Operating Clock...................................................................................... 12-2
12.3.2 Clock Supply in SLEEP Mode ....................................................................... 12-2
12.3.3 Clock Supply During Debugging ................................................................... 12-2
12.3.4 Event Counter Clock...................................................................................... 12-2
12.4 Operations ................................................................................................................... 12-2
12.4.1 Initialization .................................................................................................... 12-2
12.4.2 Counter Underflow ........................................................................................ 12-3
12.4.3 Operations in Repeat Mode........................................................................... 12-3
12.4.4 Operations in One-shot Mode ....................................................................... 12-3
12.4.5 Counter Value Read....................................................................................... 12-4
12.5 Interrupt........................................................................................................................ 12-4
12.6 Control Registers ......................................................................................................... 12-4
T16 Ch.nClock Control Register ............................................................................................. 12-4
T16 Ch.nMode Register .......................................................................................................... 12-5
T16 Ch.nControl Register........................................................................................................ 12-5
T16 Ch.nReload Data Register................................................................................................ 12-6
T16 Ch.nCounter Data Register .............................................................................................. 12-6
T16 Ch.nInterrupt Flag Register .............................................................................................. 12-6
T16 Ch.nInterrupt Enable Register.......................................................................................... 12-7
13 UART (UART2)............................................................................................................13-1
13.1 Overview ...................................................................................................................... 13-1
13.2 Input/Output Pins and External Connections .............................................................. 13-2
13.2.1 List of Input/Output Pins................................................................................ 13-2
13.2.2 External Connections .................................................................................... 13-2
13.2.3 Input Pin Pull-Up Function............................................................................. 13-2
13.2.4 Output Pin Open-Drain Output Function ...................................................... 13-2
13.2.5 Input/Output Signal Inverting Function.......................................................... 13-2
13.3 Clock Settings.............................................................................................................. 13-2
13.3.1 UART2 Operating Clock ................................................................................ 13-2
13.3.2 Clock Supply in SLEEP Mode ....................................................................... 13-3
13.3.3 Clock Supply During Debugging ................................................................... 13-3
13.3.4 Baud Rate Generator..................................................................................... 13-3
13.4 Data Format ................................................................................................................. 13-3
13.5 Operations ................................................................................................................... 13-4
13.5.1 Initialization .................................................................................................... 13-4
13.5.2 Data Transmission ......................................................................................... 13-5
13.5.3 Data Reception .............................................................................................. 13-6
13.5.4 IrDA Interface................................................................................................. 13-7
13.6 Receive Errors.............................................................................................................. 13-8
13.6.1 Framing Error ................................................................................................. 13-8
13.6.2 Parity Error..................................................................................................... 13-9
13.6.3 Overrun Error ................................................................................................. 13-9
13.7 Interrupts...................................................................................................................... 13-9
13.8 DMA Transfer Requests ............................................................................................... 13-9
13.9 Control Registers ........................................................................................................ 13-10

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UART2 Ch.nClock Control Register ....................................................................................... 13-10
UART2 Ch.nMode Register.................................................................................................... 13-11
UART2 Ch.nBaud–Rate Register ........................................................................................... 13-12
UART2 Ch.nControl Register ................................................................................................. 13-12
UART2 Ch.nTransmit Data Register ....................................................................................... 13-13
UART2 Ch.nReceive Data Register........................................................................................ 13-13
UART2 Ch.nStatus and Interrupt Flag Register ..................................................................... 13-13
UART2 Ch.nInterrupt Enable Register.................................................................................... 13-14
UART2 Ch.nTransmit Buffer Empty DMA Request Enable Register ...................................... 13-15
UART2 Ch.nReceive Buffer One Byte Full DMA Request Enable Register............................ 13-15
14 Synchronous Serial Interface (SPIA)........................................................................14-1
14.1 Overview ...................................................................................................................... 14-1
14.2 Input/Output Pins and External Connections .............................................................. 14-2
14.2.1 List of Input/Output Pins................................................................................ 14-2
14.2.2 External Connections .................................................................................... 14-2
14.2.3 Pin Functions in Master Mode and Slave Mode............................................ 14-3
14.2.4 Input Pin Pull-Up/Pull-Down Function .......................................................... 14-3
14.3 Clock Settings.............................................................................................................. 14-3
14.3.1 SPIA Operating Clock.................................................................................... 14-3
14.3.2 Clock Supply During Debugging ................................................................... 14-4
14.3.3 SPI Clock (SPICLKn) Phase and Polarity ...................................................... 14-4
14.4 Data Format ................................................................................................................. 14-5
14.5 Operations ................................................................................................................... 14-5
14.5.1 Initialization .................................................................................................... 14-5
14.5.2 Data Transmission in Master Mode ............................................................... 14-6
14.5.3 Data Reception in Master Mode.................................................................... 14-8
14.5.4 Terminating Data Transfer in Master Mode................................................... 14-10
14.5.5 Data Transfer in Slave Mode......................................................................... 14-10
14.5.6 Terminating Data Transfer in Slave Mode ..................................................... 14-11
14.6 Interrupts..................................................................................................................... 14-12
14.7 DMA Transfer Requests .............................................................................................. 14-13
14.8 Control Registers ........................................................................................................ 14-13
SPIA Ch.nMode Register ....................................................................................................... 14-13
SPIA Ch.nControl Register..................................................................................................... 14-14
SPIA Ch.nTransmit Data Register .......................................................................................... 14-15
SPIA Ch.nReceive Data Register ........................................................................................... 14-15
SPIA Ch.nInterrupt Flag Register ........................................................................................... 14-15
SPIA Ch.nInterrupt Enable Register ....................................................................................... 14-16
SPIA Ch.nTransmit Buffer Empty DMA Request Enable Register.......................................... 14-16
SPIA Ch.nReceive Buffer Full DMA Request Enable Register ............................................... 14-16
15 Quad Synchronous Serial Interface (QSPI) .............................................................15-1
15.1 Overview ...................................................................................................................... 15-1
15.2 Input/Output Pins and External Connections .............................................................. 15-2
15.2.1 List of Input/Output Pins................................................................................ 15-2
15.2.2 External Connections .................................................................................... 15-2
15.2.3 Pin Functions in Master Mode and Slave Mode............................................ 15-6
15.2.4 Input Pin Pull-Up/Pull-Down Function .......................................................... 15-6
15.3 Clock Settings.............................................................................................................. 15-6
15.3.1 QSPI Operating Clock ................................................................................... 15-6
15.3.2 Clock Supply During Debugging ................................................................... 15-7
15.3.3 QSPI Clock (QSPICLKn) Phase and Polarity ................................................. 15-7
15.4 Data Format ................................................................................................................. 15-8
15.5 Operations ................................................................................................................... 15-9

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15.5.1 Register Access Mode................................................................................... 15-9
15.5.2 Memory Mapped Access Mode ................................................................... 15-10
15.5.3 Initialization ................................................................................................... 15-11
15.5.4 Data Transmission in Master Mode .............................................................. 15-12
15.5.5 Data Reception in Register Access Master Mode........................................ 15-14
15.5.6 Data Reception in Memory Mapped Access Mode...................................... 15-17
15.5.7 Terminating Memory Mapped Access Operations ....................................... 15-25
15.5.8 Terminating Data Transfer in Master Mode................................................... 15-25
15.5.9 Data Transfer in Slave Mode......................................................................... 15-26
15.5.10 Terminating Data Transfer in Slave Mode ................................................... 15-27
15.6 Interrupts..................................................................................................................... 15-27
15.7 DMA Transfer Requests .............................................................................................. 15-28
15.8 Control Registers ........................................................................................................ 15-29
QSPI Ch.nMode Register ....................................................................................................... 15-29
QSPI Ch.nControl Register .................................................................................................... 15-31
QSPI Ch.nTransmit Data Register .......................................................................................... 15-32
QSPI Ch.nReceive Data Register........................................................................................... 15-32
QSPI Ch.nInterrupt Flag Register........................................................................................... 15-32
QSPI Ch.nInterrupt Enable Register....................................................................................... 15-33
QSPI Ch.nTransmit Buffer Empty DMA Request Enable Register ......................................... 15-33
QSPI Ch.nReceive Buffer Full DMA Request Enable Register............................................... 15-34
QSPI Ch.n FIFO Data Ready DMA Request Enable Register ................................................. 15-34
QSPI Ch.nMemory Mapped Access Configuration Register 1 .............................................. 15-34
QSPI Ch.nRemapping Start Address High Register .............................................................. 15-35
QSPI Ch.nMemory Mapped Access Configuration Register 2 .............................................. 15-35
QSPI Ch.nMode Byte Register............................................................................................... 15-37
16 I2C (I2C).......................................................................................................................16-1
16.1 Overview ...................................................................................................................... 16-1
16.2 Input/Output Pins and External Connections .............................................................. 16-2
16.2.1 List of Input/Output Pins................................................................................ 16-2
16.2.2 External Connections .................................................................................... 16-2
16.3 Clock Settings.............................................................................................................. 16-3
16.3.1 I2C Operating Clock ...................................................................................... 16-3
16.3.2 Clock Supply During Debugging ................................................................... 16-3
16.3.3 Baud Rate Generator..................................................................................... 16-3
16.4 Operations ................................................................................................................... 16-4
16.4.1 Initialization .................................................................................................... 16-4
16.4.2 Data Transmission in Master Mode ............................................................... 16-5
16.4.3 Data Reception in Master Mode.................................................................... 16-7
16.4.4 10-bit Addressing in Master Mode ............................................................... 16-10
16.4.5 Data Transmission in Slave Mode................................................................. 16-11
16.4.6 Data Reception in Slave Mode ..................................................................... 16-13
16.4.7 Slave Operations in 10-bit Address Mode.................................................... 16-15
16.4.8 Automatic Bus Clearing Operation ............................................................... 16-15
16.4.9 Error Detection.............................................................................................. 16-16
16.5 Interrupts..................................................................................................................... 16-17
16.6 DMA Transfer Requests .............................................................................................. 16-18
16.7 Control Registers ........................................................................................................ 16-18
I2C Ch.nClock Control Register............................................................................................. 16-18
I2C Ch.nMode Register.......................................................................................................... 16-19
I2C Ch.nBaud-Rate Register.................................................................................................. 16-19
I2C Ch.nOwn Address Register ............................................................................................. 16-20
I2C Ch.nControl Register ....................................................................................................... 16-20
I2C Ch.nTransmit Data Register............................................................................................. 16-21

CONTENTS
S1C31W74 TECHNICAL MANUAL Seiko Epson Corporation ix
(Rev. 1.1)
I2C Ch.nReceive Data Register.............................................................................................. 16-21
I2C Ch.nStatus and Interrupt Flag Register ........................................................................... 16-22
I2C Ch.nInterrupt Enable Register ......................................................................................... 16-23
I2C Ch.nTransmit Buffer Empty DMA Request Enable Register............................................ 16-24
I2C Ch.nReceive Buffer Full DMA Request Enable Register.................................................. 16-24
17 16-bit PWM Timers (T16B) ........................................................................................17-1
17.1 Overview ...................................................................................................................... 17-1
17.2 Input/Output Pins......................................................................................................... 17-2
17.3 Clock Settings.............................................................................................................. 17-3
17.3.1 T16B Operating Clock ................................................................................... 17-3
17.3.2 Clock Supply in SLEEP Mode ....................................................................... 17-3
17.3.3 Clock Supply During Debugging ................................................................... 17-3
17.3.4 Event Counter Clock...................................................................................... 17-3
17.4 Operations ................................................................................................................... 17-4
17.4.1 Initialization .................................................................................................... 17-4
17.4.2 Counter Block Operations ............................................................................. 17-5
17.4.3 Comparator/Capture Block Operations......................................................... 17-8
17.4.4 TOUT Output Control ................................................................................... 17-17
17.5 Interrupt....................................................................................................................... 17-23
17.6 DMA Transfer Requests .............................................................................................. 17-23
17.7 Control Registers ........................................................................................................ 17-23
T16B Ch.nClock Control Register.......................................................................................... 17-23
T16B Ch.nCounter Control Register ...................................................................................... 17-24
T16B Ch.nMax Counter Data Register................................................................................... 17-25
T16B Ch.nTimer Counter Data Register................................................................................. 17-25
T16B Ch.nCounter Status Register........................................................................................ 17-26
T16B Ch.nInterrupt Flag Register........................................................................................... 17-27
T16B Ch.nInterrupt Enable Register ...................................................................................... 17-28
T16B Ch.nComparator/Capture mControl Register.............................................................. 17-29
T16B Ch.nCompare/Capture mData Register....................................................................... 17-31
T16B Ch.nCounter Max/Zero DMA Request Enable Register ............................................... 17-32
T16B Ch.nCompare/Capture mDMA Request Enable Register............................................ 17-32
18 Sound Generator (SNDA) ..........................................................................................18-1
18.1 Overview ...................................................................................................................... 18-1
18.2 Output Pins and External Connections........................................................................ 18-2
18.2.1 List of Output Pins ......................................................................................... 18-2
18.2.2 Output Pin Drive Mode .................................................................................. 18-2
18.2.3 External Connections .................................................................................... 18-2
18.3 Clock Settings.............................................................................................................. 18-3
18.3.1 SNDA Operating Clock.................................................................................. 18-3
18.3.2 Clock Supply in SLEEP Mode ....................................................................... 18-3
18.3.3 Clock Supply in DEBUG Mode...................................................................... 18-3
18.4 Operations ................................................................................................................... 18-3
18.4.1 Initialization .................................................................................................... 18-3
18.4.2 Buzzer Output in Normal Buzzer Mode......................................................... 18-3
18.4.3 Buzzer Output in One-shot Buzzer Mode...................................................... 18-6
18.4.4 Output in Melody Mode................................................................................. 18-7
18.5 Interrupts...................................................................................................................... 18-9
18.6 DMA Transfer Requests .............................................................................................. 18-10
18.7 Control Registers ........................................................................................................ 18-10
SNDA Clock Control Register ................................................................................................. 18-10
SNDA Select Register ............................................................................................................. 18-11
SNDA Control Register............................................................................................................ 18-12

CONTENTS
xSeiko Epson Corporation S1C31W74 TECHNICAL MANUAL
(Rev. 1.1)
SNDA Data Register................................................................................................................ 18-12
SNDA Interrupt Flag Register.................................................................................................. 18-13
SNDA Interrupt Enable Register.............................................................................................. 18-13
SNDA Sound Buffer Empty DMA Request Enable Register ................................................... 18-14
19 IR Remote Controller (REMC2) ................................................................................19-1
19.1 Overview ...................................................................................................................... 19-1
19.2 Input/Output Pins and External Connections .............................................................. 19-1
19.2.1 Output Pin...................................................................................................... 19-1
19.2.2 External Connections .................................................................................... 19-2
19.3 Clock Settings.............................................................................................................. 19-2
19.3.1 REMC2 Operating Clock ............................................................................... 19-2
19.3.2 Clock Supply in SLEEP Mode ....................................................................... 19-2
19.3.3 Clock Supply During Debugging ................................................................... 19-2
19.4 Operations ................................................................................................................... 19-2
19.4.1 Initialization .................................................................................................... 19-2
19.4.2 Data Transmission Procedures...................................................................... 19-3
19.4.3 REMO Output Waveform ............................................................................... 19-3
19.4.4 Continuous Data Transmission and Compare Buffers................................... 19-5
19.5 Interrupts...................................................................................................................... 19-6
19.6 Application Example: Driving EL Lamp........................................................................ 19-7
19.7 Control Registers ......................................................................................................... 19-7
REMC2 Clock Control Register................................................................................................ 19-7
REMC2 Data Bit Counter Control Register .............................................................................. 19-8
REMC2 Data Bit Counter Register........................................................................................... 19-9
REMC2 Data Bit Active Pulse Length Register....................................................................... 19-10
REMC2 Data Bit Length Register............................................................................................ 19-10
REMC2 Status and Interrupt Flag Register............................................................................. 19-10
REMC2 Interrupt Enable Register ........................................................................................... 19-11
REMC2 Carrier Waveform Register......................................................................................... 19-11
REMC2 Carrier Modulation Control Register .......................................................................... 19-11
20 LCD Driver (LCD32B).................................................................................................20-1
20.1 Overview ...................................................................................................................... 20-1
20.2 Output Pins and External Connections........................................................................ 20-2
20.2.1 List of Output Pins ......................................................................................... 20-2
20.2.2 External Connections .................................................................................... 20-2
20.3 Clock Settings.............................................................................................................. 20-3
20.3.1 LCD32B Operating Clock .............................................................................. 20-3
20.3.2 Clock Supply in SLEEP Mode ....................................................................... 20-3
20.3.3 Clock Supply During Debugging ................................................................... 20-3
20.3.4 Frame Frequency........................................................................................... 20-3
20.4 LCD Power Supply....................................................................................................... 20-6
20.4.1 Internal Generation Mode .............................................................................. 20-6
20.4.2 External Voltage Application Mode................................................................ 20-6
20.4.3 LCD Voltage Regulator Settings .................................................................... 20-7
20.4.4 LCD Voltage Booster Setting......................................................................... 20-7
20.4.5 LCD Contrast Adjustment.............................................................................. 20-7
20.5 Operations ................................................................................................................... 20-7
20.5.1 Initialization .................................................................................................... 20-7
20.5.2 Display On/Off ............................................................................................... 20-8
20.5.3 Inverted Display ............................................................................................. 20-8
20.5.4 Drive Duty Switching ..................................................................................... 20-8
20.5.5 Drive Waveforms........................................................................................... 20-10

CONTENTS
S1C31W74 TECHNICAL MANUAL Seiko Epson Corporation xi
(Rev. 1.1)
20.5.6 Partial Common Output Drive....................................................................... 20-16
20.5.7 n-Segment-Line Inverse AC Drive ................................................................ 20-16
20.6 Display Data RAM ....................................................................................................... 20-17
20.6.1 Display Area Selection.................................................................................. 20-17
20.6.2 Segment Pin Assignment ............................................................................. 20-17
20.6.3 Common Pin Assignment ............................................................................. 20-17
20.7 Interrupt....................................................................................................................... 20-26
20.8 Control Registers ........................................................................................................ 20-26
LCD32B Clock Control Register.............................................................................................. 20-26
LCD32B Control Register........................................................................................................ 20-27
LCD32B Timing Control Register 1......................................................................................... 20-27
LCD32B Timing Control Register 2......................................................................................... 20-28
LCD32B Power Control Register............................................................................................. 20-28
LCD32B Display Control Register........................................................................................... 20-29
LCD32B COM Pin Control Registers 0 and 1 ......................................................................... 20-30
LCD32B Interrupt Flag Register .............................................................................................. 20-31
LCD32B Interrupt Enable Register.......................................................................................... 20-31
21 R/F Converter (RFC)..................................................................................................21-1
21.1 Overview ...................................................................................................................... 21-1
21.2 Input/Output Pins and External Connections .............................................................. 21-2
21.2.1 List of Input/Output Pins................................................................................ 21-2
21.2.2 External Connections .................................................................................... 21-2
21.3 Clock Settings.............................................................................................................. 21-3
21.3.1 RFC Operating Clock..................................................................................... 21-3
21.3.2 Clock Supply in SLEEP Mode ....................................................................... 21-3
21.3.3 Clock Supply in DEBUG Mode...................................................................... 21-3
21.4 Operations ................................................................................................................... 21-3
21.4.1 Initialization .................................................................................................... 21-3
21.4.2 Operating Modes........................................................................................... 21-4
21.4.3 RFC Counters ................................................................................................ 21-4
21.4.4 Converting Operations and Control Procedure ............................................. 21-5
21.4.5 CR Oscillation Frequency Monitoring Function............................................. 21-7
21.5 Interrupts...................................................................................................................... 21-7
21.6 Control Registers ......................................................................................................... 21-8
RFC Ch.nClock Control Register ............................................................................................ 21-8
RFC Ch.nControl Register....................................................................................................... 21-8
RFC Ch.nOscillation Trigger Register...................................................................................... 21-9
RFC Ch.nMeasurement Counter Low and High Registers .................................................... 21-10
RFC Ch.nTime Base Counter Low and High Registers ......................................................... 21-10
RFC Ch.nInterrupt Flag Register............................................................................................ 21-11
RFC Ch.nInterrupt Enable Register........................................................................................ 21-11
22 USB 2.0 FS Device Controller (USB, USBMISC) .....................................................22-1
22.1 Overview ...................................................................................................................... 22-1
22.2 Input/Output Pins and External Connections .............................................................. 22-2
22.2.1 List of Input/Output Pins................................................................................ 22-2
22.2.2 External Connections ................................................................................... 22-2
22.3 Clock Settings.............................................................................................................. 22-3
22.4 USB Power Supply ...................................................................................................... 22-4
22.5 Operations ................................................................................................................... 22-4
22.5.1 Initialization .................................................................................................... 22-4
22.5.2 Settings when VBUS is Disconnected............................................................. 22-6
22.5.3 Transaction Control........................................................................................ 22-7

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xii Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL
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22.5.4 Control Transfer ............................................................................................. 22-9
22.5.5 Bulk Transfer/Interrupt Transfer .................................................................... 22-11
22.5.6 Data Flow Control......................................................................................... 22-12
22.5.7 Auto-Negotiation Function ........................................................................... 22-13
22.5.8 Description by Negotiation Function ............................................................ 22-15
22.5.9 FIFO Management ........................................................................................ 22-18
22.5.10 Snooze........................................................................................................ 22-20
22.6 Interrupts..................................................................................................................... 22-21
22.7 DMA Transfer Requests .............................................................................................. 22-22
22.8 Control Registers ........................................................................................................ 22-22
USB Control Register.............................................................................................................. 22-22
USB Transceiver Control Register........................................................................................... 22-24
USB Status Register ............................................................................................................... 22-24
USB Endpoint Control Register............................................................................................... 22-25
USB General-Purpose Endpoint FIFO Clear Register............................................................. 22-25
USB FIFO Read Cycle Setup Register.................................................................................... 22-26
USB Revision Number Register .............................................................................................. 22-26
USB EP0 Setup Data Registers 0–7........................................................................................ 22-26
USB Address Register............................................................................................................. 22-27
USB EP0 Configuration Register............................................................................................. 22-27
USB EP0 Maximum Packet Size Register .............................................................................. 22-27
USB EP0 IN Transaction Control Register .............................................................................. 22-28
USB EP0 OUT Transaction Control Register........................................................................... 22-29
USB EPmControl Registers.................................................................................................... 22-30
USB EPmConfiguration Registers.......................................................................................... 22-31
USB EPmMaximum Packet Size Registers............................................................................ 22-32
USB Read FIFO Select Register ............................................................................................. 22-32
USB Write FIFO Select Register.............................................................................................. 22-33
USB FIFO Read/Write Enable Register................................................................................... 22-33
USB Remaining FIFO Data Count Register............................................................................. 22-34
USB Remaining FIFO Space Count Register.......................................................................... 22-34
USB Debug RAM Address Register........................................................................................ 22-34
USB Main Interrupt Flag Register ........................................................................................... 22-34
USB SIE Interrupt Flag Register.............................................................................................. 22-35
USB General-Purpose Endpoint Interrupt Flag Register ........................................................ 22-36
USB EP0 Interrupt Flag Register............................................................................................. 22-36
USB EPmInterrupt Flag Registers.......................................................................................... 22-37
USB Main Interrupt Enable Register ....................................................................................... 22-38
USB SIE Interrupt Enable Register.......................................................................................... 22-38
USB General-Purpose Endpoint Interrupt Enable Register .................................................... 22-39
USB EP0 Interrupt Enable Register......................................................................................... 22-39
USB EPmInterrupt Enable Registers...................................................................................... 22-40
USB FIFO Data Register ......................................................................................................... 22-41
USB Debug RAM Data Register.............................................................................................. 22-41
USB Misc Control Register ..................................................................................................... 22-41
USB FIFO Write DMA Request Enable Register ..................................................................... 22-43
USB FIFO Read DMA Request Enable Register ..................................................................... 22-43
23 Electrical Characteristics .........................................................................................23-1
23.1 Absolute Maximum Ratings ......................................................................................... 23-1
23.2 Recommended Operating Conditions ......................................................................... 23-1
23.3 Current Consumption................................................................................................... 23-2
23.4 System Reset Controller (SRC) Characteristics........................................................... 23-4
23.5 Clock Generator (CLG) Characteristics........................................................................ 23-5
23.6 Flash Memory Characteristics ..................................................................................... 23-6
23.7 Input/Output Port (PPORT) Characteristics ................................................................. 23-7

CONTENTS
S1C31W74 TECHNICAL MANUAL Seiko Epson Corporation xiii
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23.8 Supply Voltage Detector (SVD2) Characteristics ......................................................... 23-7
23.9 UART (UART2) Characteristics .................................................................................... 23-9
23.10 Synchronous Serial Interface (SPIA) Characteristics ................................................. 23-9
23.11 Quad Synchronous Serial Interface (QSPI) Characteristics...................................... 23-11
23.12 I2C (I2C) Characteristics............................................................................................ 23-12
23.13 LCD Driver (LCD32B) Characteristics ....................................................................... 23-12
23.14 R/F Converter (RFC) Characteristics......................................................................... 23-15
23.15 USB 2.0 FS Device Controller (USB) Characteristics ............................................... 23-16
24 Basic External Connection Diagram .......................................................................24-1
25 Package......................................................................................................................25-1
Appendix A List of Peripheral Circuit Control Registers ......................................... AP-A-1
0x4000 0000 System Register (SYS) ............................................. AP-A-1
0x4000 0020 Power Generator (PWGA) ........................................ AP-A-1
0x4000 0040–0x4000 0050 Clock Generator (CLG)............................................. AP-A-1
0x4000 0080 Cache Controller (CACHE)....................................... AP-A-2
0x4000 00a0–0x4000 00a4 Watchdog Timer (WDT2).......................................... AP-A-2
0x4000 00c0–0x4000 00d2 Real-time Clock (RTCA) ........................................... AP-A-3
0x4000 0100–0x4000 0106 Supply Voltage Detector (SVD2) Ch.0...................... AP-A-4
0x4000 0160–0x4000 016c 16-bit Timer (T16) Ch.0 ............................................ AP-A-5
0x4000 01b0 Flash Controller (FLASHC) ....................................... AP-A-5
0x4000 0200–0x4000 02e2 I/O Ports (PPORT) .................................................... AP-A-5
0x4000 0300–0x4000 031e Universal Port Multiplexer (UPMUX) ....................... AP-A-11
0x4000 0380–0x4000 0392 UART (UART2) Ch.0 ................................................ AP-A-12
0x4000 03a0–0x4000 03ac 16-bit Timer (T16) Ch.1 ........................................... AP-A-13
0x4000 03b0–0x4000 03be Synchronous Serial Interface (SPIA) Ch.0............... AP-A-14
0x4000 03c0–0x4000 03d6 I2C (I2C) Ch.0 .......................................................... AP-A-15
0x4000 0400–0x4000 041c 16-bit PWM Timer (T16B) Ch.0............................... AP-A-16
0x4000 0440–0x4000 045c 16-bit PWM Timer (T16B) Ch.1............................... AP-A-17
0x4000 0480–0x4000 048c 16-bit Timer (T16) Ch.3 ........................................... AP-A-19
0x4000 0600–0x4000 0612 UART (UART2) Ch.1 ................................................ AP-A-19
0x4000 0680–0x4000 068c 16-bit Timer (T16) Ch.2 ........................................... AP-A-21
0x4000 0690–0x4000 06a8 Quad Synchronous Serial Interface (QSPI) Ch.0..... AP-A-21
0x4000 06c0–0x4000 06d6 I2C (I2C) Ch.1 .......................................................... AP-A-22
0x4000 0700–0x4000 070c Sound Generator (SNDA) ........................................ AP-A-24
0x4000 0720–0x4000 0732 IR Remote Controller (REMC2) ............................... AP-A-24
0x4000 0800–0x4000 0812 LCD Driver (LCD32B) .............................................. AP-A-25
0x4000 0840–0x4000 0850 R/F Converter (RFC) Ch.0 ....................................... AP-A-26
0x2040 0000–0x2040 0104,
0x4000 0970–0x4000 0976 USB 2.0 FS Device Controller (USB, USBMISC) .... AP-A-27
0x4000 0980–0x4000 0986 Supply Voltage Detector (SVD2) Ch.1..................... AP-A-32
0x4000 1000–0x4000 2014 DMA Controller (DMAC) .......................................... AP-A-33
Appendix B Power Saving .......................................................................................... AP-B-1
B.1 Operating Status Configuration Examples for Power Saving...................................... AP-B-1
B.2 Other Power Saving Methods ..................................................................................... AP-B-2
Appendix C Mounting Precautions............................................................................ AP-C-1
Appendix D Measures Against Noise ........................................................................ AP-D-1
Revision History

1 OVERVIEW
S1C31W74 TECHNICAL MANUAL Seiko Epson Corporation 1-1
(Rev. 1.1)
1 Overview
The S1C31W74 is a 32-bit MCU with an Arm®Cortex®-M0+ processor included that features low-power opera-
tion. It incorporates a lot of serial interface circuits and is suitable for various kinds of battery-driven controller ap-
plications.
1.1 Features
Table 1.1.1 Features
Model S1C31W74
CPU
CPU Arm®32-bit RISC processor Cortex®-M0+
Other Serial-wire debug ports (SW-DP) and a micro trace buffer (MTB) included
Embedded Flash memory
Capacity 512K bytes (for both instructions and data)
Erase/program count 1,000 times (min.) *When being programmed by the dedicated flash loader
Other On-board programming function
Flash programming voltage can be generated internally.
Embedded RAMs
General-purpose RAM 128K bytes (shared with MTB)
Display RAM 704 bytes
Instruction cache 512 bytes
DMA Controller (DMAC)
Number of channels 4 channels
Data transfer path Memory to memory, memory to peripheral, and peripheral to memory
Transfer mode Basic, ping-pong, scatter-gather
DMA trigger source UART2, SPIA, QSPI, I2C, USB, T16B, SNDA, and software
Clock generator (CLG)
System clock source 4 sources (IOSC/OSC1/OSC3/EXOSC)
System clock frequency (operating frequency) VD1 voltage mode = mode0: 21 MHz (max.)
VD1 voltage mode = mode1: 2.1 MHz (max.)
IOSC oscillator circuit (boot clock source) VD1 voltage mode = mode0: 20/16/12/8/2/1 MHz (typ.) software selectable
VD1 voltage mode = mode1: 2/1 MHz (typ.) software selectable
10 µs (max.) starting time (time from cancelation of SLEEP state to vector table read
by the CPU)
OSC1 oscillator circuit 32.768 kHz (typ.) crystal oscillator
Oscillation stop detection circuit included
OSC3 oscillator circuit 20.5 MHz (max.) crystal/ceramic oscillator
EXOSC clock input 21 MHz (max.) square or sine wave input
Other Configurable system clock division ratio
Configurable system clock used at wake up from SLEEP state
Operating clock frequency for the CPU and all peripheral circuits is selectable.
I/O port (PPORT)
Number of general-purpose I/O ports 71 bits (max.)
Pins are shared with the peripheral I/O.
Number of input interrupt ports 67 bits (max.)
Number of ports that support universal port
multiplexer (UPMUX)
24 bits
A peripheral circuit I/O function selected via software can be assigned to each port.
Timers
Watchdog timer (WDT2) Generates NMI or watchdog timer reset.
Programmable NMI/reset generation cycle
Real-time clock (RTCA) 128–1 Hz counter, second/minute/hour/day/day of the week/month/year counters
Theoretical regulation function for 1-second correction
Alarm and stopwatch functions
16-bit timer (T16) 4 channels
Generates the SPIA and QSPI master clocks.
16-bit PWM timer (T16B) 2 channels
Event counter/capture function
PWM waveform generation function
Number of PWM output or capture input ports: 2 ports/channel
Supply voltage detector (SVD2)
Number of channels 2 channels
Detection level 32 levels (1.7 to 4.3 V)
Other Intermittent operation mode
Generates an interrupt or reset (Ch.0) according to the detection level evaluation.

1 OVERVIEW
1-2 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL
(Rev. 1.1)
Serial interfaces
UART (UART2) 2 channels
Baud-rate generator included, IrDA1.0 supported
Open drain output, signal polarity, and baud rate division ratio are configurable.
Synchronous serial interface (SPIA) 1 channel
2 to 16-bit variable data length
The 16-bit timer (T16) can be used for the baud-rate generator in master mode.
Quad synchronous serial interface (QSPI) 1 channel
Supports single, dual, and quad transfer modes.
Low CPU overhead memory mapped access mode that can directly read data from
the external flash memory with XIP (eXecute-In-Place) mode.
I2C (I2C) *12 channels
Baud-rate generator included
USB 2.0 FS device controller (USB)
Number of transceiver/receiver channels 1 channel
Transfer rate FS (12 Mbps)
Clock source 48 MHz crystal oscillator or OSC3 (12 MHz) + PLL selectable
Number of endpoints 4 endpoints (3 general-purpose endpoints and endpoint 0)
Power supply Voltage regulators for USB included
Sound generator (SNDA)
Buzzer output function 512 Hz to 16 kHz output frequencies
One-shot output function
Melody generation function Pitch: 128 Hz to 16 kHz ≈C3 to C6
Duration: 7 notes/rests (Half note/rest to thirty-second note/rest)
Tempo: 16 tempos (30 to 480)
Tie/slur may be specified.
IR remote controller (REMC2)
Number of transmitter channels 1 channel
Other EL lamp drive waveform can be generated (by the hardware) for an application
example.
LCD driver (LCD32B)
LCD output 88SEG ×1–16COM (max.), 80SEG ×17–24COM (max.), 72SEG ×25–32COM (max.)
LCD contrast 16 levels
Other 1/5 or 1/4 bias power supply included, external voltage can be applied.
R/F converter (RFC)
Conversion method CR oscillation type with 24-bit counters
Number of conversion channels 1 channel (Up to two sensors can be connected.)
Supported sensors DC-bias resistive sensors, AC-bias resistive sensors
Reset
#RESET pin Reset when the reset pin is set to low.
Power-on reset Reset at power on.
Brownout reset Reset when the power supply voltage drops (when VDD ≤ 1.45 V (typ.) is detected).
Key entry reset Reset when the P00 to P01/P02/P03 keys are pressed simultaneously
(can be enabled/disabled using a register).
Watchdog timer reset Reset when the watchdog timer overflows (can be enabled/disabled using a register).
Supply voltage detector reset Reset when the supply voltage detector detects the set voltage level
(can be enabled/disabled using a register).
Interrupt
Non-maskable interrupt 6 systems (Reset, NMI, HardFault, SVCall, PendSV, SysTic)
Programmable interrupt External interrupt: 1 system
Internal interrupt: 23 systems
Power supply voltage
VDD operating voltage 1.8 to 3.6 V
VDD operating voltage for Flash programming 2.4 to 3.6 V (when VPP is supplied externally)
2.4 to 3.6 V (when VPP is generated internally)
VDD operating voltage when LCD driver is used 2.5 to 3.6 V
Operating temperature
Operating temperature range -40 to 85 °C
Current consumption (Typ. value)
SLEEP mode *20.4 µA
IOSC = OFF, OSC1 = OFF, OSC3 = OFF
0.9 µA
IOSC = OFF, OSC1 = ON, OSC3 = OFF, RTC = ON
HALT mode *31.7 µA
OSC1 = 32 kHz
7.7 µA
OSC1 = 32 kHz, LCD = ON (no panel load)

1 OVERVIEW
S1C31W74 TECHNICAL MANUAL Seiko Epson Corporation 1-3
(Rev. 1.1)
Current consumption (Typ. value)
RUN mode 250 µA/MHz
VD1 voltage mode = mode0, CPU = IOSC
150 µA/MHz
VD1 voltage mode = mode1, CPU = IOSC
Shipping form
1 *4VFBGA8H-181 (P-VFBGA-181-0808-0.50, 8 ×8 mm, t = 1.0 mm, 0.5 mm pitch)
2 Die form (pad pitch: 80 µm (min.))
*1 The input filter in I2C (SDA and SCL inputs) does not comply with the standard for removing noise spikes less than 50 ns.
*2 SLEEP mode refers to deep sleep mode in the Cortex®-M0+ processor. The RAM retains data even in SLEEP mode.
*3 HALT mode refers to sleep mode in the Cortex®-M0+ processor.
*4 Shown in parentheses is a JEITA package name.
1.2 Block Diagram
CPU core, interrpt controller, and debuger
(Cortex®-M0+)
RAM
128K bytes
Display RAM
704 bytes
System clock
Interrupt signal
DMA request signal
SWCLK
SWD
Cache controller
Cache RAM
512 bytes
MTB
16-bit peripheral bus
32-bit AHB bus
IOSC
oscillator
EXOSC
input circuit
Clock generator
(CLG)
Power generator
(PWGA)
VDD
VSS
VD1
RTC1S
SDA0–1
SCL0–1
EXSVD0
VBUS_MON
(EXSVD1)
P00–07
P10–17
P20–27
P30–37
P40–47
P50–57
P60–67
P70–77
P80–81
P90
PD0–D3
FOUT
OSC1
OSC2
OSC3
OSC4
EXOSC
OSC3
oscillator
OSC1
oscillator
I/O port
(PPORT)
Watchdog timer
(WDT2)
Real-time clock
(RTCA)
I2C
(I2C)
2 Ch.
Supply voltage
detector
(SVD2)
2 Ch.
16-bit timer
(T16)
4 Ch.
TOUT00–01
TOUT10–11
CAP00–01
CAP10–11
EXCL00–01
EXCL10–11
16-bit PWM timer
(T16B)
2 Ch.
USB_DP
USB_DM
V
BUS
USB_XI
USB_XO
USB33VOUT
USB18VOUT
V PP
USB 2.0 FS
device controller
(USB)
SDI0
SDO0
SPICLK0
#SPISS0
Synchronous
serial interface
(SPIA)
1 Ch.
QSDIO00–03
QSPICLK0
#QSPISS0
Quad
synchronous
serial interface
(QSPI)
1 Ch.
USIN0–1
USOUT0–1
UART
(UART2)
2 Ch.
Flash memory
512K bytes
DMA controller
REMO
CLPLS
IR remote
controller
(REMC2)
1 Ch.
COM0–31
SEG0–87
LFRO
VC1–5
CP1–5
LCD driver
(LCD32B)
BZOUT
#BZOUT
Sound generator
(SNDA)
R/F converter
(RFC)
1 Ch.
RFIN0
REF0
SENA0
SENB0
RFCLKO0
Power-on reset
(POR)
System reset controller
(SRC)
#RESET
Brownout reset
(BOR)
Figure 1.2.1 S1C31W74 Block Diagram

1 OVERVIEW
1-4 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL
(Rev. 1.1)
1.3 Pins
1.3.1 Pin Configuration Diagram
VFBGA8H-181
Top View Bottom View
A1 Corner A1 Corner
Index A
B
C
D
E
F
G
H
J
K
L
M
N
P
A
B
C
D
E
F
G
H
J
K
L
M
N
P
12345678910 11 12 13 14 14 13 12 11 10 987654321
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
N.C. CP5 CP4 SEG14 SEG19 SEG23 SEG27 SEG31 SEG35 SEG39 SEG44 SEG45 SEG47 N.C.
B
VC3 VC1 CP3 SEG15 SEG18 SEG22 SEG26 SEG30 SEG34 SEG38 SEG43 SEG46 SEG48 SEG50
C
SEG13 VC4 VC2 CP1 SEG17 SEG21 SEG25 SEG29 SEG33 SEG37 SEG42 SEG49 SEG51 SEG52
D
SEG10 P70
SEG9
SEG12 CP2 SEG16 SEG20 SEG24 SEG28 SEG32 SEG36 SEG53 SEG54 SEG55 P67
SEG56
E
P75
SEG4
P73
SEG6
P71
SEG8
SEG11 VC5 VDD VDD VSS SEG40 SEG41 P66
SEG57
P65
SEG58
P64
SEG59
P63
SEG60
F
P81
SEG0
P76
SEG3
P77
SEG2
P72
SEG7
VSS VSS P56
SEG65
P62
SEG61
P61
SEG62
P60
SEG63
P57
SEG64
G
COM12 COM15 COM14 P80
SEG1
P74
SEG5
Top View
P51
SEG70
P55
SEG66
P54
SEG67
P53
SEG68
P52
SEG69
H
COM8 COM11 COM10 COM13 VSS VDD P50
SEG71
P47
COM31
SEG72
P46
COM30
SEG73
P45
COM29
SEG74
J
COM4 COM7 COM6 COM9 VSS P40
COM24
SEG79
P44
COM28
SEG75
P43
COM27
SEG76
P42
COM26
SEG77
P41
COM25
SEG78
K
COM0 COM3 COM2 COM5 VDD VDD P17
RTC1S
UPMUX
P22
QSDIO01
VSS P37
UPMUX
COM23
SEG80
P33
UPMUX
COM19
SEG84
P34
UPMUX
COM20
SEG83
P36
UPMUX
COM22
SEG81
P35
UPMUX
COM21
SEG82
L
USB_XI USB18
VOUT
COM1 VSS VSS P12
EXCL00
UPMUX
P16
CLPLS
UPMUX
P21
QSDIO00
P23
QSDIO02
VDD P27
EXSVD0
P30
LFRO
UPMUX
COM16
SEG87
P32
UPMUX
COM18
SEG85
P31
RFCLKO0
UPMUX
COM17
SEG86
M
USB_XO VSS VBUS VBUS P00
SDI0
UPMUX
VSS P11
#BZOUT
UPMUX
P15
REMO
UPMUX
P20
QSPICLK0
P26
(ENVPP)
EXOSC
SWCLK
PD0
TEST VPP OSC2
N
VSS VSS USB33
VOUT
P90
EXSVD1
(VBUS_
MON)
P01
SDO0
UPMUX
P03
#SPISS0
UPMUX
P05
SENA0
UPMUX
P10
BZOUT
UPMUX
P14
FOUT
UPMUX
P24
EXCL01
QSDIO03
SWD
PD1
VD1 #RESET OSC1
P
N.C. USB_DM USB_DP VSS P02
SPICLK0
UPMUX
P04
SENB0
UPMUX
P06
REF0
UPMUX
P07
RFIN0
UPMUX
P13
EXCL10
UPMUX
P25
EXCL11
#QSPISS0
PD2
OSC3
PD3
OSC4
VSS N.C.
Figure 1.3.1.1 S1C31W74 Pin Configuration Diagram (VFBGA8H-181)

1 OVERVIEW
S1C31W74 TECHNICAL MANUAL Seiko Epson Corporation 1-5
(Rev. 1.1)
1.3.2 Pad Configuration Diagram
4.840 mm
5.480 mm
VC1 VC2 VC3 VC4 VC5
VSS
SEG13 SEG12 SEG11 SEG10
P70 P71 P72 P73 P74 P75 P76 P77 P80 P81
COM15 COM14 COM13 COM12 COM11 COM10
COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0
USB_XI
USB_XO
USB18VOUT USB18VOUT
VBUS
VSS
VC1 VC2 VC3 VC4 VC5
VSS
SEG13 SEG12 SEG11 SEG10
P70/SEG9 P71/SEG8 P72/SEG7 P73/SEG6 P74/SEG5 P75/SEG4 P76/SEG3 P77/SEG2 P80/SEG1 P81/SEG0
COM15 COM14 COM13 COM12 COM11 COM10
COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0
USB_XI
USB_XO
USB18VOUT USB18VOUT
VBUS
VSS
SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 P43 P42 P41 P40 P37 P36 P35 P34 P33 P32 P31 P30 P27 VPP OSC2 OSC1 TEST VDD #RESET
SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 P67/SEG56 P66/SEG57 P65/SEG58 P64/SEG59 P63/SEG60 P62/SEG61 P61/SEG62 P60/SEG63 P57/SEG64 P56/SEG65 P55/SEG66 P54/SEG67 P53/SEG68 P52/SEG69 P51/SEG70 P50/SEG71 P47/COM31/SEG72 P46/COM30/SEG73 P45/COM29/SEG74 P44/COM28/SEG75 P43/COM27/SEG76 P42/COM26/SEG77 P41/COM25/SEG78 P40/COM24/SEG79 P37/UPMUX/COM23/SEG80 P36/UPMUX/COM22/SEG81 P35/UPMUX/COM21/SEG82 P34/UPMUX/COM20/SEG83 P33/UPMUX/COM19/SEG84 P32/UPMUX/COM18/SEG85
P31/RFCLKO0/UPMUX/COM17/SEG86
P30/LFRO/UPMUX/COM16/SEG87 P27/EXSVD0 VPP OSC2 OSC1 TEST VDD #RESET
VSS
VD1
PD3
PD2
PD1
PD0
P26
P25
P24
P23
P22
P21
P20
P17
P16
P15
P14
P13
P12
P11
P10
P07
P06
P05
P04
P03
P02
P01
P00
VDD
VSS
P90
VSS
VBUS
USB33VOUT
USB_DP
VSS
USB_DM
VSS
VD1
PD3/OSC4
PD2/OSC3
SWD/PD1
SWCLK/PD0
P26(ENVPP)/EXOSC
P25/EXCL11/#QSPISS0
P24/EXCL01/QSDIO03
P23/QSDIO02
P22/QSDIO01
P21/QSDIO00
P20/QSPICLK0
P17/RTC1S/UPMUX
P16/CLPLS/UPMUX
P15/REMO/UPMUX
P14/FOUT/UPMUX
P13/EXCL10/UPMUX
P12/EXCL00/UPMUX
P11/#BZOUT/UPMUX
P10/BZOUT/UPMUX
P07/RFIN0/UPMUX
P06/REF0/UPMUX
P05/SENA0/UPMUX
P04/SENB0/UPMUX
P03/#SPISS0/UPMUX
P02/SPICLK0/UPMUX
P01/SDO0/UPMUX
P00/SDI0/UPMUX
VDD
VSS
P90/EXSVD1(VBUS_MON)
VSS
VBUS
USB33VOUT
USB_DP
VSS
USB_DM
Pad
name
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
VDD
CP1
CP2
CP3
CP4
CP5
Port function
or signal
assignment
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
VDD
CP1
CP2
CP3
CP4
CP5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
Y
X
(0, 0)
Die No. CRxxxxxxx
Figure 1.3.2.1 S1C31W74 Pad Configuration Diagram
Pad opening: Pad No. 1–36, 83–127 X = 68 µm, Y = 80 µm
Pad No. 49–78, 128–167 X = 80 µm, Y = 68 µm
Pad No. 37, 38, 81, 82 X = 76 µm, Y = 90 µm
Pad No. 43–45, 79, 80 X = 90 µm, Y = 76 µm
Pad No. 46–48 X = 85 µm, Y = 122 µm
Pad No. 39–42 X = 122 µm, Y = 85 µm
Chip thickness: 400 µm